Introduction to VLSI Design - University of...
Transcript of Introduction to VLSI Design - University of...
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© Digital Integrated Circuits2nd Introduction
Introduction to VLSI Design Introduction to VLSI Design
Instructor: Steven P. Levitan [email protected]: Gayatri Mehta, Jose MartinezBook: Digital Integrated Circuits: A Design Perspective; Jan RabaeyLab Notes: Handed outhttp://infopad.EECS.Berkeley.EDU/~icdesign/
ECE 1192 © 2006, Steven Levitan, University of Pittsburgh
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Course Outline (approximate)Course Outline (approximate)– Introduction and Motivation– The VLSI Design Process– Details of the MOS Transistor– Device Fabrication– Design Rules– CMOS circuits– VLSI Structures– System Timing– Real Circuits and Performance
ECE 1192 © 2006, Steven Levitan, University of Pittsburgh
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Reference BooksReference Books– Digital Integrated Circuits: A Design
Perspective Rabaey et. al– CMOS VLSI Design A Circuits and Systems
Perspective (3rd Edition) Neil Weste and David Harris Addison Wesley
– Introduction to VLSI Circuits and Systems Uyemura
– More – on reserve in the LibraryChen, Smith, Sedra & Smith, etc.
ECE 1192 © 2006, Steven Levitan, University of Pittsburgh
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SoftwareSoftware– Cadence “icfb”
Schematic and Layout editorsUnix BasedSome Auto-Layout generation Batch Design Rule CheckingCircuit Extraction - LVSMany Supported Technology files
– HSPICEBased on well known SPICE (HSPICE is better)Good support/documentationInterface with both schematic and Layout
– Verilog / (later)High level design and evaluationFast functional validationSynthesis from Verilog to circuit to layout
– OthersMicro Magic Max and Sue and Data Path CompilerEtc.
ECE 1192 © 2006, Steven Levitan, University of Pittsburgh
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Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
IntroductionIntroduction
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
July 30, 2002
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What is this book all about?What is this book all about?Introduction to digital integrated circuits.
CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
What will you learn?Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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Digital Integrated CircuitsDigital Integrated CircuitsIntroduction: Issues in digital designThe CMOS inverterCombinational logic structuresSequential logic gatesDesign methodologiesInterconnect: R, L and CTimingArithmetic building blocksMemories and array structures
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IntroductionIntroduction
Why is designing digital ICs different today than it was before?Will it change in future?
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The First ComputerThe First Computer
The BabbageDifference Engine(1832)25,000 partscost: £17,470
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ENIAC ENIAC -- The first electronic computer (1946)The first electronic computer (1946)
Electronic Numerical Integrator and Computer
cost: ~$500,000
17,468 vacuum tubes, 7,200 crystal diodes, 1,500 relays, 70,000 resistors, 10,000 capacitors30 tons8 feet by 3 feet by 100 feet 150 kW of powerI/O via IBM cards
Patch cords, NOT a stored program
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The Transistor RevolutionThe Transistor Revolution
First transistorBell Labs, 1948
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The First Integrated Circuits The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
6 Transistors5 ResistorsTrue and complement outputs
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Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor
19711000 transistors1 MHz operation
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Intel Pentium (IV) microprocessorIntel Pentium (IV) microprocessor
200140M Transistors100MHz (?)
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MooreMoore’’s Laws Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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MooreMoore’’s Laws Law16151413121110
9876543210
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LOG
2 OF
THE
NU
MB
ER O
FC
OM
PON
ENTS
PER
INTE
GR
ATE
D F
UN
CTI
ON
Electronics, April 19, 1965.
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Transistor CountsTransistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
808680286
i386i486
Pentium®Pentium® Pro
K 1 Billion 1 Billion TransistorsTransistors
Source: IntelSource: Intel
ProjectedProjected
Pentium® IIPentium® III
Courtesy, Intel
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MooreMoore’’s law in Microprocessorss law in Microprocessors
400480088080
8085 8086286
386486 Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tran
sist
ors
(MT)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years
Courtesy, Intel
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Die Size GrowthDie Size Growth
40048008
80808085
8086 286386
486 Pentium ® procP6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
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FrequencyFrequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Freq
uenc
y (M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
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Evolution in ComplexityEvolution in Complexity
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Power DissipationPower DissipationP6
Pentium ® proc
486386
2868086
808580808008
4004
0.1
1
10
Pow
er (W
atts
)100
1971 1974 1978 1985Year
1992 2000
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
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Power will be a major problemPower will be a major problem5KW
18KW
1.5KW 500W
4004800880808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Pow
er (W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
Courtesy, Intel
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Power densityPower density
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
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Not Only MicroprocessorsNot Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
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Challenges in Digital DesignChallenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
∝ DSM
?
∝ 1/DSM“Giga = 1/Nano”
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CMOS:Complementary MOSCMOS:Complementary MOS– Means we are using both N-channel and P-
channel type enhancement mode Field Effect Transistors (FETs).
– Field Effect- NO current from the controlling electrode into the output
FET is a voltage controlled current devicevs. BJT (which is a current controlled current device)
– N/P Channel - doping of the substrate for increased carriers (electrons or holes)
ECE 1192 © Steven Levitan University of Pittsburgh
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Silicon DopingSilicon DopingGroup V atoms: Phosphorus or Arsenic, one more electron n-type
Group III atoms: Boron, one less electron p-type
Doping concentrations: 10e-5 (strong) to 10e-8 (weak)
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NN--Channel Enhancement mode Channel Enhancement mode MOS FETMOS FET
– Four Terminal Device - substrate bias
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VLSI:Very Large Scale IntegrationVLSI:Very Large Scale IntegrationIntegration: Integrated Circuits
multiple devices on one substrateHow large is Very Large?
– SSI (small scale integration)7400 series, 10-100 transistors
– MSI (medium scale)74000 series 100-1000
– LSI 1,000-10,000 transistors– VLSI > 10,000 transistors (original definition)– ULSI/SLSI (some disagreement, VLSI > 10M)
ECE 1192 © Steven Levitan University of Pittsburgh
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VLSI DesignVLSI Design– But the real issue is that VLSI is about
designing systems on chips.– The designs are complex, and we need to use
structured design techniques and sophisticated design tools to manage the complexity of the design.
– We also accept the fact that any technology we learn the details of will be out of date soon.
– We are trying to develop and use techniques that will transcend the technology, but still respect it.
ECE 1192 © Steven Levitan University of Pittsburgh
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The Process of VLSI Design:The Process of VLSI Design:Consists of many different representations/Abstractions
of the system (chip) that is being designed.– System Level Design– Architecture / Algorithm Level Design– Digital System Level Design– Logical Level Design– Electrical Level Design– Layout Level Design– Semiconductor Level Design (possibly more)
Each abstraction/view is itself a Design Hierarchy of refinements which decompose the design.
ECE 1192 © Steven Levitan University of Pittsburgh
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Help from Computer Aided Design Help from Computer Aided Design toolstools
ToolsEditorsSimulatorsLibrariesModule SynthesizersPlacers/RoutersChip AssemblersSilicon Compilers
ExpertsLogic designElectronic/circuit designDevice physicsArtworkApplications - system designArchitectures
ECE 1192 © Steven Levitan University of Pittsburgh
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New Design MethodologiesNew Design Methodologies
Methodologies which are based on:System Level Abstractions v.s. Device Characteristic Abstractions
– Logic structures and circuitry change slowly over time
trade-offs do change, but the choices do not
Scalable Designs– Layout techniques also change slowly.
But the minimum feature size steadily decreases with time (also Voltage, Die Size, etc.)
ECE 1192 © Steven Levitan University of Pittsburgh
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TechnologiesTechnologiesBipolar (BJT) dual Junction, current controlled devices
TTL, SchottkyECLI^2 L
Voltage controlled devicesMetal Oxide Silicon Field Effect Transistors (MOS FET)
– NMOS, PMOS (enhancement, depletion)– CMOS <== our course
Single Junction voltage controlled devicesGaAs (typically JFET’s)OEIC’s - MQW’s, Integrated Lasers,?
ECE 1192 © Steven Levitan University of Pittsburgh
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Design ApproachesDesign ApproachesCustom
full control of designbest results, slowest design time.
Semi-custom (std cell)use Cell libraries from vendorcad tools, faster design time
Gate Arrayfastest design timeworst speed/power/densitybest low volume (worst high volume)
EPLA/EPLD - FPGA - electrically programmable (in the field) -
ECE 1192 © Steven Levitan University of Pittsburgh
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Productivity TrendsProductivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./Staff Month.
xxxx
xx
x21%/Yr. compound
Productivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Prod
uctiv
ity(K
) Tra
ns./S
taff
-Mo.
Source: Sematech
Complexity outpaces design productivity
Com
plex
ity
Courtesy, ITRS Roadmap
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Why Scaling?Why Scaling?Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantly (effective area grows by 2x)Cost of a function decreases by 2xBut …
How to design chips with more and more functions?Design engineering population does not double every two years…
Hence, a need for more efficient design methodsExploit different levels of abstraction
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Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Figure 1.2 (p.4) Figure 1.2 (p.4) General overview of General overview of the design the design hierarchy.hierarchy.
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Design MetricsDesign Metrics
How to evaluate performance of a digital circuit (gate, block, …)?
CostAreaReliabilityScalabilitySpeed (delay, operating frequency) Power dissipationEnergy to perform a function
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Cost of Integrated CircuitsCost of Integrated Circuits
NRE (non-recurrent engineering) costsdesign time and effort, mask generationone-time cost factor
Recurrent costssilicon processing, packaging, testproportional to volumeproportional to chip area
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NRE Cost is IncreasingNRE Cost is Increasing
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Die CostDie Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
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Cost per TransistorCost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢¢--perper--transistortransistor
Fabrication capital cost per transistor (Moore’s law)
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YieldYield%100
per wafer chips ofnumber Totalper wafer chips good of No.
×=Y
yield Dieper wafer DiescostWafer cost Die×
=
( )area die2
diameterwafer area die
diameter/2wafer per wafer Dies2
××π
−×π
=
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DefectsDefects
α−⎟⎠⎞
⎜⎝⎛
α×
+=area dieareaunit per defects1yield die
α is approximately 3
4area) (die cost die f=
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Some Examples (1994)Some Examples (1994)Chip Metal
layersLine width
Wafer cost
Def./ cm2
Area mm2
Dies/wafer
Yield Die cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
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ITRS Technology ITRS Technology ““nodesnodes””International Technology Roadmap for Semiconductorshttp://www.itrs.net/
Sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of this industry. --- “Moore’s Law Police”
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Silicon in 2010Silicon in 2010
Voltage: 0.7 - 1.0 VTechnology: 0.045 μmMetal layers: 12-16Clock: 10-15GHzMetal Pitch: 45nmActive length: 30nm/18nm (38/23nm low power)DRAM: 32Gbit on 24x24mm dieLogic Transistors: 6G on 30x30mm diePins: 1,000 – 4,000 (66% Power Pins)Power: 100-200WWafer Size: 12” diameter
Digital Integrated Circuits © Prentice Hall 1995IntroductionIntroductionECE 1192 © Steven Levitan University of Pittsburgh
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““more than Mooremore than Moore””
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SummarySummaryDigital integrated circuits have come a long way and still have quite some potential left for the coming decadesSome interesting challenges ahead
Getting a clear perspective on the challenges and potential solutions is the purpose of this book
Understanding the design metrics that govern digital design is crucial
Cost, reliability, speed, power and energy dissipation
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ReliabilityReliability――Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and groundnoise
v(t) VDD
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DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic
V(x)
V(y)
VOH
VOL
VM
VOHVOL
fV(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)VOL = f(VOH)VM = f(VM)
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Mapping between analog and digital signalsMapping between analog and digital signals
V IL V IH V in
Slope = -1
Slope = -1
V OL
V OH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
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Definition of Noise MarginsDefinition of Noise Margins
Noise margin high
Noise margin low
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
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Noise BudgetNoise Budget
Allocates gross noise margin to expected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed and proportional noise sources
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Key Reliability PropertiesKey Reliability PropertiesAbsolute noise margin values are deceptive
a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)
Noise immunity is the more important metric –the capability to suppress noise sourcesKey metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the receiver;
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Regenerative PropertyRegenerative Property
v0
v1
v3
finv(v)
f (v)
v3
out
v2 in
Non-RegenerativeRegenerativev2
v1
f (v)
finv(v)
v3
out
v0 in
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Regenerative PropertyRegenerative Property
A chain of inverters
v0 v1 v2 v3 v4 v5 v6
2
V (V
olt)
4
v0
v1v2
t (nsec)0
2 1
1
3
5
6 8 10Simulated response
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FanFan--in and Fanin and Fan--outout
N
Fan-out N Fan-in M
M
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The Ideal GateThe Ideal Gate
Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = ∞
V in
V out
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An OldAn Old--time Invertertime Inverter
NM H
V in (V)
V
o u t
( V )
NM L
V M
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
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Delay DefinitionsDelay Definitions
Vout
tf
tpHL tpLH
trt
Vin
t
90%
10%
50%
50%
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Ring OscillatorRing Oscillator
v0 v1 v5
v1 v2v0 v3 v4 v5
T = 2 × tp × N
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A FirstA First--Order RC NetworkOrder RC Network
vout
vin C
R
tp = ln (2) τ = 0.69 RC
Important model – matches delay of inverter
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Power DissipationPower Dissipation
Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
Peak power: Ppeak = Vsupplyipeak
Average power:
( )∫ ∫+ +
==Tt
tTt
t supplysupply
ave dttiT
Vdttp
TP )(1
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Energy and EnergyEnergy and Energy--DelayDelay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp
Energy-Delay Product (EDP) =
quality metric of gate = E × tp
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A FirstA First--Order RC NetworkOrder RC Network
E0 1→ P t( )dt0
T∫ Vdd isupply t( )dt
0
T∫ Vdd CLdVout
0
Vdd
∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt0
T∫ Vouticap t( )dt
0
T∫ CLVoutdVout
0
Vdd∫
12---C
LVdd•
2= = = =
vout
vin CL
R