Introduction To Microelectronics Fabrication Processes LECTURE 3.

Introduction To Microelectronics Fabrication Processes

LECTURE 3

• Foundry (TSMC, UMC, Silterra, 1st Silicon)

– only manufacture

• Design House (Alterra, MyMS)- only design

• Integrated Design Manufacturing (Intel, Motorola, IBM, Mimos)

- design and manufacture

Semiconductor Manufacturing Processes

• Design- Mask info to MASK-SHOP + GDSII

file• Mask making• Generate runcard• Wafer Preparation• Front-end Processes (individual

transistor)- Deposition- Oxidation- Diffusion- Photolithography- Etch (wet and dry)- Implantation

• Backend ProcessDeposition (oxide, nitride etc)MetalizationRapid Thermal ProcessLithography & Etch

• Test (Parametric and Functional)

• Packaging

Pattern PreparationReticle

Chrome Pattern

Quartz Substrate

Pellicle

Wafer Preparation

• Silicon Refining• Crystal Pulling• Wafer Slicing & Polishing• Epitaxial Silicon Deposition

Silicon Refining

Chemical Reactions Silicon Refining: SiO2 + 2 C Si + 2 CO Silicon Purification: Si + 3 HCl HSiCl3 + H2

Silicon Deposition: HSiCl3 + H2 Si + 3 HCl

Reactants H2 Silicon Intermediates H2SiCl2

HSiCl3

Silicon nugget inside crucible

Crystal Pulling

Czochralski Method• Silicon quartzite are melted in quartz crucible• Crucible is placed in high-temperature furnace• Crystal seed is brought into contact with moltensilicon• The puller is slowly pull-up.• Deposited silicon melt condenses and large rounded single crystal is formed

Single Crystal GrowthSingle Crystal Growth

3/15/98 PRAX01C.PPT Rev. 1.0

Wafer Slicing & Polishing

The silicon ingot is grown and individual wafers are sliced.

The silicon ingot is sliced into individual wafers, polished, and cleaned.

silicon wafer

p+ silicon substrate

Wafer PolishedWafer Polished

•Grinding

•Edge Polished

•Slicing

•Lapping

•Polished

•Process Control

Epitaxial Silicon Deposition

GasInput Lamp

Module

QuartzLamps

Wafers

Susceptor

Exhaust

* High proportion of the total product use

Chemical Reactions Silicon Deposition: HSiCl3 + H2 Si + 3 HClProcess Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1,100 degrees C. Pressure: 100 Torr to Atmospheric

silicon wafer

p- silicon epi layer


Dopants AsH3

B2H6

PH3

Etchant HClCarriers Ar H2 * N2

Silicon Sources SiH4

H2SiCl2

HSiCl3 * SiCl4 *

Front-End/Back-end Processes

FOX FOX

N-Well N-Well

Arsenic ImplantLDD

As+ S/D ImplantP-Well

NMOSPMOSCapacitor

FOX FOX

BF2 S/D Implant

BPSG

AlSiCu

Planarisation

Metal 2Passivation

P+ Substrate

Test InsertandScribe-line

Front-end• Fabrication steps up to the formation of individual transistors which electrically isolated

Back-end• Fabrication steps to connect every single transistors until completed

Front-end Process

• OXIDATION

• DIFFUSION

• DEPOSITION

• LITHOGRAPHY

• ION IMPLANTATION

OXIDATION

PURPOSE: TO GROW SILICON OXIDE FILM

WHAT IS OXIDATION?

A PROCESS OF ‘GROWING’ SILICON OXIDE ON A WAFER, EITHER ON BARE SILICON OR EXISTING SILICON OXIDE LAYER

PROCESS EQUATIONS

Si + O2 SiO2 (dry oxidation)Si +2H2O SiO2 + 2H2 (wet oxidation)

O2/H2O DIFFUSE TO SILICON WAFER/OXIDE LAYER AND REACT WITH Si

WHEN REACTION ON SURFACE IS DONE, THICKER FILM WILL REQUIRE THE REACTANT SPECIES TO DIFFUSE DEEPER INTO SILICON (Deal-Groove Linear - Parabolic Model)

GENERALLY AT HIGH TEMPERATURE OF 600 - 1200 ºC.

GASES USED ARE BASICALLY O2, OR H2 AND O2.

DILUTED PROCESS WHERE SMALL AMOUNT OF O2 WITH N2 AS DILUTER TO GET LOWER GROWTH RATE(FOR BETTER CONTROL OF VERY THIN OXIDE)

O2 ALONE IS CALLED DRY OXIDATION

H2 AND O2 IS CALLED WET OXIDATION

FURNACE SYSTEM FOR OXIDATION

VERTICAL FURNACE

FURNACE SYSTEM FOR OXIDATION

HORIZONTAL FURNACE

GAS

SOURCE

QUARTZ DOOR

PADDLE

BOAT

DUMMY WAFERS

DIFFUSION

PURPOSE: TO DRIVE IN DOPANT INTO CERTAIN DEPTH IN SEMICONDUCTOR SUBSTRATE AFTER ION IMPLANTATION PROCESS OR SPIN ON DOPANT TECHNIQUE

DEPOSITION

PURPOSE: TO DEPOSIT MATERIALS SUCH AS NITRIDE, OXIDE, POLYSI ETC

METHODSPECVDLPCVDSACVDPVDEVAPORATION


Polysilicon H2

N2

SiH4 * AsH3 B2H6 PH3

Exhaust ViaVacuum Pumpsand Scrubber

3 ZoneTemperatureControl

Gas Inlet

Vertical LPCVD Furnace

Quartz TubeChemical Reactions Nitride Deposition: 3 SiH4 + 4 NH3 Si3N4 + 12 H2

Polysilicon Deposition: SiH4 Si + 2 H2

Process Conditions (Silicon Nitride LPCVD) Flow Rates: 10 - 300 sccm Temperature: 600 degrees C. Pressure: 100 mTorr

Nitride NH3 * H2SiCl2 * N2

SiH4 * SiCl4

Poly or nitride

p- silicon epi layer


PHOTOLITHOGRAPHY

• A process for producing highly accurate, microscopic, two dimensional patterns in a photosensitive material.

• These patterns are replicas of master pattern on a durable photomask, typically made of a thin patterned layer of chromium on a transparent glass plate.

• The process is repeated many times to build an integrated circuit

SEM

Photolithography Process Flow

Nine basic microlithographic process steps

PRIME

Chill Plate to cool wafer

APPLY RESIST

SOFT BAKE

IMAGING

PEB

DEVELOP

Hard bake

Implant or EtchSEM

Cluster lithocell

Photoresist Patterning

After development

Exposure

silicon

resist

Oxide / nitride

silicon

resist

Photomask

After etch

silicon

resist

Photolithography room

• Photolithography area is yellow-lighted to prevent exposure of photoresist coated wafers to the light.

• It is a class-10 clean room and is the highest level of cleanliness in the clean room suite.

Photoresist Coating Processes

p- epi

p+ substrate

field oxidephotoresist

Photoresists Negative Photoresist * Positive Photoresist *Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials *Developers TMAH * Specialty Developers *Inert Gases Ar N2

Exposure Processes

p- epi

p+ substrate

field oxidephotoresist

Expose Kr + F2 (gas) *

Inert Gases N2

Ion Implantation

• Well Implants• Channel Implants (Vt adjust)• Source/Drain Implants

To introduce impurities into substrate by bombardments of ions

Ion Implantation

180 kV

ResolvingAperture

Ion Source

Equipment Ground

Acceleration Tube

90° Analyzing Magnet

Terminal Ground

20 kV

Focus Neutral beam and beam path gated

Beam trap andgate plate

Wafer in waferprocess chamber

X - axisscanner

Y - axisscanner

Neutral beam trap and beam gate

Gases Ar AsH3

B11F3 * He N2

PH3

SiH4

SiF4

GeH4

Solids Ga In SbLiquids Al(CH3)3


junction depth

p- epi

p+ substrate

field oxide

photoresist mask

n-w ellp-channel transistor

phosphorus (-) ions

Process Conditions Flow Rate: 5 sccm Pressure: 10-5 Torr Accelerating Voltage: 5 to 200 keV

Etch

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly

DesignWaferPreparation

• Conductor Etch

- Poly Etch and Silicon Trench Etch

- Metal Etch

• Dielectric Etch

Conductor Etch


EtchChambers

Cluster ToolConfiguration

TransferChamber

Loadlock

Wafers

RIE Chamber

TransferChamber

Gas Inlet

Exhaust

RF Power

Wafer

p+ substrate

p-w elln-channel transistor


source-drain areas

gate linew idth

gate oxide

Polysilicon Etches HBr * C2F6 SF6 * NF3 * O2

Aluminum Etches BCl3 * Cl2

Diluents Ar He N2

Chemical Reactions Silicon Etch: Si + 4 HBr SiBr4 + 2 H2 Aluminum Etch: Al + 2 Cl2 AlCl4

Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 mTorr RF Power: 50 to 100 Watts

Dielectric Etch


EtchChambers


TransferChamber

Loadlock

Wafers

RIE Chamber

TransferChamber

Gas Inlet

Exhaust

RF Power

Wafer

Contact locations



p+ substrate

Chemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flow Rates: 10 to 300 sccm Pressure: 5 to 10 mTorr RF Power: 100 to 200 Watts

Plasma Dielectric Etches CHF3 * CF4

C2F6

C3F8

CO *

Diluents Ar He N2

CO2

O2

SF6

SiF4

Cleaning

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


• Critical Cleaning

• Photoresist Strips

• Pre-Deposition Cleans

Critical Cleaning

11 22 33 44 55

1 O r g a n i c s 2 O x i d e s 3 P a r t i c l e s 4 M e t a l s 5 D r yH 2 S O 4 + H F + N H 4 O H + H C l + H 2 O o r I P A +H 2 O 2 H 2 O H 2 O 2 + H 2 O H 2 O 2 + H 2 O N 2

H 2 O R i n s e H 2 O R i n s e H 2 O R i n s e H 2 O R i n s e

Contact locations



p+ substrate

RCA Clean SC1 Clean (H2O + NH4OH + H2O2) * * SC2 Clean (H2O + HCl + H2O2) *

Piranha Strip * H2SO4 + H2O2 *

Nitride Strip H3PO4 *

Oxide Strip HF + H2O *

Solvent Cleans NMP Proprietary Amines (liquid)Dry Cleans HF O2 Plasma Alcohol + O3

Dry Strip N2O O2

CF4 + O2

O3

Process Conditions Temperature: Piranha Strip is 180 degrees C.

Back-end Process

• CVD Dielectrics• CVD Tungsten• PVD Metal• Planarization

• local (deposit-etch)• global (CMP)

Thin Films

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly

DesignWaferPreparation• Chemical Vapor Deposition

(CVD) Dielectric

• CVD Tungsten

• Physical Vapor Deposition (PVD)

• Chamber Cleaning

Chemical Vapor Deposition (CVD) Dielectric


CVD Dielectric O2

O3

TEOS * TMP *

TEOSSource

LPCVDChamber

TransferChamber

Gas Inlet

Exhaust

RF Power

Wafer

MeteringPump

Inert MixingGas

Process Gas

Vaporizer

DirectLiquid

Injection



p+ substrate

Metal 1insulator layer 2

Chemical Reactions Si(OC2H5)4 + 9 O3 SiO2 + 5 CO + 3 CO2 + 10 H2OProcess Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric

Chemical Vapor Deposition (CVD) Tungsten


CVD Dielectric WF6 * Ar H2

N2

OutputCassette

InputCassette

WaferHander

Wafers

Water-cooledShowerheads

Multistation SequentialDeposition Chamber

ResistivelyHeated Pedestal



p+ substrate

titanium tungsten

Chemical Reactions WF6 + 3 H2 W + 6 HFProcess Conditions Flow Rate: 100 to 300 sccm Pressure: 100 mTorr Temperature: 400 degrees C.

Physical Vapor Deposition (PVD)

Barrier Metals SiH4

Ar N2

N2

Ti PVD Targets *

PhysicalVaporDepositionChambers


TransferChamber

Loadlock

Wafers

PVD Chamber

TransferChamber

Cryo Pump

Wafer

N S N

+

e -

BacksideHe Cooling

Argon &Nitrogen

ReactiveGases

DC PowerSupply (+)




p+ substrate

Process Conditions Pressure: < 5 mTorr Temperature: 200 degrees C. RF Power:

Chamber Cleaning


Chamber Cleaning C2F6 * NF3

ClF3

Water-cooledShowerheads

Multistation SequentialDeposition Chamber

ResistivelyHeated Pedestal

Chemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flow Rates: 10 to 300 sccm Pressure: 10 to 100 mTorr RF Power: 100 to 200 Watts

Aluminum

Surface Coating

Process Material Residue

Chamber Wall Cross-Section

Planarization

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


• Oxide Planarization

• Metal Planarization

Chemical Mechanical Planarization (CMP)

* High proportion of the total product use.

Platen

PolishingHead

PadConditioner

Carousel

HeadSweep Slide

Load/UnloadStation

Wafer HandlingRobot & I/O

Polishing PadSlurryDelivery

Platen

WaferCarrier

Wafer



p+ substrate

Backing (Carrier) Film PolyurethanePad PolyurethanePad Conditioner Abrasive

CMP (Oxide) Silica Slurry KOH * NH4OH H2O

CMP (Metal) Alumina * FeNO3

Process Conditions (Oxide) Flow: 250 to 1000 ml/min Particle Size: 100 to 250 nm Concentration: 10 to 15%, 10.5 to 11.3 pHProcess Conditions (Metal) Flow: 50 to 100 ml/min Particle Size: 180 to 280 nm Concentration: 3 to 7%, 4.1 - 4.4 pH

*

Test and Assembly

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIonImplantation

Planarization

Test &Assembly


• Electrical Test Probe

• Die Cut and Assembly

• Die Attach and Wire Bonding

• Final Test

Electrical Test Probe

Defective IC

Individual integrated circuits are tested to distinguish good

die from bad ones.

n-wellp-channel transistor

p-welln-channel transistor

p+ substrate

bonding padnitride

Metal 2

Die Cut and Assembly

Good chips are attached to a lead frame package.

Die Attach and Wire Bonding

lead frame gold wire

bonding pad

connecting pin

Final Test

Chips are electrically tested under varying environmental conditions.

References

1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997.

2. Semiconductor Processing with MKS Instruments, Inc.

3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State Technology, January 1996.

4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.

5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.

6. CVD Tungsten, Novellus Sales Brochure, 7/96.

7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process,” http://www.fullman.com/semiconductors/index.html, 1997.

8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific American Special Issue: The Solid State Century, January 22, 1998.

Introduction To Microelectronics Fabrication Processes LECTURE 3.

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