Interfacing I/O devices Interfacing I/O devices and peripheralsand peripherals

Addressing schemes:

i) Memory-mapped I/Oii) I/O mapped I/O.

Memory mapped I/O Memory mapped I/O

• An I/O device is treated as a memory location; An I/O device is treated as a memory location; hence a 16-bit address is assigned to it. hence a 16-bit address is assigned to it.

• In memory mapped I/O all data transfer instructions of In memory mapped I/O all data transfer instructions of µP are applicable to memory as well as I/O devices. µP are applicable to memory as well as I/O devices.

• Thus, if instruction MOV M, A is used, it will transfer Thus, if instruction MOV M, A is used, it will transfer the data from accumulator to an address given by the the data from accumulator to an address given by the register pair HL. If the memory pointer points to the register pair HL. If the memory pointer points to the address that pertains to memory device the content of address that pertains to memory device the content of accumulator will be transfer to that memory location. accumulator will be transfer to that memory location. However, if this pertains to I/O device the content of However, if this pertains to I/O device the content of accumulator will be transfer to that I/O device alone. accumulator will be transfer to that I/O device alone. Memory mapped I/O can be used in all µP system.Memory mapped I/O can be used in all µP system.

• I/O devices are accessed by memory READ-WRITE I/O devices are accessed by memory READ-WRITE cycles cycles

I/O mapped I/OI/O mapped I/O

• I/O devices are treated as distinct form memory I/O devices are treated as distinct form memory devices.devices.

• To identify the I/O device µP has to send a proper To identify the I/O device µP has to send a proper control signal on I/O line along with the 8-bit port control signal on I/O line along with the 8-bit port address. address.

• In this scheme the CPU uses instructions like IN 8-In this scheme the CPU uses instructions like IN 8-bit port addr or OUT 8-bit port addr for I/O bit port addr or OUT 8-bit port addr for I/O Read/Write operations. Read/Write operations.

• The main disadvantage of this scheme is the The main disadvantage of this scheme is the timing incompatibility of the I/O devices with the timing incompatibility of the I/O devices with the µP, some times it leads to interfacing problemsµP, some times it leads to interfacing problems

• I/O mapping is done by I/O READ-WRITE cycles.I/O mapping is done by I/O READ-WRITE cycles.

Comparison between Memory Mapping and I/O Mapping

Memory Mapping I/O mapping1. The device is accessed by memory

read or write cycle2. 16-bit addresses are provided for

I/O devices3. The I/O port or peripheral can be

treated as memory location so all the instructions related to memory can be used for data transfer between I/O device and the µP.

4. The data can be transferred from any register to port and vice-versa.

5. In memory mapping a large number of I/O ports can be interfaced.

6. Memory mapping is used for small systems, where the memory requirement is less.

1. The device is accessed by I/O read or write cycle

2. 8-bit addresses are provided for I/O devices

3. In I/O mapping IN and OUT instructions are used for data transfer between I/O device and the µP.

4. The data transfer can take place only between accumulator and the ports.

5. In I/O mapping only 256 I/O ports can be interfaced

6. I/O mapping is suitable for large systems, where the memory requirement is large.

Memory interfacing:Memory interfacing:

• In a microprocessor based system the memory devices In a microprocessor based system the memory devices (EPROM/ RAM) {and I/O devices} are also important as the (EPROM/ RAM) {and I/O devices} are also important as the CPU itself, because memory is the device where the system CPU itself, because memory is the device where the system program and data resides. While executing a program, the program and data resides. While executing a program, the microprocessor needs to access memory quite frequently to microprocessor needs to access memory quite frequently to read instruction codes and to read / write data. So we need read instruction codes and to read / write data. So we need to interface memory devices to the microprocessor. to interface memory devices to the microprocessor.

• 8085 Microprocessor has total 16 address lines, therefore it 8085 Microprocessor has total 16 address lines, therefore it can access (address) 64K bytes of memory. The term can access (address) 64K bytes of memory. The term “Memory Interfacing” means, to “PLACE” available memory “Memory Interfacing” means, to “PLACE” available memory chip (2K, 4K, 8K or 16K – EPROM or RAM) within 64K bytes chip (2K, 4K, 8K or 16K – EPROM or RAM) within 64K bytes address range. This is also referred to as “Mapping”. address range. This is also referred to as “Mapping”.

• Mapping decides “Address” of the memory component.Mapping decides “Address” of the memory component.

For interfacing memory devices to 8085 microprocessor, For interfacing memory devices to 8085 microprocessor, following steps are to be kept in mind:following steps are to be kept in mind:

1.1. 8085 microprocessor can access 64K bytes of memory, since its address bus is 16-8085 microprocessor can access 64K bytes of memory, since its address bus is 16-bit. But it is not always necessary to use full 64K bytes of address range. The total bit. But it is not always necessary to use full 64K bytes of address range. The total memory size depends upon the application.memory size depends upon the application.

2.2. Generally EPROM(s) is used as a program memory and RAM(s) as a data memory and Generally EPROM(s) is used as a program memory and RAM(s) as a data memory and total address space is shared by both.total address space is shared by both.

3.3. The size of the program memory and data memory depends on the type of The size of the program memory and data memory depends on the type of application.application.

4.4. It is not necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and It is not necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and RAMs as per requirement.RAMs as per requirement.

5.5. We can place EPROM/ RAM anywhere in full 64K bytes of address space. But at least We can place EPROM/ RAM anywhere in full 64K bytes of address space. But at least one program memory (EPROM) should be located from address 0000H, since RESET one program memory (EPROM) should be located from address 0000H, since RESET address of 8085 microprocessor is 0000H.address of 8085 microprocessor is 0000H.

6.6. It is not necessary to locate EPROM and RAM in consecutive memory address.It is not necessary to locate EPROM and RAM in consecutive memory address.7.7. Wherever we place memory, but we have to decide address for the same. Address Wherever we place memory, but we have to decide address for the same. Address

must be 16-bit.must be 16-bit.8.8. A memory chip of given size can be address with different addresses.A memory chip of given size can be address with different addresses.9.9. Once the address is finalized, we have to use a digital circuit, which is normally Once the address is finalized, we have to use a digital circuit, which is normally

referred to as “Decoder Logic”, to decode address and locate a desired memory referred to as “Decoder Logic”, to decode address and locate a desired memory register. Decoder logic is nothing but a combinational logic circuit. One can use Logic register. Decoder logic is nothing but a combinational logic circuit. One can use Logic gates or 3:8 decoder (IC 74LS138) to built or design Decoder Logic. Generally 3:8 gates or 3:8 decoder (IC 74LS138) to built or design Decoder Logic. Generally 3:8 decoders is preferred in 8085 microprocessor base systems for decoder logic, since it decoders is preferred in 8085 microprocessor base systems for decoder logic, since it reduces hardware and with one decoder circuit we can select 8 different chips.reduces hardware and with one decoder circuit we can select 8 different chips.

To understand decoder logic let us take an example:

Example: Interface a 4K X 8 RAM to 8085 microprocessor with starting address C000H.

4K memory requires 12 address lines, 2 12 = 4096

Step – 1 : Memory size is 4K. Thus total address lines required will be A11 – A0

and remaining 4 lines A15 – A12 can be used for decoder logic (chip

select logic)

Step – 2 : Address range for 4K RAM starting from C000H will be

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000HStarting Address

1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 CFFFHEnd Address(Size = 4K)

← Used by →decoder logic

← Directly given to memory chip →

CS A15 – A12 are to be used for decoder logic (- chip select logic). Since CS

3 : 8Decoder 72138

0

1

2

3

4

5

6

7

A

B

C

A12

A13

A14

G1G2AG2B

A15

CS

Step – 3 : A15 – A12 lines are to be used for decoder logic ( chip select logic). Since chip select of RAM is active low, A15 – A12 = (1100)2 – when given to decoder, decoder output should go LOW and for any other value of A15 – A12 decoder output should be HIGH.

Step – 4 : Below given figure shows one of the way to implement Step – 3.

3 : 8Decoder 72138

Basic 8085 p

0

1

2

3

4

5

6

7

A

B

C

MEMW

MEMR

A12

A13

A14

A15

A11 - A8

A7 - A0

D7 - D04K X 8 RAM

CS RD WR

G1G2AG2B

8 Lines A7 - A0

8 Lines

4 Lines

D7 - D0

A11 - A8

Step – 5 : Interfacing 4K X 8 RAM to 8085 μP with starting address C000H will be as shown

Absolute decoding:

To address (interface) a memory of given size, required number of address lines are directly connected to memory chip and remaining all the high order address lines are used for designing decoder logic (chip select logic). Due to this, memory Chip is selected only when a specific (unique) bit pattern (address) appears on the address lines. Therefore this type of decoding technique is referred to as “Absolute Decoding or Full Decoding”.

Absolute decoding is preferred in microprocessor based system where memory size is large.

Linear or Partial Decoding:Linear or Partial Decoding: In small microprocessor based systems wherein the memory In small microprocessor based systems wherein the memory

size is small we don’t required all 16 address lines to address a size is small we don’t required all 16 address lines to address a desired memory location. So if few address lines are not used it desired memory location. So if few address lines are not used it will work. Unused address lines are labeled as don’t care (X) will work. Unused address lines are labeled as don’t care (X) lines. Simply ignoring few address lines in decoding technique lines. Simply ignoring few address lines in decoding technique is referred to as “Partial or Linear Decoding”. is referred to as “Partial or Linear Decoding”.

But due to this we come across very interesting phenomena But due to this we come across very interesting phenomena normally referred as normally referred as ““Shadows of memory or Folded memory”.”.

In partial decoding the same memory can be addressed by In partial decoding the same memory can be addressed by multiple addresses called Shadow addresses. Once the shadow multiple addresses called Shadow addresses. Once the shadow address is finalized and if we want to map one more memory address is finalized and if we want to map one more memory chip, then we have to take a precaution that there is no chip, then we have to take a precaution that there is no overlapping of addresses including shadow addresses. overlapping of addresses including shadow addresses.

Advantage of partial decoding is –Advantage of partial decoding is – hardware for decoding logic hardware for decoding logic can be reduced or can be eliminated. It reduces the cost of can be reduced or can be eliminated. It reduces the cost of decoding circuit.decoding circuit.

Comparison between absolute decoding and partial decoding:

Absolute (Full) decoding Partial (Linear) decoding

1. All higher address lines are used in decoding logic to select the memory or I/O device

2. More hardware is required to design decoder logic

3. Higher cost for decoding circuit4. No multiple addresses5. Used in large systems.

1. Few high order address lines are ignored in decoder logic to select memory or I/O device.

2. Hardware required to design decoder logic is small or it can be eliminated

3. Low cost for decoding circuit4. Disadvantage of multiple

addressing (Shadow or folded addresses)

5. Used in small systems.