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Intel® Agilex™ Hard ProcessorSystem Technical Reference Manual

Updated for Intel® Quartus® Prime Design Suite: 19.3

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MNL-1100 | 2019.09.30Latest document on the web: PDF | HTML

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Contents

1. Intel® Agilex™ Hard Processor System Technical Reference Manual Revision History... 12

2. Introduction to the Hard Processor System.................................................................. 182.1. Features of the HPS............................................................................................. 192.2. HPS Block Diagram and System Integration.............................................................20

2.2.1. HPS Block Diagram.................................................................................. 202.2.2. Cortex-A53 MPCore Processor....................................................................212.2.3. Cache Coherency Unit.............................................................................. 212.2.4. System Memory Management Unit............................................................. 222.2.5. HPS Interfaces........................................................................................ 232.2.6. System Interconnect................................................................................ 232.2.7. On-Chip RAM...........................................................................................242.2.8. Flash Memory Controllers..........................................................................242.2.9. System Modules...................................................................................... 252.2.10. Interface Peripherals...............................................................................272.2.11. CoreSight Debug and Trace..................................................................... 302.2.12. Hard Processor System I/O Pin Multiplexing...............................................31

2.3. Endian Support....................................................................................................312.4. Introduction to the Hard Processor System Address Map........................................... 31

3. Cortex-A53 MPCore Processor...................................................................................... 323.1. Features of the Cortex-A53 MPCore........................................................................ 323.2. Advantages of Cortex-A53 MPCore......................................................................... 333.3. Cortex-A53 MPCore Block Diagram......................................................................... 343.4. Cortex-A53 MPCore System Integration.................................................................. 343.5. Cortex-A53 MPCore Functional Description.............................................................. 35

3.5.1. Exception Levels...................................................................................... 353.5.2. Virtualization...........................................................................................373.5.3. Memory Management Unit.........................................................................383.5.4. Level 1 Caches........................................................................................ 403.5.5. Level 2 Memory System............................................................................433.5.6. Snoop Control Unit...................................................................................433.5.7. Cryptographic Extensions..........................................................................433.5.8. NEON Multimedia Processing Engine........................................................... 443.5.9. Floating Point Unit....................................................................................453.5.10. ACE Bus Interface.................................................................................. 453.5.11. Abort Handling.......................................................................................463.5.12. Cache Protection.................................................................................... 463.5.13. Generic Interrupt Controller.....................................................................483.5.14. Generic Timers...................................................................................... 543.5.15. Debug Modules...................................................................................... 553.5.16. Cache Coherency Unit.............................................................................573.5.17. Clock Sources........................................................................................58

3.6. Cortex-A53 MPCore Programming Guide................................................................. 583.6.1. Enabling Cortex-A53 MPCore Clocks........................................................... 583.6.2. Bringing the Cortex-A53 MPCore out of Reset.............................................. 593.6.3. Enabling and Disabling Cache.................................................................... 593.6.4. Entering Low Power Modes........................................................................ 59

Contents

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3.7. Cortex-A53 MPCore Address Map .......................................................................... 59

4. Cache Coherency Unit................................................................................................... 604.1. Supported Features..............................................................................................614.2. Functional Description.......................................................................................... 61

4.2.1. Connectivity............................................................................................634.2.2. System Integration.................................................................................. 654.2.3. Reset and Initialization............................................................................. 664.2.4. Discovery Routine.................................................................................... 664.2.5. Operational State.....................................................................................664.2.6. Maintenance Operations............................................................................664.2.7. Error Handling.........................................................................................664.2.8. OCRAM Firewall....................................................................................... 67

4.3. Cache Coherency Unit Transactions........................................................................ 684.3.1. Command Mapping.................................................................................. 69

4.4. Cache Coherency Unit Address Map and Register Definitions......................................70

5. System Memory Management Unit................................................................................ 715.1. System Memory Management Unit Features............................................................ 715.2. System MMU Block Diagram.................................................................................. 72

5.2.1. System Memory Management Unit Interfaces.............................................. 735.3. System Integration.............................................................................................. 735.4. System Memory Management Unit Functional Description..........................................74

5.4.1. Translation Stages....................................................................................755.4.2. Exception Levels...................................................................................... 755.4.3. Translation Regimes................................................................................. 765.4.4. Translation Buffer Unit.............................................................................. 765.4.5. Translation Control Unit............................................................................ 775.4.6. Security State Determination.....................................................................775.4.7. Stream ID...............................................................................................785.4.8. Quality of Service Arbitration.....................................................................795.4.9. System Memory Management Unit Interrupts.............................................. 795.4.10. System Memory Management Unit Reset...................................................805.4.11. System Memory Management Unit Clocks..................................................80

5.5. System Memory Management Unit Configuration......................................................805.6. System Memory Management Unit Address Map and Register Definitions.....................81

6. System Interconnect.....................................................................................................826.1. Functional Description.......................................................................................... 82

6.1.1. Masters and Slaves Connectivity Matrix.......................................................846.1.2. Secure Transaction Protection....................................................................906.1.3. Rate Adapter...........................................................................................956.1.4. Arbitration and Quality of Service...............................................................956.1.5. Observation Network................................................................................96

6.2. System Interconnect Clocks.................................................................................. 986.3. System Interconnect Resets.................................................................................. 996.4. System Interconnect Address Spaces....................................................................100

6.4.1. L3 Address Space...................................................................................1006.4.2. MPU Address Space................................................................................ 1046.4.3. SoC-to-FPGA Bridge Address Space.......................................................... 1046.4.4. Peripheral Region Address Map.................................................................105

6.5. System Interconnect Address Map and Register Definitions......................................107

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7. HPS Bridges................................................................................................................ 1087.1. Features of the HPS Bridges................................................................................ 1087.2. HPS Bridges Block Diagram................................................................................. 1097.3. FPGA-to-SoC Bridge........................................................................................... 109

7.3.1. FPGA-to-SoC Bridge Signals.....................................................................1107.4. SoC-to-FPGA Bridge........................................................................................... 111

7.4.1. SoC-to-FPGA Bridge Signals.....................................................................1117.5. Lightweight SoC-to-FPGA Bridge.......................................................................... 112

7.5.1. Lightweight SoC-to-FPGA Bridge Signals....................................................1137.6. Clocks and Resets.............................................................................................. 113

7.6.1. FPGA-to-SoC Bridge Clocks and Resets......................................................1137.6.2. SoC-to-FPGA Bridge Clocks and Resets......................................................1137.6.3. Lightweight SoC-to-FPGA Bridge Clocks and Resets.....................................1147.6.4. Taking HPS Bridges Out of Reset ............................................................. 114

7.7. Data Width Sizing.............................................................................................. 1147.8. HPS Bridges Address Map and Register Definitions..................................................114

8. DMA Controller............................................................................................................1158.1. Features of the DMA Controller............................................................................ 1158.2. DMA Controller Block Diagram ............................................................................ 117

8.2.1. Distributed Virtual Memory Support.......................................................... 1188.3. Functional Description of the DMA Controller..........................................................118

8.3.1. Error Checking and Correction.................................................................1198.3.2. Peripheral Request Interface....................................................................120

8.4. DMA Controller Address Map and Register Definitions..............................................121

9. On-Chip RAM...............................................................................................................1229.1. Features of the On-Chip RAM...............................................................................1229.2. On-Chip RAM Interfaces......................................................................................1229.3. Functional Description of the On-Chip RAM............................................................ 123

9.3.1. Read and Write Double-Bit Bus Errors....................................................... 1239.3.2. On-Chip RAM Controller.......................................................................... 1239.3.3. On-Chip RAM Burst Support.....................................................................1239.3.4. Exclusive Access Support........................................................................ 1249.3.5. Sub-word Accesses.................................................................................1249.3.6. On-Chip RAM Clocks............................................................................... 1249.3.7. On-Chip RAM Resets...............................................................................1249.3.8. On-Chip RAM Initialization.......................................................................1259.3.9. ECC Protection ......................................................................................125

9.4. On-Chip RAM Address Map and Register Definitions................................................ 125

10. Error Checking and Correction Controller..................................................................12610.1. ECC Controller Features.................................................................................... 12610.2. ECC Supported Memories.................................................................................. 12610.3. ECC Controller Block Diagram and System Integration...........................................12710.4. ECC Controller Functional Description..................................................................128

10.4.1. Overview.............................................................................................12810.4.2. ECC Structure...................................................................................... 12810.4.3. Memory Data Initialization.....................................................................13010.4.4. Indirect Memory Access.........................................................................13110.4.5. Error Logging.......................................................................................138

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10.4.6. ECC Controller Interrupts...................................................................... 14010.4.7. ECC Controller Initialization and Configuration..........................................14410.4.8. ECC Controller Clocks............................................................................14510.4.9. ECC Controller Reset.............................................................................145

10.5. ECC Controller Address Map and Register Descriptions.......................................... 146

11. Clock Manager.......................................................................................................... 14711.1. Features of the Clock Manager........................................................................... 14711.2. Top Level Clocks...............................................................................................149

11.2.1. Boot Clock...........................................................................................15111.3. Functional Description of the Clock Manager.........................................................151

11.3.1. Clock Manager Building Blocks............................................................... 15111.3.2. PLL Integration.................................................................................... 15211.3.3. Hardware-Managed and Software-Managed Clocks....................................15311.3.4. Hardware Sequenced Clock Groups.........................................................15311.3.5. Software Sequenced Clocks................................................................... 15511.3.6. Resets................................................................................................ 15711.3.7. Security.............................................................................................. 15811.3.8. Interrupts............................................................................................158

11.4. Clock Manager Address Map and Register Definitions.............................................158

12. Reset Manager.......................................................................................................... 15912.1. Functional Description.......................................................................................16012.2. Modules Under Reset........................................................................................ 16312.3. Reset Handshaking...........................................................................................16312.4. Reset Sequencing.............................................................................................164

12.4.1. Warm Reset Sequence.......................................................................... 16512.4.2. Watchdog Reset Sequence.....................................................................165

12.5. Reset Signals and Registers............................................................................... 16612.6. Reset Manager Address Map and Register Definitions............................................ 167

13. System Manager....................................................................................................... 16813.1. Features of the System Manager........................................................................ 16813.2. System Manager Block Diagram......................................................................... 16913.3. Functional Description of the System Manager......................................................170

13.3.1. Additional Module Control...................................................................... 17013.3.2. FPGA Interface Enables......................................................................... 17313.3.3. ECC and Parity Control.......................................................................... 17313.3.4. Preloader Handoff Information............................................................... 17413.3.5. Clocks.................................................................................................17413.3.6. Resets................................................................................................ 174

13.4. System Manager Address Map and Register Definitions..........................................174

14. Hard Processor System I/O Pin Multiplexing............................................................ 17514.1. Features of the Intel Agilex HPS I/O Block........................................................... 17514.2. Intel Agilex HPS I/O System Integration.............................................................. 17614.3. Functional Description of the HPS I/O..................................................................176

14.3.1. I/O Pins.............................................................................................. 17614.3.2. FPGA Access........................................................................................ 17614.3.3. Intel Agilex I/O Control Registers............................................................17714.3.4. Configuring HPS I/O Multiplexing............................................................180

14.4. Intel Agilex Pin MUX Test Considerations..............................................................180

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14.5. Intel Agilex I/O Pin MUX Address Map and Register Definitions............................... 180

15. NAND Flash Controller ............................................................................................. 18215.1. NAND Flash Controller Features .........................................................................18215.2. NAND Flash Controller Block Diagram and System Integration ............................... 183

15.2.1. Distributed Virtual Memory Support ....................................................... 18315.3. NAND Flash Controller Signal Descriptions .......................................................... 18415.4. Functional Description of the NAND Flash Controller ............................................. 185

15.4.1. Discovery and Initialization ................................................................... 18515.4.2. Bootstrap Interface ..............................................................................18715.4.3. Configuration by Host .......................................................................... 18715.4.4. Local Memory Buffer ............................................................................ 18815.4.5. Clocks ................................................................................................18815.4.6. Resets ............................................................................................... 18915.4.7. Indexed Addressing ............................................................................. 19015.4.8. Command Mapping ..............................................................................19115.4.9. Data DMA ...........................................................................................19615.4.10. ECC ................................................................................................. 200

15.5. NAND Flash Controller Programming Model.......................................................... 20315.5.1. Basic Flash Programming ......................................................................20315.5.2. Flash-Related Special Function Operations .............................................. 208

15.6. NAND Flash Controller Address Map and Register Definitions ................................. 217

16. SD/MMC Controller................................................................................................... 21816.1. Features of the SD/MMC Controller .................................................................... 218

16.1.1. Device Support ................................................................................... 21916.1.2. SD Card Support Matrix ........................................................................22016.1.3. MMC Support Matrix ............................................................................ 220

16.2. SD/MMC Controller Block Diagram ..................................................................... 22116.2.1. Distributed Virtual Memory Support ....................................................... 221

16.3. SD/MMC Controller Signal Description ................................................................ 22216.4. Functional Description of the SD/MMC Controller ................................................. 223

16.4.1. SD/MMC/CE-ATA Protocol ..................................................................... 22316.4.2. BIU ................................................................................................... 22416.4.3. CIU ................................................................................................... 23616.4.4. Clocks ................................................................................................25216.4.5. Resets ............................................................................................... 25316.4.6. Voltage Switching ................................................................................ 254

16.5. SD/MMC Controller Programming Model ..............................................................25616.5.1. Software and Hardware Restrictions† ......................................................25616.5.2. Initialization........................................................................................ 25816.5.3. Controller/DMA/FIFO Buffer Reset Usage ................................................ 26516.5.4. Non-Data Transfer Commands ...............................................................26616.5.5. Data Transfer Commands ..................................................................... 26716.5.6. Transfer Stop and Abort Commands ....................................................... 27416.5.7. Internal DMA Controller Operations ........................................................27516.5.8. Commands for SDIO Card Devices ......................................................... 27816.5.9. CE-ATA Data Transfer Commands ...........................................................28016.5.10. Card Read Threshold .......................................................................... 28816.5.11. Interrupt and Error Handling ............................................................... 29116.5.12. Booting Operation for eMMC and MMC .................................................. 292

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16.6. SD/MMC Controller Address Map and Register Definitions.......................................304

17. Ethernet Media Access Controller .............................................................................30517.1. Features of the Ethernet MAC ............................................................................306

17.1.1. MAC .................................................................................................. 30617.1.2. DMA .................................................................................................. 30717.1.3. Management Interface ......................................................................... 30717.1.4. Acceleration ........................................................................................30717.1.5. PHY Interface ......................................................................................307

17.2. EMAC Block Diagram and System Integration ......................................................30817.3. Distributed Virtual Memory Support ................................................................... 30917.4. EMAC Signal Description ...................................................................................310

17.4.1. HPS EMAC I/O Signals ..........................................................................31117.4.2. FPGA EMAC I/O Signals ....................................................................... 31517.4.3. PHY Management Interface ...................................................................31617.4.4. PHY Interface Options .......................................................................... 317

17.5. EMAC Internal Interfaces ..................................................................................31817.5.1. DMA Master Interface .......................................................................... 31817.5.2. Timestamp Interface ............................................................................31917.5.3. System Manager Configuration Interface ................................................ 320

17.6. Functional Description of the EMAC .................................................................... 32117.6.1. Transmit and Receive Data FIFO Buffers ................................................. 32217.6.2. DMA Controller ....................................................................................32317.6.3. Descriptor Overview .............................................................................33617.6.4. IEEE 1588-2002 Timestamps ................................................................ 34817.6.5. IEEE 1588-2008 Advanced Timestamps ..................................................35417.6.6. IEEE 802.3az Energy Efficient Ethernet ...................................................35817.6.7. Checksum Offload ............................................................................... 35917.6.8. Frame Filtering ....................................................................................35917.6.9. Clocks and Resets ................................................................................36417.6.10. Interrupts .........................................................................................367

17.7. Ethernet MAC Programming Model .....................................................................36717.7.1. System Level EMAC Configuration Registers ............................................ 36717.7.2. EMAC FPGA Interface Initialization ......................................................... 36917.7.3. EMAC HPS Interface Initialization ...........................................................37017.7.4. DMA Initialization ................................................................................ 37117.7.5. EMAC Initialization and Configuration ..................................................... 37217.7.6. Performing Normal Receive and Transmit Operation ..................................37317.7.7. Stopping and Starting Transmission ....................................................... 37317.7.8. Programming Guidelines for Energy Efficient Ethernet ...............................37417.7.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output .......... 375

17.8. Ethernet MAC Address Map and Register Definitions ............................................. 377

18. USB 2.0 OTG Controller............................................................................................. 37818.1. Features of the USB OTG Controller.................................................................... 379

18.1.1. Supported PHYs................................................................................... 38118.2. Block Diagram and System Integration................................................................38118.3. Distributed Virtual Memory Support.................................................................... 38218.4. USB 2.0 ULPI PHY Signal Description...................................................................38218.5. Functional Description of the USB OTG Controller..................................................383

18.5.1. USB OTG Controller Components........................................................... 383

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18.5.2. Local Memory Buffer............................................................................. 38718.5.3. Clocks.................................................................................................38718.5.4. Resets................................................................................................ 38718.5.5. Interrupts............................................................................................389

18.6. USB OTG Controller Programming Model..............................................................39018.6.1. Enabling SPRAM ECCs........................................................................... 39018.6.2. Host Operation.....................................................................................39018.6.3. Device Operation..................................................................................392

18.7. USB 2.0 OTG Controller Address Map and Register Definitions................................ 393

19. SPI Controller........................................................................................................... 39419.1. Features of the SPI Controller ........................................................................... 39419.2. SPI Block Diagram and System Integration ......................................................... 395

19.2.1. SPI Block Diagram ...............................................................................39519.3. SPI Controller Signal Description ....................................................................... 395

19.3.1. Interface to HPS I/O ............................................................................ 39619.3.2. FPGA Routing ......................................................................................396

19.4. Functional Description of the SPI Controller .........................................................39719.4.1. Protocol Details and Standards Compliance ............................................. 39719.4.2. SPI Controller Overview ....................................................................... 39819.4.3. Transfer Modes ....................................................................................40119.4.4. SPI Master ..........................................................................................40319.4.5. SPI Slave ........................................................................................... 40619.4.6. Partner Connection Interfaces ............................................................... 40919.4.7. DMA Controller Interface....................................................................... 41419.4.8. Slave Interface ....................................................................................41419.4.9. Clocks and Resets ................................................................................414

19.5. SPI Programming Model ................................................................................... 41519.5.1. Master SPI and SSP Serial Transfers .......................................................41619.5.2. Master Microwire Serial Transfers ...........................................................41819.5.3. Slave SPI and SSP Serial Transfers .........................................................42019.5.4. Slave Microwire Serial Transfers .............................................................42119.5.5. Software Control for Slave Selection ...................................................... 42119.5.6. DMA Controller Operation...................................................................... 422

19.6. SPI Controller Address Map and Register Definitions .............................................425

20. I2C Controller............................................................................................................42720.1. Features of the I2C Controller ............................................................................42720.2. I2C Controller Block Diagram and System Integration ...........................................42820.3. I2C Controller Signal Description ........................................................................42920.4. Functional Description of the I2C Controller .........................................................430

20.4.1. Feature Usage .....................................................................................43020.4.2. Behavior ............................................................................................ 43120.4.3. Protocol Details ................................................................................... 43220.4.4. Multiple Master Arbitration ....................................................................43620.4.5. Clock Frequency Configuration .............................................................. 43820.4.6. SDA Hold Time ....................................................................................44020.4.7. DMA Controller Interface ...................................................................... 44020.4.8. Clocks ................................................................................................44120.4.9. Resets ............................................................................................... 441

20.5. I2C Controller Programming Model .....................................................................441

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20.5.1. Slave Mode Operation .......................................................................... 44120.5.2. Master Mode Operation ........................................................................ 44520.5.3. Disabling the I2C Controller ...................................................................44720.5.4. Abort Transfer......................................................................................44820.5.5. DMA Controller Operation ..................................................................... 448

20.6. I2C Controller Address Map and Register Definitions ............................................. 452

21. UART Controller........................................................................................................ 45321.1. UART Controller Features ..................................................................................45321.2. UART Controller Block Diagram and System Integration ........................................45421.3. UART Controller Signal Description .....................................................................455

21.3.1. HPS I/O Pins .......................................................................................45521.3.2. FPGA Routing ......................................................................................455

21.4. Functional Description of the UART Controller ......................................................45521.4.1. FIFO Buffer Support .............................................................................45621.4.2. UART(RS232) Serial Protocol .................................................................45621.4.3. Automatic Flow Control ........................................................................ 45721.4.4. Clocks ................................................................................................45921.4.5. Resets ............................................................................................... 45921.4.6. Interrupts ...........................................................................................459

21.5. DMA Controller Operation ................................................................................. 46221.5.1. Transmit FIFO Underflow ...................................................................... 46321.5.2. Transmit Watermark Level .................................................................... 46321.5.3. Transmit FIFO Overflow ........................................................................ 46521.5.4. Receive FIFO Overflow ......................................................................... 46521.5.5. Receive Watermark Level ......................................................................46521.5.6. Receive FIFO Underflow ........................................................................465

21.6. UART Controller Address Map and Register Definitions .......................................... 466

22. General-Purpose I/O Interface ................................................................................ 46722.1. Features of the GPIO Interface .......................................................................... 46722.2. GPIO Interface Block Diagram and System Integration ......................................... 46822.3. Functional Description of the GPIO Interface ....................................................... 468

22.3.1. Debounce Operation ............................................................................ 46822.3.2. Pin Directions ......................................................................................46922.3.3. Taking the GPIO Interface Out of Reset ...................................................469

22.4. GPIO Interface Programming Model ................................................................... 46922.5. General-Purpose I/O Interface Address Map and Register Definitions ...................... 469

23. Timers ......................................................................................................................47023.1. Features of the Timers ..................................................................................... 47023.2. Timers Block Diagram and System Integration .................................................... 47023.3. Functional Description of the Timers .................................................................. 471

23.3.1. Clocks ................................................................................................47223.3.2. Resets ............................................................................................... 47223.3.3. Interrupts ...........................................................................................472

23.4. Timers Programming Model .............................................................................. 47323.4.1. Initialization ........................................................................................47323.4.2. Enabling the Timers .............................................................................47323.4.3. Disabling the Timers ............................................................................ 47323.4.4. Loading the Timers Countdown Value ..................................................... 47323.4.5. Servicing Interrupts .............................................................................474

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23.5. Timers Address Map and Register Definitions .......................................................474

24. Watchdog Timers...................................................................................................... 47524.1. Features of the Watchdog Timers .......................................................................47524.2. Watchdog Timers Block Diagram and System Integration ......................................47624.3. Functional Description of the Watchdog Timers ....................................................476

24.3.1. Watchdog Timers Counter .....................................................................47624.3.2. Watchdog Timers Pause Mode ............................................................... 47724.3.3. Watchdog Timers Clocks .......................................................................47724.3.4. Watchdog Timers Resets .......................................................................478

24.4. Watchdog Timers Programming Model ................................................................47824.4.1. Setting the Timeout Period Values ..........................................................47824.4.2. Selecting the Output Response Mode ......................................................47824.4.3. Enabling and Initially Starting a Watchdog Timers ....................................47924.4.4. Reloading a Watchdog Counter ..............................................................47924.4.5. Pausing a Watchdog Timers .................................................................. 47924.4.6. Disabling and Stopping a Watchdog Timers ............................................. 47924.4.7. Watchdog Timers State Machine ............................................................ 479

24.5. Watchdog Timers Address Map and Register Definitions ........................................ 481

25. CoreSight Debug and Trace ...................................................................................... 48225.1. Features of CoreSight Debug and Trace............................................................... 48325.2. Arm CoreSight Documentation........................................................................... 48425.3. CoreSight Debug and Trace Block Diagram ..........................................................48525.4. Functional Description of CoreSight Debug and Trace ........................................... 486

25.4.1. Debug Access Port................................................................................48625.4.2. CoreSight SoC-400 Timestamp Generator ............................................... 48825.4.3. System Trace Macrocell......................................................................... 48825.4.4. Trace Funnel........................................................................................ 48925.4.5. CoreSight Trace Memory Controller......................................................... 48925.4.6. AMBA Trace Bus Replicator.....................................................................49125.4.7. Trace Port Interface Unit........................................................................49125.4.8. NoC Trace Ports....................................................................................49125.4.9. Embedded Cross Trigger System ............................................................49225.4.10. Embedded Trace Macrocell .................................................................. 49325.4.11. HPS Debug APB Interface ................................................................... 49325.4.12. FPGA Interface .................................................................................. 49325.4.13. Debug Clocks..................................................................................... 49525.4.14. Debug Resets.....................................................................................496

25.5. CoreSight Debug and Trace Programming Model................................................... 49725.5.1. CoreSight Component Address .............................................................. 49725.5.2. CTI Trigger Connections to Outside the Debug System...............................49825.5.3. Configuring Embedded Cross-Trigger Connections..................................... 500

25.6. CoreSight Debug and Trace Address Map and Register Definitions........................... 501

A. Booting and Configuration.......................................................................................... 502A.1. FPGA Configuration First Mode Overview............................................................... 504A.2. HPS Boot First Mode Overview............................................................................. 505

B. Accessing the Secure Device Manager Quad SPI Flash Controller through HPS...........508B.1. Features of the Quad SPI Flash Controller..............................................................508B.2. Taking Ownership of Quad SPI Controller...............................................................508

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B.3. Quad SPI Flash Controller Block Diagram and System Integration.............................509B.4. Quad SPI Flash Controller Signal Description..........................................................510B.5. Functional Description of the Quad SPI Flash Controller...........................................511

B.5.1. Overview.............................................................................................. 511B.5.2. Data Slave Interface...............................................................................511B.5.3. SPI Legacy Mode....................................................................................515B.5.4. Register Slave Interface..........................................................................516B.5.5. Local Memory Buffer...............................................................................517B.5.6. Arbitration between Direct/Indirect Access Controller and STIG.................... 517B.5.7. Configuring the Flash Device....................................................................517B.5.8. XIP Mode.............................................................................................. 517B.5.9. Write Protection..................................................................................... 518B.5.10. Data Slave Sequential Access Detection...................................................518B.5.11. Clocks.................................................................................................518B.5.12. Resets................................................................................................ 519B.5.13. Interrupts........................................................................................... 519

B.6. Quad SPI Flash Controller Programming Model.......................................................520B.6.1. Setting Up the Quad SPI Flash Controller...................................................520B.6.2. Indirect Read Operation.......................................................................... 521B.6.3. Indirect Write Operation..........................................................................521B.6.4. XIP Mode Operations.............................................................................. 522

B.7. Accessing the SDM Quad SPI Flash Controller Through HPS Address Map andRegister Definitions..........................................................................................524

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1. Intel® Agilex™ Hard Processor System TechnicalReference Manual Revision HistoryTable 1. Intel® Agilex™ Hard Processor System Technical Reference Manual Revision

History Summary

Chapter Date of Last Update

Introduction to the Hard Processor System September 30, 2019

Cortex-A53 MPCore* Processor September 30, 2019

Cache Coherency Unit September 30, 2019

System Memory Management Unit September 30, 2019

System Interconnect September 30, 2019

HPS-FPGA Bridges September 30, 2019

DMA Controller September 30, 2019

On-Chip RAM September 30, 2019

Error Checking and Correction Controller September 30, 2019

Clock Manager September 30, 2019

Reset Manager September 30, 2019

System Manager September 30, 2019

Hard Processor Subsystem I/O Pin Multiplexing September 30, 2019

NAND Flash Controller September 30, 2019

SD/MMC Controller September 30, 2019

Ethernet Media Access Controller September 30, 2019

USB 2.0 OTG Controller September 30, 2019

SPI Controller September 30, 2019

I2C Controller September 30, 2019

UART Controller September 30, 2019

General-Purpose I/O Interface September 30, 2019

Timer September 30, 2019

Watchdog Timer September 30, 2019

CoreSight* Debug and Trace September 30, 2019

Booting and Configuration July 1, 2019

Accessing the SDM Quad SPI Flash Controller through HPS September 30, 2019

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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Table 2. Introduction to the Hard Processor System Revision History

Document Version Changes

2019.09.30 Added links to access the complete HPS address map and register definitions.

2019.04.02 Initial release.

Introduction to the Hard Processor System on page 18

Table 3. Cortex-A53 MPCore Processor Revision History




Cortex-A53 MPCore Processor on page 32

Table 4. Cache Coherency Unit Revision History



2019.07.01 Added the following sections:• Reset and Initialization• Discovery Routine• Operational State• Maintenance Operations• Error Handling• OCRAM Firewall


Cache Coherency Unit on page 60

Table 5. System Memory Management Unit Revision History




System Memory Management Unit on page 71

Table 6. System Interconnect Revision History



2019.07.01 • Added the missing data width for MPFE blocks in Figure: Block Diagram.• Corrected the Figure: Generic Timestamp Connection.• Corrected the GIC address region in Figure: L3 Address Regions.• Corrected the address range in Figure: SDRAM Regions.• Added a new section: Peripheral Region Address Map.


System Interconnect on page 82

1. Intel® Agilex™ Hard Processor System Technical Reference Manual Revision History

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Table 7. HPS-FPGA Bridges Revision History



2019.07.01 Added information about FPGA Fabric Bypass Mux in section: FPGA-to-SoCBridge.


HPS Bridges on page 108

Table 8. DMA Controller Revision History




DMA Controller on page 115

Table 9. On-Chip RAM Revision History




On-Chip RAM on page 122

Table 10. Error Checking and Correction Controller Revision History




Error Checking and Correction Controller on page 126

Table 11. Clock Manager Revision History




Clock Manager on page 147

Table 12. Reset Manager Revision History



2019.07.01 Corrected steps in section: Warm Reset Sequence.


Reset Manager on page 159


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Table 13. System Manager Revision History




System Manager on page 168

Table 14. Hard Processor System I/O Pin Multiplexing Revision History




Hard Processor System I/O Pin Multiplexing on page 175

Table 15. NAND Flash Controller Revision History




NAND Flash Controller on page 182

Table 16. SD/MMC Controller Revision History




SD/MMC Controller on page 218

Table 17. Ethernet Media Access Controller Revision History




Ethernet Media Access Controller on page 305

Table 18. USB 2.0 OTG Controller Revision History




USB 2.0 OTG Controller on page 378


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Table 19. SPI Controller Revision History




SPI Controller on page 394

Table 20. I2C Controller Revision History




I2C Controller on page 427

Table 21. UART Controller Revision History




UART Controller on page 453

Table 22. General-Purpose I/O Revision History




General-Purpose I/O Interface on page 467

Table 23. Timers Revision History




Timers on page 470

Table 24. Watchdog Timers Revision History




Watchdog Timers on page 475


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Table 25. CoreSight Debug and Trace Revision History




CoreSight Debug and Trace on page 482

Table 26. Booting and Configuration Revision History


2019.07.01 Simplified information in the appendix. For more information, refer to the IntelAgilex Configuration User Guide and Intel Agilex Boot User Guide.


Booting and Configuration on page 502

Table 27. Accessing the SDM Quad SPI Flash Controller through HPS Revision History




Accessing the Secure Device Manager Quad SPI Flash Controller through HPS on page508


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2. Introduction to the Hard Processor SystemThe Intel Agilex system-on-a-chip (SoC) is composed of two distinct portions: a 64-bitquad core Arm* Cortex*-A53 MPCore hard processor system (HPS) and an FPGA. TheHPS architecture integrates a wide set of peripherals that reduce board size andincrease performance within a system.

The HPS communicates outside of the SoC through the following types of interfaces:

• Dedicated I/O interfaces

• FPGA fabric interfaces

• FPGA secure device manager (SDM) interfaces

Key modules in the HPS include:

• Quad core Arm Cortex-A53 MPCore processor

• Level 3 (L3) interconnect

• Cache Coherency Unit (CCU)

• System Memory Management Unit (SMMU)

• Multi-port front end (MPFE) subsystem, consisting of the hard memory controlleradaptor and interface to the CCU interconnect

• DMA Controller

• On-chip RAM

• Debug components

• PLLs

• Flash memory controllers

• Support peripherals

• Interface peripherals

The HPS incorporates third-party intellectual property (IP) from several vendors.

The FPGA portion of the device contains:

• FPGA fabric

• PLLs

• User I/O

• Hard memory controllers

• Secure Device Manager (SDM)

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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The HPS and FPGA portions of the device each have their own pins. The HPS hasdedicated I/O pins. You can also route most of the HPS peripherals into the FPGAfabric to use the FPGA I/O. You can configure pin placement assignments when youinstantiate the HPS component in Intel Platform Designer System Integration Tool.

You can boot the SoC from a power-on reset in one of two ways:

• FPGA configures first and then optionally boots the HPS (also called FPGAConfiguration First).

• HPS boots first and then configures the FPGA (called HPS Boot First).

For more information, refer to the "Boot and Configuration" appendix.

2.1. Features of the HPS

• Quad-core Arm Cortex-A53 MPCore processor

• Cache Coherency Unit (CCU)

• System Memory Management Unit (SMMU)

• System interconnect that includes:

— L3 main interconnect

• Provides high bandwidth routing from master to slave

• Provides two memory-mapped SoC-to-FPGA interfaces:

— SoC-to-FPGA bridge (32-, 64-, or 128-bit wide Arm AdvancedMicrocontroller Bus Architecture (AMBA*) Advanced eXtensibleInterface (AXI*)-4)

— Lightweight SoC-to-FPGA bridge: 32-bit wide AXI-4

— MPFE interconnect

• Routes transactions from FPGA translation buffer units (TBU) to SDRAM orSoC

• General-purpose direct memory access (DMA) controller

• 256 KB on-chip RAM

• Error checking and correction controllers for on-chip RAM and peripheral RAMs

• Clock manager

• Reset manager

• System manager

• Dedicated I/O pin multiplexer (MUX)

• NAND flash controller

• Secure digital/multimedia card (SD/MMC) controller

• Three Ethernet media access controllers (EMACs)

• Two USB 2.0 on-the-go (OTG) controllers

• Two serial peripheral interface (SPI) master controllers

• Two SPI slave controllers

2. Introduction to the Hard Processor System

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• Five inter-integrated circuit (I2C) controllers:

— Three can provide support for EMAC

— Two for general purpose

• Two UARTs

• Two general-purpose I/O (GPIO) interfaces with a total of 48 dedicated I/O

• Four system timers

• Four watchdog timers

• Arm CoreSight debug components:

— Debug access port (DAP)

— Trace port interface unit (TPIU)

— System trace macrocell (STM)

— Embedded trace macrocell (ETM)

— Embedded trace router (ETR)

— Embedded cross trigger (ECT)

2.2. HPS Block Diagram and System Integration

2.2.1. HPS Block Diagram

Figure 1. Intel Agilex HPS Block Diagram

SwitchCache

CoherencyUnit

GIC

TCU

On-Chip RAM(256 K)

FPGA Core Fabric

USB (2)

Osc1 Timer(2)

Watchdog(4)

SPI Slave(2)

SPI Master(2)

USB OTG(2)

NAND Coresight System(DAP, STM, ETR)

IO_TBU DMA_TBU EMAC_TBU

IO96 IO96

FPGA Bypass Mux

L3 Main Interconnect

Interconnect Interconnect

MPFE InterconnectArbitration

Hard Memory Controller Adaptor

16-/32-/64-bit

256-bitACE-Lite

512-bitAXI4

32-bit AXI464-bit

AXI4

64-bit

64-bitDVM

64-bit ACE-Lite

64-bit AXI4

IRQ from FPGA

32-bitACE-Lite

128-bitACE

48 HPS I/Os

L4 Bus L4 Bus L4 Bus L4 Bus L4 Bus

SD/MMC

EMAC0

EMAC1

EMAC2

DMA

Initiating Peripherals

DDR

FPGA Core Fabric

Pin Mux

Targeted Peripherals

MPU

CPU0CPU1

CPU2CPU3

L2 Cache

SCU

512-bitACE-Lite

512-bitACE-Lite

128-/256-/ 512-bit

ACE-Lite

32-bit AHB

32-bit AHB

32-bit AXI4

32-bit AXI4

32-bit AXI4

32-bit AXI4

32-bit AXI4

64-bit AXI4

64-bit AXI4 64-bit AXI4

64-bit AXI4 64-bit AXI4 64-bit AXI4

32-bit AXI4

32-/64-/ 128-bit

AXI

32-bit AXI

32-bit AXI4

IRQ fromPeripherals

LW SoC-to-FPGASoC-to-FPGA

FPGA-to-SoC

FPGA Bypass Mux

MPFE

FPGA_TBU

SD/MMC EMACO EMAC1 EMAC2NAND ETR DMA

SDM

System Modules

SystemManager

ClockManager

ResetManager

Hard Processor System

SP Timer(2)

UART(2)

GPIO(2)

I2C(5)

SDM_TBU


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2.2.2. Cortex-A53 MPCore Processor

The Intel Agilex SoC integrates a full-featured Arm Cortex-A53 MPCore Processor.

The Cortex-A53 MPCore supports high-performance applications and provides thecapability for secure processing and virtualization. Each CPU in the processor has thefollowing features:

• Support for 32- and 64-bit instruction sets

• In-order pipeline with symmetric dual-issue of most instructions

• Arm NEON* single instruction, multiple data (SIMD) co-processor with a floating-point unit (FPU)

— Single- and double-precision IEEE-754 floating point math support

— Integer and polynomial math support

• Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes

• Armv8 Cryptography Extension

• Level 1 (L1) cache

— 32 KB two-way set associative instruction cache

— Single Error Detect (SED) and parity checking support for L1 instruction cache

— 32 KB four-way set associative data cache

— Error checking and correction (ECC), Single Error Correct, Double Error Detect(SECDED) protection for L1 data cache

• Memory Management Unit (MMU) that communicates with the system MMU(SMMU)

• Generic timer

• Governor module that controls clock and reset

• Debug modules

— Performance Monitor Unit

— Embedded Trace Macrocell (ETMv4)

— CoreSight cross trigger interface

The four CPUs share a 1 MB L2 cache with ECC, SECDED protection. A snoop controlunit (SCU) maintains coherency between the CPUs and communicates with the systemcache coherency unit (CCU).

At a system level, the Cortex-A53 MPCore interfaces to a generic interrupt controller(GIC), CCU, and system memory management unit (SMMU).

2.2.3. Cache Coherency Unit

The cache coherency unit allows I/O masters to maintain one-way coherency with theCortex-A53 MPCore. It acts as an interconnect among the processor, FPGA-to-SoCbridge, system MMU, multiport front end (MPFE) subsystem and peripheral mastersinterfacing the system interconnect and supports weighted priority of memoryaccesses.

The CCU features include:


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• Coherency directory to track the state of the L2 and L1 caches in the Arm Cortex-A53 MPCore

• Snoop filter support for tracking coherent lines and sending coherency transactionrequests, including cache maintenance operations

• Support for distributed virtual memory (DVM) using the Arm AXI CoherencyExtensions (ACE) protocol. Distributed virtual memory broadcast messages aresent to the Cortex-A53 MPCore and translation control unit (TCU) in the systemmemory management unit (SMMU)

• Quality-of-service (QoS) support for transaction prioritization using a weightbandwidth allocation

• Interconnect debug capability through master and slave bridge status registers

• Interrupt support for CCU transaction and counter events

2.2.4. System Memory Management Unit

The SMMU provides system-wide address translation for system bus masters. A two-stage translation supports memory virtualization. The module includes a single TCUthat controls distributed translation buffer units (TBUs).

The system MMU features include:

• A central TCU that supports five distributed TBUs for the following masters:

— FPGA

— DMA

— EMAC0-2, collectively

— USB0-1, NAND, SD/MMC, ETR, collectively

— Secure Device Manager (SDM)

• Caches for storing page table entries and intermediate table walk data:

— 512-entry macro translation lookaside buffer (TLB) page table entry cache inthe TCU

— 128-entry micro TLB for table walk data in the FPGA TBU and 32-entry microTLB for all other distributed TBUs

— Single-bit error detection and invalidation on error detection for caches

• Communication with the MMU of the Arm Cortex-A53 MPCore

• System-wide address translation

• Address virtualization

• Support for 32 contexts

• Two stages of translation or combined (stage 1 and stage 2) translation

• Support for up to 49-bit virtual addresses and up to 48-bit physical andintermediate physical addresses

• Programmable QoS to support page table walk arbitration

• Fault handling, logging and interrupts for translation errors

• Debug support


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2.2.5. HPS Interfaces

The Intel Agilex device family provides multiple communication channels between theFPGA, HPS, and SDRAM.

2.2.5.1. SoC-FPGA Memory-Mapped Interfaces

The SoC-FPGA memory-mapped interfaces provide the major communication channelsamong the HPS, the FPGA fabric, and SDRAM. The SoC-FPGA memory-mappedinterfaces include:

• FPGA-to-SoC bridge—a high–performance bus with a configurable data width of128, 256, or 512 bits, allowing the FPGA fabric to master transactions to theslaves in the HPS or access to SDRAM through the MPFE interconnect. Thisinterface allows the FPGA fabric to have full visibility into the HPS address space.This interface supports single-direction I/O coherency with the HPS MPU.

• SoC-to-FPGA bridge—a high–performance interface with a configurable data widthof 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in theFPGA fabric.

• Lightweight SoC-to-FPGA bridge—an interface with a 32–bit fixed data width,allowing the HPS to master transactions to slaves in the FPGA fabric. This bridge isprimarily used for control and status register accesses.

2.2.5.2. Other HPS Interfaces

• TPIU trace—sends trace data created in the SoC-FPGA fabric.

• FPGA System Trace Macrocell (STM)—an interface that allows the FPGA fabric tosend hardware events to be stored in the HPS trace data.

• FPGA cross–trigger—an interface that allows the CoreSight trigger system to sendtriggers to IP cores in the FPGA, and vice versa.

• DMA peripheral interface—multiple peripheral–request channels.

• Interrupts—allow soft IP cores to supply interrupts directly to the MPU interruptcontroller.

• MPU standby and events—signals that notify the FPGA fabric that the MPU is instandby mode and signals that wake-up Cortex–A53 processors from a wait forevent (WFE) state.

• HPS debug interface – an interface that allows the HPS debug control domain(debug APB) to extend into FPGA.

2.2.6. System Interconnect

The system interconnect supports the following features:


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• Configurable Arm TrustZone*-compliant firewall and security support.

— For each peripheral, implements secure or non-secure access.

— Allows configuration of individual transactions as secure or non-secure at theinitiating master.

• Multi-tiered bus structure to separate high bandwidth masters from lowerbandwidth peripherals and control and status ports.

• Quality of service (QoS) with three programmable levels of service on a permasterbasis.

• On-chip debugging and tracing capabilities. The system interconnect is based onthe Arteris® FlexNoC™ network-on-chip (NoC) interconnect technology.

2.2.6.1. MPFE Subsystem

The multiport front end (MPFE) subsystem connects the HPS to the hard memorycontroller adaptor (HMCA) that is located in the FPGA portion of the device. The MPFEsubsystem includes an MPFE Interconnect, which is secured by firewalls. It supportsAMBA AXI QoS for the FPGA fabric interfaces.

The MPFE Subsystem implements the following high-level features:

• Support for double data rate 4 (DDR4) devices

• Software-configurable priority scheduling per port

• 8-bit Single Error Correction, Double Error Detection (SECDED) ECC with write-back, and error counters

• Fully-programmable timing parameter support for all JEDEC®-specified timingparameters

• All ports support memory protection and mutual-exclusive accesses

2.2.7. On-Chip RAM

The on-chip RAM offers the following features:

• 256 KB size

• 64-bit slave interface

• ECC support provides detection of single–bit and double–bit errors and correctionfor single-bit errors

• Memory scrambling on tamper events

2.2.8. Flash Memory Controllers

The Intel Agilex device family provides two flash memory controllers:

• NAND Flash Controller

• SD/MMC Controller


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2.2.8.1. NAND Flash Controller

The NAND flash controller is based on the Cadence* Design IP* NAND Flash MemoryController and offers the following functionality and features:

• Supports up to two chip selects

• Integrated descriptor-based direct memory access (DMA) controller

• Supports Open NAND Flash Interface (ONFI) 1.0

• Programmable page sizes of 512 bytes, 2 KB, 4 KB, or 8 KB

• Supports 32, 64, or 128 pages per block

• Programmable hardware ECC

• Supports 8- and 16-bit data width

2.2.8.2. SD/MMC Controller

The Secure Digital (SD), Multimedia Card (MMC), (SD/MMC) and CE-ATA hostcontroller is based on the Synopsys* DesignWare* Mobile Storage Host controller andoffers the following features:

• Supports eMMC

• Integrated descriptor-based DMA

• Supports CE-ATA digital protocol commands

• Supports only single card

— Single data rate (SDR) mode only

— Programmable card width: 1-, 4-, and 8-bit

— Programmable card types: SD, SDIO, or MMC

• Up to 64 KB programmable block size

• Supports up to 50 MHz flash operating frequency

Note: For an inclusive list of the programmable card types and versions supported, refer tothe SD/MMC Controller chapter.

2.2.9. System Modules

2.2.9.1. Clock Manager

The clock manager is responsible for providing software-programmable clock controlto configure all clocks generated in the HPS. The clock manager offers the followingfeatures:

• Manages clocks for HPS

• Supports clock gating at the signal level

• Supports dynamic clock tuning


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2.2.9.2. Reset Manager

The reset domains and sequences support several security features. The SDM bringsthe reset manager out of reset; and after that, the reset manager brings th

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