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Serial Lite IV Intel® Agilex™ FPGA IPDesign Example User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.1

IP Version: 1.2.0

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Contents

1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide.................. 3

2. Quick Start Guide............................................................................................................52.1. Design Example Block Diagram............................................................................... 52.2. Hardware and Software Requirements...................................................................... 62.3. Generating the Design............................................................................................7

2.3.1. Design Example Parameters........................................................................72.3.2. Directory Structure.................................................................................... 9

2.4. Compiling and Simulating the Design......................................................................112.5. Compiling and Testing the Design...........................................................................12

3. Detailed Description for Serial Lite IV Design Example................................................. 143.1. Features............................................................................................................. 143.2. Design Example Components................................................................................ 15

3.2.1. Traffic Generator......................................................................................153.2.2. Traffic Checker.........................................................................................153.2.3. DCFIFO.................................................................................................. 16

3.3. Simulation.......................................................................................................... 173.3.1. Simulation Results for Basic Mode.............................................................. 173.3.2. Simulation Result for Full Mode..................................................................19

3.4. Hardware Testing.................................................................................................203.5. Error Handling.....................................................................................................233.6. Link Debugging Sequence..................................................................................... 233.7. Serial Lite IV IP Toolkit......................................................................................... 26

3.7.1. Setting Up and Running the Toolkit.............................................................263.7.2. Toolkit GUI Settings................................................................................. 28

4. Serial Lite IV Intel Agilex FPGA IP Design Example User Guide Archives...................... 30

5. Document Revision History for the Serial Lite IV Intel Agilex FPGA IP DesignExample User Guide.................................................................................................31

Contents

Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback

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1. About the Serial Lite IV Intel® Agilex™ FPGA IP DesignExample User Guide

This user guide provides features, usage guidelines, and functional description of theSerial Lite IV Intel® FPGA IP design examples using E-tile transceivers in Intel Agilex®

devices.

Intended Audience

This user guide is intended for:

• Design architects to make IP selection during system level design planning phase.

• Hardware designers when integrating the IP into their system level design.

• Validation engineers during system level simulation and hardware validationphase.

Related Documents

The following table lists other reference documents that are related to the Serial LiteIV Intel FPGA IP.

Table 1. Related Documents

Reference Description

Serial Lite IV Intel FPGA IP User Guide This user guide provides IP features, architecturedescription, steps to generate, and guidelines to design theSerial Lite IV Intel FPGA IP using the E-tile transceivers.

Serial Lite IV Intel Stratix® 10 Design Example User Guide This document provides features, usage guidelines, andfunctional descriptions of the Serial Lite IV Intel FPGA IPdesign examples in Intel Stratix 10 devices.

E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs

This document describes the features, functionality, andguidelines of the E-Tile Hard IP for Ethernet and E-Tile CPRIPHY Intel FPGA IP cores in Intel Stratix 10 and Intel Agilexdevices.

Intel Agilex Device Data Sheet This document describes the electrical characteristics,switching characteristics, configuration specifications, andtiming for Intel Agilex devices.

E-Tile Transceiver PHY User Guide This document describes the features, functionality, andguidelines for the E-Tile Transceiver PHY in Intel Stratix 10and Intel Agilex devices.

Intel Agilex F-Series Transceiver SoC Development Kit UserGuide

This document describes the features, functionality, andguidelines for the Intel Agilex F-Series Transceiver SoCDevelopment Kit.

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Acronyms and Glossary

Table 2. Acronym List

Acronym Expansion

CW Control Words

RS-FEC Reed-Solomon Forward Error Correction

PMA Physical Medium Attachment

TX Transmitter

RX Receiver

PAM4 Pulse-Amplitude Modulation 4-Level

NRZ Non-return-to-zero

PCS Physical Coding Sublayer

MII Media Independent Interface

XGMII 10 Gigabit Media Independent Interface

1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide

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2. Quick Start GuideThe Serial Lite IV Intel FPGA IP provides the ability to generate design examples forselected configurations.

The Serial Lite IV Intel FPGA IP design example for Intel Agilex devices features asimulation testbench and a hardware design that supports compilation and hardwaretesting. The design example demonstrates loopback mode designs in basic or fullmode for duplex configurations.

Figure 1. Development Stages for the Design Example

DesignExample

Generation

Compilation(Simulator)

FunctionalSimulation

Compilation(Quartus Prime)

HardwareTesting

2.1. Design Example Block Diagram

Figure 2. High-level Block Diagram for Intel Agilex Design Examples

DemoManagement

DemoControl

JTAGInterface

SystemConsole

TrafficChecker

DCFIFO

TrafficGenerator

DCFIFO

IOPLLSerial Lite IV

Duplex

Table 3. Design Example Components

Component Description

Serial Lite IV IP The Serial Lite IV IP in this design example supports streaming or packettransfer mode with the following features:• 56 Gbps per lane with a maximum of eight PAM4 lanes with RS-FEC• 28 Gbps per lane with a maximum of 16 NRZ lanes with or without

RS-FEC

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Component Description

The Serial Lite IV IP accepts data from the traffic generator and formatsthe data for transmission.The Serial Lite IV IP also receives data from the link, strips the headers,and sends it to the traffic checker for analysis.You generate the IP using the parameter editor in the Intel Quartus®

Prime Pro Edition software.

System Console The System Console is an Intel Quartus Prime tool that provides a user-friendly interface for you to do first-level debugging and monitor thestatus of the IP, and the traffic generator, and checker.

Demo control The demo control module consists of Avalon-MM pipeline bridgesconnected to the transceiver reconfiguration and the demo managementinterfaces. The design also instantiates the JTAG master, parallel input/output (PIO), and ISSP (In-system Source and Probe) modules forSystem Console debugging purposes.

Demo management The demo management module implements control and status registers(CSRs) to control, monitor the design operation, and log errors thatoccur during the operation.

User clock—IOPLL For Intel Agilex E-tile devices, the design example uses an IOPLL togenerate a user clock to transmit data to the Serial Lite IV IP.The design uses the iopll_ref_clk clock signal as an IOPLL referenceclock to connect to the clock generator.Important: The iopll_ref_clk should have the same frequency as

the pll_refclk and come from the same clock module.

Traffic generator The traffic generator generates traffic in a deterministic format to verifythat the link transmits data correctly.

Traffic checker The traffic checker performs inspections to verify that the received datais in the expected format.

Dual-clock FIFO (DCFIFO) The DCFIFO blocks handle data streaming and control signals for clockcrossing between different clock domains.

Related Information

• Traffic Generator on page 15

• Traffic Checker on page 15

• DCFIFO on page 16

2.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design examples in a Linuxsystem:

• Intel Quartus Prime Pro Edition software version 20.1

• ModelSim*(1), Xcelium*, NCSim (Verilog only), or VCS*/VCS MX simulator

• Intel Agilex F-Series Transceiver-SoC Development Kit (AGFB014R24A2E3VR0) forhardware testing

(1) ModelSim - Intel FPGA Edition is not supported for this IP.

2. Quick Start Guide

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2.3. Generating the Design

You can use the IP parameter editor in the Intel Quartus Prime Pro Edition software togenerate the design example.

Figure 3. Generating the Design Flow

Start ParameterEditor

Specify IP Variationand Select Device

SelectDesign Parameters

InitiateDesign Generation

Specify Example Design

To generate the design example from the IP parameter editor:

1. In the Tools ➤ IP Catalog, locate and select Serial Lite IV Intel FPGA IP. TheIP parameter editor appears.

2. Specify the parameters for your design.

3. Click the Generate Example Design button.

The software generates all design files in the sub-directories. You need these files torun simulation, compilation, and hardware testing.

Related Information

Directory Structure on page 9

2.3.1. Design Example Parameters

The Serial Lite IV IP parameter editor includes an Example Design tab for you tospecify parameters before generating the design example.


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Figure 4. Example Design Tab

Table 4. Parameters in the Example Design Tab

Parameter Description

Generate Files for The IP generates the necessary design example files for simulation andcompilation.Simulation—select this option to generate the necessary designsimulation files.Synthesis—select this option to generate the necessary design synthesisfiles. Use these files to compile the design in the Intel Quartus Prime ProEdition software for hardware testing.

Generate Files for Synthesis When selected, the IP generates the synthesis files. Use these files tocompile the design in the Intel Quartus Prime Pro Edition software forhardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.

Select Board Supported hardware for design implementation. When you select anIntel FPGA development board, the Target Device is the one thatmatches the device on the Development Kit.If this menu is grayed out, there is no supported board for the optionsthat you select.Agilex F-Series Transceiver-SoC Development Kit: This optionallows you to test the design example on the selected Intel FPGA IPdevelopment kit. This selection automatically selects the Target Deviceto match the device on the Intel FPGA IP development kit. If your boardrevision has a different speed grade, you can change the target device.Custom Development Kit: This option allows you to test the designexample on a third party development kit with Intel FPGA IP device, acustom designed board with Intel FPGA IP device, or a standard IntelFPGA IP development kit not available for selection. You can also select acustom device for the custom development kit.

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Parameter Description

No Development Kit: This option excludes the hardware aspects forthe design example.

Change Target Device Select a different device grade for Intel FPGA IP development kit. Fordevice-specific details, refer to the device datasheet on the Intel FPGAwebsite.

2.3.2. Directory Structure

The Intel Quartus Prime Pro Edition software generates the design example files in thefollowing folders:

• <user_defined_design_example_directory>/ed_sim

• <user_defined_design_example_directory>/ed_synth

• <user_defined_design_example_directory>/ed_hwtest

The following diagrams show the directories that contain the generated files for thedesign example.


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Figure 5. Directory Structure for Intel Agilex Serial Lite IV Design Example

<Design Example>

ed_sim ed_synth ed_hwtest

cadence

mentor

xcelium

synopsys

tb_components

common

system_console

sliv_ip_toolkit_agilex

src

seriallite_iv_streaming_demo.qpf

seriallite_iv_streaming_demo.qsf

seriallite_iv_streaming_demo.sdc

Readme.txt

gen_qsys_seriallite4_dup.tcl

gen_sim_verilog.tcl/gen_sim_vhdl.tcl

demo_control

ip

reset_release_ip

seriallite4_dcfifo

seriallite4_dup

seriallite4_io_pll

demo_control.qsys

gen_qsys_seriallite4_dcfifo.tcl

gen_qsys_seriallite4_dup.tcl

gen_qsys_seriallite4_io_pll.tcl

gen_qsys_seriallite4_reset_release.tcl

gen_synth_verilog.tcl/gen_synth_vhld.tcl

jtag_timing_template.sdc

reset_release_ip.qsys

seriallite4_dcfifo.qsys

seriallite4_dup.ip

seriallite4_io_pll.ip

seriallite4_dup.ip

seriallite4_dup

log_generate_eds.txt

log_generate_eds.txt

aldec


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Table 5. Design Example Generated Directory and File Descriptions

Directory/File Description

ed_sim/tb_components The directory that contains the testbench files.

ed_sim/common The directory that contains the .tcl scripts for all thesimulators.

ed_sim/cadence

ed_sim/mentor

ed_sim/xcelium

ed_sim/synopsys/vcs

The directories that contain the simulation scripts. Thesedirectories also serve as a working area for the simulators.

ed_sim/seriallite4_dup The directory that contains the design example simulationsource files.

ed_sim/seriallite4_dup.ip IP-XACT representation of the design.

ed_synth/seriallite_iv_streaming_demo.qpf Intel Quartus Prime Pro Edition project file.

ed_synth/seriallite_iv_streaming_demo.qsf Intel Quartus Prime Pro Edition settings file.

ed_synth/seriallite_iv_streaming_demo.sdc Synopsys Design Constraints (SDC) file.

ed_synth/src The directory that contains the design examplesynthesizable components.

ed_synth/src/seriallite_iv_streaming_demo.v Design example top-level HDL.

ed_synth/demo_control The directory for each synthesizable component includingPlatform Designer-generated IPs, such as DemoManagement and Demo Control modules.

ed_hwtest The directory that contains the design example hardwaresetup files.

ed_hwtest/Readme.txt Instruction file to download the generated design exampleon the development kit.

ed_hwtest/system_console The directory that contains system console scripts thatprovide useful commands to read statistics and to test thehardware design.

ed_hwtest/sliv_ip_toolkit_agilex The folder that contains the scripts to invoke the Serial LiteIV IP toolkit for Intel Agilex devices. This toolkit is a user-friendly GUI that provides step-by-step link initialization anddebugging.

Related Information

Generating the Design on page 7

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.

Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1. Change the working directory to <example_design_directory>/ed_sim/<simulator>


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Note: In Serial Lite IV Intel FPGA IP version 1.1.0, the ModelSim simulator doesnot capture the top-level IP signals in the waveform. To capture the top-level IP signals, add the ld_debug command to the ed_sim/mentor/run_tb.tcl file.

2. Run the simulation script for the simulator of your choice.

Table 6. Testbench Simulation Scripts

Simulator File Directory Command

ModelSimNote: This IP only supports

ModelSim - Intel FPGAStarter Edition simulator.

<variation name>seriallite4_0_example_design/ed_sim/mentor

do run_tb.tcl

VCS <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcs

sh run_tb.sh

VCS MX <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcsmx

sh run_tb.sh

NCSim <variation name>seriallite4_0_example_design/ed_sim/cadence

sh run_tb.sh

Xcelium <variation name>seriallite4_0_example_design/ed_sim/xcelium

sh run_tb.sh

3. When the simulation is complete, you can now analyze the results and verify thedesign. A successful simulation ends with the following message, "Test Passed."

# ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 534579600# # Total words tranferred = 10000# # Number of bursts = 0# # Random number generator seed = 1756255697# # Link Latency = 434 ns# # *************************************** Test Passed **************************************

2.5. Compiling and Testing the Design

The Serial Lite IV IP parameter editor allows you to compile and run the designexample on a target development kit.

Compile Designin Quartus Prime

Software

Set up Hardware Program Device Test Designin Hardware


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Follow these steps to compile and test the design in hardware:

1. Launch the Intel Quartus Prime Pro Edition software and change the directory toexample_design_dir/ed_synth/ and open theseriallite_iv_streaming_demo.qpf file.

2. Click Processing> Start Compilation to compile the design.

The Intel Quartus Prime Pro Edition software automatically loads the timingconstraints for the design example and the design components during compilation.

3. Connect the development board to the host computer.

4. Configure the FPGA on the development board using the generatedseriallite_iv_streaming_demo.sof file (Tools> Programmer).

The design example targets the Intel Agilex F-Series Transceiver SoC DevelopmentKit.

The design includes a Synopsys Design Constraints File (.sdc) and an IntelQuartus Prime Pro Edition Settings File (.qsf) with verified constraints inloopback mode. If you use the design example with another device ordevelopment board, you may need to update the device settings and constraintsin the .qsf file.

Note: Before downloading the design onto the FPGA, you need to program theclock oscillator on the board to match the transceiver PLL and IOPLLreference clock frequencies configured in the design example. Refer to theIntel Agilex F-Series Transceiver SoC Development Kit User Guide: Controlon-board clock through Clock Controller GUI for steps to program the clockoscillator on board.

5. After loading the .sof file onto the development board, you can run the hardwaredesign example using either system console or the Serial Lite IV IP toolkit. Formore information about the Serial Lite IV IP toolkit, refer to the Serial Lite IV IPToolkit topic.

Figure 6. Example of Hardware Design Example Test Result in System Console

All transactions are successful when traffic checker detects no errors.

The number of words transferred in a test.

Related Information

Intel Agilex F-Series Transceiver SoC Development Kit User Guide: Control on-boardclock through Clock Controller GUI


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3. Detailed Description for Serial Lite IV Design ExampleThis design example demonstrates the functionality of data streaming using basic andfull mode.

You can specify the parameter settings of your choice and generate the designexample.

The design example is available only in duplex mode.

3.1. Features

You can use the design example to test the following features of the Serial Lite IV IP:

• Basic and full transmission modes:

— Basic mode—This is a pure streaming mode where data is sent without thestart-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IPtakes the first valid data as the start of a burst.

— Full mode—This is a packet transfer mode. This mode sends a burst and async cycle at the start and end of a packet as delimiters.

• Slave test mode for master and slave testing.

• Transceiver data rate up to:

— 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link withRSFEC feature(2)

— 28 Gbps per lane with a maximum of 16 NRZ lanes with optional RSFECfeature(2).

• Data error reporting including PCS errors, loss of alignment, CRC errors, and datainvalid errors on the RX datapath.

• Traffic checker for data verification and lane deskew verification.

• System console commands for hardware testing.

• Serial Lite IV IP debugging toolkit.

• Debugging sequence.

(2) The maximum data rate that the IP can achieve depends on the device speed grade. Refer to Intel Agilex Device Data Sheet for more information about maximum data rate for each devicespeed grade.

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3.2. Design Example Components

3.2.1. Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data istransmitted correctly across the link. The traffic consists of sets of sample words, onefor each lane on the link, that the traffic checker transmits to the source userinterface.

If you configure the Serial Lite IV IP in full mode, the traffic generator also asserts thetx_is_usr_cmd signal at random to specify the packet is from user data for testingpurposes. The Serial Lite IV IP asserts the num_valid_bytes_eob control signal tosignify the number of valid bytes of the burst packet.

Figure 7. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.

Word ID Burst Count Word Count

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

Table 7. Traffic Generator Sample Word Fields

Field Bits Description

Word ID 63–59 Contains a static value to distinguish which 64-bit word on the user interface that thissample was presented on. The Word ID value ranges from 0 to (lanes – 1).

Burst Count 58–32 Tracks the number of bursts used to transfer the sample data. This field value starts withone after reset and is incremented each time the start_of_burst signal asserts on thesource user interface.

Word Count 31–0 Tracks the number of valid sample words that the traffic generator transfers, across allbursts, to the source user interface.

3.2.2. Traffic Checker

The traffic checker performs the following inspections to verify that the received dataare in the expected format:

• Checks each sample word to verify that the traffic checker receives the expectedword ID.

• Checks each sample word to verify that the word count value is higher than theword count value from the last valid sample word.

• Verifies that lane de-skew is working correctly by validating that the word countand burst count values from the sample word are the same as the values receivedfrom the adjacent lane.

• If the start_of_burst signal asserts on the user interface, verifies that theburst count value in the current sample word is higher than the burst count valuefrom the last valid sample word. Otherwise, it verifies that the burst count valuehas not changed.

3. Detailed Description for Serial Lite IV Design Example

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3.2.3. DCFIFO

The design uses two DCFIFO blocks at both TX and RX paths. The DCFIFO blockshandle data streaming and control signals for clock crossing between different clockdomains.

Table 8. TX and RX DCFIFO Configuration

Parameter Value

lpm_width (Number of lanes x 64)+32

lpm_numwords 64

The format of the data that transmits through the FIFO is similar to the formatgenerated by the traffic generator.

Figure 8. Data Format

Word ID Burst Count Word Count

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

Table 9. Control SignalsThe table lists how the IP concatenates the TX and RX control signals with the data bus signals and passesthrough the data.

Control DCFIFO DataOut Bit

Signal Description

[20] tx_valid

rx_valid

Indicates TX or RX data is valid for Full and Basicmodes.

[19] tx_start_of_packet

rx_start_of_packet

Indicates the start of a TX or RX data packet.For Full mode only.

[18] tx_end_of_packet

rx_end_of_packet

Indicates the end of a TX or RX data packet.For Full mode only.

[17:10] tx_channel

rx_channel

The channel number for data being transmitted orreceived on the current cycle number.For Full mode only.

[9:5] tx_empty

rx_empty

Indicates the number of non-valid words in the finalburst of the TX or RX data.For Full mode only.

[4:1] tg_tx_num_valid_bytes_eob

tc_rx_num_valid_bytes_eob

Indicates the number of valid bytes in the last wordof the final burst.For Full mode only.

[0] tg_tx_is_usr_cmd

tc_rx_is_usr_cmd

Initiates a user-defined information cycle.• Full mode: Must coincide with

tx_startofpacket or rx_startofpacket• Basic mode: Not supported.

Related Information

• FIFO Intel FPGA IP User Guide

• Serial Lite IV Intel FPGA IP User Guide: Serial Lite IV Intel FPGA IP InterfaceSignals


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3.3. Simulation

Figure 9. Example Testbench (Duplex) for Intel Agilex E-tile Devices

Testbench

Serial Lite IV Intel FPGA IP

TrafficGenerator

TrafficChecker

DCFIFO TX MAC

RX MAC SkewInsertion

Device Under Test (Duplex Mode)Test Environment

DCFIFO

CustomPCS

The simulation test cases demonstrate streaming of 10,000 sample words from thetraffic generator to the Serial Lite IV TX core, and externally loopback to the RX core.The words are either separated into different bursts or continuously transferred in asingle burst. The transfer modes are randomized by the testbench.

The simulation test case performs the following steps:

1. Initializes and configures Serial Lite IV IP, traffic generator, and traffic checker.

2. Traffic generator generates data and starts data transmission.

3. Logs and displays link up status and burst information.

4. Traffic checker verifies received data and stops transmission.

5. Testbench logs and displays test results and test information.

3.3.1. Simulation Results for Basic Mode

The generated example testbench is dynamic and has the same configuration as theIP.

In basic or pure streaming mode, the traffic generator generates 10,000 words andtransmits to the IP once the TX and RX links are established. The words are thenlooped back to the RX MAC. The RX MAC then sends the words to the traffic checkerfor data verification. In the simulation results, you can find the following information:

• TX and RX link status

• Configuration settings of the IP

• Number of words transferred per burst

• Test results with the total number of words transferred and link latency value

The following is a sample of the basic mode simulation results:

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 354081776# # Phy EHIP ready asserted at time 475222181


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# # TX link_up asserted at time 475228320# TX user_clock frequency = 3.731343e+02 MHz# RX user_clock frequency = 3.731343e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 475239040# # LANES = 4# # Streaming Mode = BASIC# # SRL4 Align Period = 128# # RSFEC Enable = 0# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************# # Waiting for RX Link Up# # Phy block lock asserted at time 495699771# # Phy RX PCS Ready asserted at time 495731094# # RX link_up asserted at time 495786600# # ******************************* Data Forwarding Test Started *****************************# # Test Mode: Burst# User Stall Insertion: Disabled# # # Traffic Generator: 98 sample burst started at time 495797320# # Traffic Generator: 17 sample burst started at time 496110880...# Traffic Generator: 96 sample burst started at time 533156520# # Traffic Generator: 85 sample burst started at time 533515640# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 534579600# # Total words tranferred = 10000# # Number of bursts = 0# # Random number generator seed = 1756255697# # Link Latency = 434 ns# # *************************************** Test Passed **************************************


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3.3.2. Simulation Result for Full Mode

In full mode or packet transfer mode, the traffic generator generates 10,000 words ina random number of bursts and transmits to the IP once the TX and RX links areestablished. The words are looped back to the RX MAC. The RX MAC then sends theburst to the traffic checker for data verification. In the simulation results, you can findthe following information:

• TX and RX link status

• Configuration settings of the IP

• Number of sample words sent per burst

• Test results with the total number of words transferred, number of bursts, and linklatency value

The following is a sample of the full mode simulation result:

# Waiting for TX Link Up# # Phy TX Lanes Stable asserted at time 354081776# # Phy EHIP ready asserted at time 475222181# # TX link_up asserted at time 475228320# TX user_clock frequency = 3.731343e+02 MHz# RX user_clock frequency = 3.731343e+02 MHz# # *************************************** Test Started *************************************# # Tests started at time 475239040# # LANES = 4# # Streaming Mode = FULL# # SRL4 Align Period = 128# # RSFEC Enable = 0# # PER LANE CRC ENABLE Enable = 0# # ******************************* Data Forwarding Test Initialize *****************************# # Waiting for RX Link Up# # Phy block lock asserted at time 495699771# # Phy RX PCS Ready asserted at time 495731094# # RX link_up asserted at time 495786600# # ******************************* Data Forwarding Test Started *****************************# # Test Mode: Burst# User Stall Insertion: Disabled# # # Traffic Generator: 98 sample burst started at time 495797320# # Traffic Generator: 17 sample burst started at time 496110880...# Traffic Checker: Burst start descriptor read at time 534212440


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# Sync value 242# Sample number 9907# # Traffic Checker: Burst end descriptor read at time 534534040# Inter-burst interval 7# Empty value 0# Sample number 10000# # ****************************** Data Forwarding Test Completed ****************************# # ************************************** Test Completed ************************************# # End time = 534810080# # Total words tranferred = 10000# # Number of bursts = 196# # Random number generator seed = 1756255697# # Link Latency = 0 ns# # *************************************** Test Passed **************************************

3.4. Hardware Testing

After you download the design and the accompanying software onto the FPGA, youcan test the design through the system console.

Note: The design example targets the Intel Agilex F-Series Transceiver-SoC DevelopmentKit. The design includes an .sdc script as well as a .qsf file with verified constraintsin loopback mode. If you use the design example with another device or developmentboard, you may need to update the device setting and constraints in the .qsf file.

To use the system console script, navigate to the ./ed_hwtest/system_consoledirectory. Source the sliv_etile.tcl script. The system console script providesuseful commands for reading statistics and enables you to control various features inthe design.

Table 10. System Console Commands for Hardware Testing

Command Function

list_jtag Displays a list of JTAG master indexes that are connected to your board.

set_jtag <jtag master_index number> Selects the JTAG master.

continued...


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Command Function

• To enable internal and external loopback, use the JTAG master indexnumber of phy_1/phy_jtag_m JTAG node.For example, the JTAG master index of phy_1/phy_jtag_m JTAGnode shown in the following JTAG list is 2. Type set_jtag 2 toselect JTAG master index 2. Next type the enable internal or externalloopback commands.

% list_jtagAvailable JTAG Masters:0: /devices/<JTAG_port>/phy_0/master1: /devices/<JTAG_port>/phy_0/demo_jtag_m.master2: /device/<JTAG_port>/phy_1/phy_jtag_m.master

• To perform commands other than internal and external loopback, useJTAG master index number of phy_0/demo_jtag_m JTAG node.For example, the JTAG master index of phy_0/demo_jtag_m JTAGnode shown in the following JTAG list is 1. Type set_jtag 1 toselect JTAG master index 1. Next type the system console commandthat you want to use.

% list_jtagAvailable JTAG Masters:0: /devices/<JTAG_port>/phy_0/master1: /devices/<JTAG_port>/phy_0/demo_jtag_m.master2: /device/<JTAG_port>/phy_1/phy_jtag_m.master

Note: After programming the .sof file, perform eithersl4_link_init_int_lpbk or sl4_link_init_ext_lpbkbefore running the design example for proper transceivercalibration.

sl4_link_init_int_lpbk Enables TX to RX internal serial loopback within the transceiver andperforms the specific transceiver calibration flow.

sl4_link_init_ext_lpbk Enables TX to RX external loopback and performs the specific transceivercalibration flow.

traffic_gen_enable Enables the traffic generator and checker.The simulation runs in basic or pure streaming mode by default whenthe traffic generator is enabled.

traffic_gen_disable Disables the traffic generator and checker.

tx_source_traffic_reset Resets the TX datapath for the DCFIFO and traffic generator.

rx_sink_traffic_reset Resets the RX datapath for the DCFIFO and traffic checker.

read_error_statistic Displays the error statistics.

continuous_mode_en Resets the TX and RX core (MAC and PHY) and enables the trafficgenerator to generate continuous (single continuous data generation)traffic stream.

burst_mode_en Resets the TX and RX core (MAC and PHY) and enables the trafficgenerator to generate a burst (multiple burst packet data generation)traffic stream.

crc_err_inject_pulse Enables CRC error injection for all lanes.

slave_test_mode_enable This option disables the traffic generator/checker and enables the trafficto flow from sink to source. This option is only available for hardwaresetup with master and slave configuration using two differentdevelopment kits.

slave_test_mode_disable This option disables data flow from sink to source. Select option 1 toenable the data generator and data checker.


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Figure 10. Example of System Console Printout

Figure 11. Example of System Console Printout for Traffic Statistics

All transactions are successful when traffic checker detects no errors.

The number of words transferred in a test.

In addition to this command script, you can also use the Serial Lite IV IP toolkit forreal-time troubleshooting during active link operation.

Related Information

Serial Lite IV IP Toolkit on page 26


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3.5. Error Handling

The Serial Lite IV IP detects error conditions and the behaviors in response to theseerror conditions.

Table 11. Error Condition BehaviorIn this table, N represents the number of lanes.

Signal Width Location Direction Clock Domain Error Indication

tx_error 5 Top-levelsignal

Output tx_core_clkout Not used.

rx_error (N*2*2)+3(PAM4mode)

(N*2)*3(NRZ mode)

Top-levelsignal

Output rx_core_clkout When asserted, indicatesan error condition on theRX datapath.• [(N*2+2):N+3] =

Indicates PCS error fora specific lane.

• [N+2] = Indicatesalignment error. Re-initialize lanealignment if this bit isasserted.

• [N+1]= Indicates datais forwarded to theuser logic when userlogic is not ready.

• [N] = Indicates loss ofalignment.

• [(N-1):0] = Indicatesthe data contains CRCerror.

tx_adaptation_fifo_full

1 Top-level TXDCFIFOsignal

Output TX user clock This vector indicates thewrite domain TX buffer isfull and cannot acceptdata.

rx_adaptation_fifo_full

1 Top-level TXDCFIFOsignal

Output TX user clock This vector indicates thewrite domain RX buffer isfull and cannot acceptdata.

readfull 1 Top-level RXDCFIFOsignal

Output RX user clock This vector indicates theread domain buffer is fulland cannot accept data.

Related Information

FIFO Intel FPGA IP User Guide

3.6. Link Debugging Sequence

The Serial Lite IV IP provides a link debugging sequence for TX and RX that you canuse when debugging your design.


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https://www.intel.com/content/www/us/en/programmable/documentation/eis1414462767872.html#eis1414462854553


Figure 12. TX Link Debugging Flowchart

Start

No

Yes Yes

No

Yes Note: If rx_link_up status = 0, you need to debug the RX link.

No

tx_link_upAsserted?

* Resets = tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, and reconfig_reset

Check Transceiver Reference Clock

Check if tx_serial_data and rx_serial_data are connected

Check if the resets* are out of reset for at least 10 clock cycles

Check rx_link_up Status

No

pll_lockedAsserted?

phy_tx_lanes_stableAsserted?

phy_ehip_readyAsserted?

Table 12. TX Link Debugging Signals

Signal Location Description

tx_link_up Top-level TX signal The IP asserts this signal to indicate that theinitialization sequence is complete and the IP is readyto transmit the data.

tx_pll_locked Top-level PHYsignal

This active-high signal indicates that the transceiversare locked to the reference clock.

phy_tx_lanes_stable Top-level PHYsignal

The IP asserts this signal when TX datapath is readyto send data.

phy_ehip_ready[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal after thetx_pcs_fec_phy_reset_n andrx_pcs_fec_phy_reset_n signals deassert toindicate that the custom PCS has completed internalinitialization and is ready for transmission.


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Figure 13. RX Link Debugging Flowchart

Start

No

Yes Yes

No No

rx_link_upAsserted?

* Resets = tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, and reconfig_reset

Check Transceiver Reference Clock

Check if tx_serial_data and rx_serial_data are connected

Check if the resets* are out of reset for at least 10 clock cycles

No

phy_rx_pcs_readyAsserted?

phy_rx_block_lockAsserted?

phy_ehip_readyAsserted?

Yes RX Ready to Receive Data

Table 13. RX Link Debugging Signals

Signal Location Description

rx_link_up Top-level RX signal The IP asserts this signal to indicate that theinitialization sequence is complete, and the IP isready to receive data.

phy_rx_pcs_ready[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal when RX datapath is readyto receive data.

phy_rx_block_lock[(n*2)-1:0] Top-level PHYsignal

The IP asserts this signal to indicate the 66b blockalignment has completed for the lanes.

Related Information

Serial Lite IV Intel FPGA IP User Guide: Serial Lite IV Intel FPGA IP Interface Signals


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3.7. Serial Lite IV IP Toolkit

The Serial Lite IV IP toolkit is an inspection tool that monitors the status of a SerialLite IV IP link and provides a step-by-step guide for the IP link initializationsequences.

The Serial Lite IV IP toolkit mainly monitors the following:

• MAC link up status

• Hardened Custom PCS lane alignment status

• Clock data recovery (CDR) lock

• Traffic generator and checker statistics

• Forward Error Correction (FEC) statistics

The IP link initialization sequences guide also includes CSRs to monitor and log errorsthat occur during the operation.

Note: The toolkit uses hardened customer PCS core and MAC output ports to provide real-time link status. Therefore, the toolkit can only work with the design files with thesettings you set during the design example generation. Any modifications to thegenerated design files may cause the toolkit to work incorrectly.

Related Information

Hardware Testing on page 20

3.7.1. Setting Up and Running the Toolkit

To run the toolkit, follow these steps:

1. Generate the design example after you specify the parameters.

2. Compile the design example to generate a .sof file.

3. In the Intel Quartus Prime Pro Edition software, select Tools ➤ SystemDebugging Tools ➤ System Console to launch the system console.

4. In the System Console, click Load Design and select the .sof file for thedesign example.

5. Under the list of Instances, select sliv_ip_toolkit_1.3.

6. Under the Details pane, select Serial Lite IV IP Toolkit and click Open Toolkit.


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Figure 14. Launch the Serial Lite IV IP Toolkit

5

6

7

7

When the toolkit is up and running, set JTAG master by following the instructionsgiven in the display window.

Figure 15. Setting JTAG Master

Ensure that you specify the same settings as your design example

Related Information

Analyzing and Debugging Designs with System Console


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3.7.2. Toolkit GUI Settings

The Serial Lite IV IP toolkit offers an easy-to-manage user interface.

The Serial Lite IV IP toolkit user interface has four tabs.

• The GUI configuration tab lets you set the JTAG master settings to enablecommunication between the development kit and toolkit.

• The MAC and PHY tab implements various CSR for both the hardened customPCS core and the MAC soft logic.

• The Traffic Statistics and Bandwidth Performance tab implements variousCSR for the Demo Management module to configure the traffic generator andchecker. Additionally, the tab also provides a real-time bandwidth calculationmeasurement result based on the traffic modules instantiated in the exampledesign.

• The Help tab provides useful next-step troubleshooting information based on theassertion and deassertion of specific status registers or output ports if any errorshappen after the link initialization is executed.

The MAC and PHY tab shows a step-by-step guide for link initialization and real-timestatus monitoring of a Serial Lite IV IP link.

The toolkit continuously reads and displays all of the essential status registers relatedto the Serial Lite IV IP link after you execute the following stages:

1. Click Assert system reset and Deassert system reset to perform a full systemreset.

2. Click Link initialization to perform link initialization with internal/externalloopback enabled.

3. Click Read status to poll all corresponding status registers and output ports fromboth hardened custom PCS and MAC soft logic.

4. Click Read FEC statistics to generate the FEC statistics report after steps 1–3complete successfully and the link is up and running.

Figure 16. MAC and PHY Tab

Note: The toolkit user interface changes dynamically to illustrate each execution stage.


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In case of any failure, the toolkit diagnoses the failure based on the various statusbits. These status bits are based on the register bank or output port from thehardened custom PCS core or MAC soft logic. The corresponding next-step debugginginformation is displayed in the Help tab.

Figure 17. Traffic Statistics and Bandwidth Performance Tab

You can configure the traffic generator and checker to run in user-specified modeusing the Traffic Statistics and Bandwidth Performance tab. You can turn on theSink RX to Source TX parameter to run the hardware design example in slave mode.When this parameter is enabled, the traffic flows from sink to source. You can alsoread the traffic statistics in this tab. Additionally, the toolkit also calculates anddisplays the real-time effective bandwidth based on the design example.

Figure 18. Help Tab

The Help tab provides useful next-step debugging information based on the errors orstatus registers reported from the MAC and PCS status in the MAC and PHY tab.


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4. Serial Lite IV Intel Agilex FPGA IP Design Example UserGuide Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions upto v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPcores have a new IP versioning scheme.If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version User Guide

1.2.0 Serial Lite IV Intel Agilex FPGA IP Design Example User Guide

1.1.0 Serial Lite IV Intel Agilex FPGA IP Design Example User Guide

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https://www.altera.com/en_US/pdfs/literature/ug/archives/ug-dex-ag-sl4-1-2-0.pdf

https://www.altera.com/en_US/pdfs/literature/ug/archives/ug-dex-ag-sl4-1-1-0.pdf





5. Document Revision History for the Serial Lite IV IntelAgilex FPGA IP Design Example User Guide

Document Version Intel QuartusPrime

IP Version Changes

2020.04.13 20.1 1.2.0 • Added slave test mode feature in the hardwaredesign example.

• Added example of hardware design example systemconsole test result in the Compiling and Testing theDesign topic.

• Updated the description for set_jtag command inthe System Console Commands for HardwareTesting table.

• Updated the steps to set up and run the toolkit inthe Setting Up and Running the Toolkit topic.

• Updated the Example Design Tab figure in theDesign Example Parameters topic.

• Updated the development kit name to Agilex F-Series Transceiver-SoC Development Kit.

2019.12.16 19.4 1.2.0 • Added information for hardware design example.• Updated Directory and File Description for Design

Example Folder table.• Added information to launch, configure, and run the

Serial Lite IV IP Toolkit.

2019.09.30 19.3 1.1.0 Initial release.

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