Intel® Agilex™ I-Series FPGA Development Kit User Guide

Intel® Agilex™ I-Series FPGADevelopment Kit User Guide

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Contents

1. Overview........................................................................................................................ 31.1. Block Diagram.......................................................................................................31.2. Box Contents........................................................................................................ 51.3. Operating Conditions..............................................................................................5

2. Getting Started............................................................................................................... 72.1. Installing Intel Quartus® Prime Software.................................................................. 7

2.1.1. Activating Your License...............................................................................72.2. Development Board Package................................................................................... 72.3. Installing the Intel FPGA Download Cable II Driver..................................................... 8

3. Development Board Setup.............................................................................................. 93.1. Applying Power to the Development Board................................................................ 93.2. Default Switch and Jumper Settings....................................................................... 10

3.2.1. Default Setting........................................................................................ 103.2.2. Factory Reset.......................................................................................... 123.2.3. Perform Board Restore through Board Test System (BTS) GUI........................123.2.4. Control On-Board Clock through Clock GUI..................................................13

4. Revision History............................................................................................................14

A. Development Kits Components..................................................................................... 15A.1. Board Overview...................................................................................................15A.2. Intel Agilex I-Series FPGA..................................................................................... 16A.3. PCIe and CXL Interfaces....................................................................................... 16A.4. MCIO Connector.................................................................................................. 16A.5. MCIO Cable Assembly Information......................................................................... 18A.6. Network Interfaces.............................................................................................. 18A.7. Port Controller.....................................................................................................19A.8. FPGA Configuration.............................................................................................. 20A.9. Supported Configuration Modes............................................................................. 21A.10. Memory Interfaces............................................................................................. 22A.11. I2C.................................................................................................................. 23A.12. Clock Circuits.................................................................................................... 24A.13. System Power................................................................................................... 24

A.13.1. Power Guidelines....................................................................................25A.13.2. Power Distribution System.......................................................................26A.13.3. Power Sequence.................................................................................... 27A.13.4. Power Measurement............................................................................... 28

A.14. Temperature Monitoring......................................................................................29A.15. Mechanical Requirements....................................................................................29A.16. Board Thermal Requirements...............................................................................30A.17. Board Operating Conditions.................................................................................31A.18. Over Temperature Warning LED........................................................................... 31

Contents

Intel® Agilex™ I-Series FPGA Development Kit User Guide Send Feedback

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1. OverviewThis user guide describes the design features and the usage of the Intel® Agilex™ I-Series FPGA Development Kit board.

Table 1. Intel Agilex I-Series FPGA Development Kit Ordering Information

Version Ordering Code

AGIB027R29A1E2VR0 DK-DEV-AGI027RES

For the board and FPGA capabilities, refer to the Intel Agilex FPGA and SoC page onthe Intel website.

1.1. Block Diagram

This board is used as a demonstration board to showcase and evaluate theperformance features and operation of the Intel Agilex I-Series device in the F2957FBGA package featuring R-tile transceivers with PCIe* Gen5 x16 and CXL interfacesand F-tile transceivers with 28G x8 or 56G x8 QSFPDD interfaces. The board supportstwo on-board DDR4 x72 with ECC channels. The board also features a dual DIMMmemory channel for DDR4 and DDR-T.

Figure 1. Intel Agilex I-Series FPGA Development Kit Board Diagram

x16

28G/56Gx8

28G/56Gx8

x72AVST x8

x72

Dual x8

GPIO

x72, 2-DPC

I2C

TempDiodes

All VoltagesVoltage Sense

Inputs

All Clocks

Seq Ctrl

GPIOs,Push-buttons,

LEDsIntel MAX 10

FPGAPower Seq.

PowerMonitor

JTAGJTAG HeaderI2C

I/Os

JTAG

Aux 12VConn

+12V fromPCIe Gold

Fingers

Dual DIMMDDR4 / DDR-T

15AR-Tile

x16

15CR-Tile

x16

14CR-Tile

x16

CXL/PCIe Gen 5 x16Edge Conn

QSFPDD -2

QSFPDD -1

USBConn

CXL/PCIe Connectorx2 MCIO

Aux12V

SDM 2B 2E 2F 2C

TempSense

PowerRegulators

Hot-Plug andPWR or CKT

Clocks

Intel® MAX® 10FPGA

Intel FPGADownload Cable II

JTAG SWI2C CTRLConfig QSPI

2 Gb Flash

Comp -CH0DDR4 x72 with ECC

Comp -CH1DDR4 x72 with ECC

12AF-Tilex20

GPIO3A 3B 3C 3D HPS

USBPHY

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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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Feature Summary

• Intel Agilex I-Series (AGIB027) device in the 2957A BGA package

— 0.8 VID-adjustable VCC core

— R-tile transceivers supporting PCIe Gen5/CXL

— F-tile transceivers supporting 56 Gbps NRZ

• FPGA Configuration

— Partial reconfiguration support

— Configuration via Protocol (CvP) configuration support

— 2 Gb QSPI flash

— Storage for two configuration images in flash (factory and user)

— JTAG header for device programming

— Built-in Intel FPGA Download Cable II for device programming

• Programmable Clock Sources

— 156.25 MHz differential LVDS for F-tile (QSFPDD)

— 100.000 Mhz HCSL for PCIe and CXL (R-tile)

— 33.33 Mhz differential LVDS for memory

— 125 Mhz configuration clock

— 100 MHz differential LVDS for I/O banks

• Transceiver Interfaces

— PCIe x16 interface supporting the Gen5 end-point mode connected to a x16PCIe edge connector (gold edge fingers)

— 2x standard QSFPDD optical module interfaces connected to the F-tiletransceivers

— 1x PCIe/CXL interface supporting CXL x16 or PCIe x16 at 32 Gbps via a MCIOconnector

• Memory Interfaces

— Two on-board independent single rank DDR4 x72 (ECC) channels operating at1200 MHz (DDR4-2400)

— Two DIMM sockets supporting dual DIMM for DDR4 or Intel Optane™ Persistentmemory module

• Communication Ports

— 2x QSFPDD optical interface port

— JTAG header

— USB (Micro USB) on-board Intel FPGA Download Cable II

— System I2C header

1. Overview

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• Buttons, Switches, and LEDs

— System Reset Push-button

— CPU Reset Push-button

— PCIe Reset Push-button

— Four dedicated User LEDs

— Link LED of each QSFP28 port to indicate the link and data transceiver

— Two dedicated configuration status LEDs

• Heatsink and Fan

— Air-cooled heatsink assembly

— Red Over-Temperature Warning LED Indicator

• Power

— PCIe input power including required 2x4 aux power connector

— Blue Power-On LED

— On/Off Slide Power Switch for benchtop operation

— On board power and temperature measurement circuitry

• Mechanical

— PCIe standard height form factor (full height, 3/4 length, dual-width)

— 4.376” x 10.0” board size

— 2 slots height with heatsink

• Operating Environment

— Maximum ambient temperature of 0–35°C

1.2. Box Contents

Intel Agilex I-Series FPGA Development board, DDR4 DIMM module, USB2.0 Micro-USB cable, 240W power adapter, and NA/EU/JP/UK cords.

Note: Only one DIMM module is provided with each development kit.

1.3. Operating Conditions

Table 2. Recommended Operating Conditions

Operating Condition Range

Recommended ambient operating temperature range 0°C to 35°C

Maximum ICC load current 198 A

Maximum ICC load transient percentage 30%

Maximum FPGA power supported by the suppliedheatsink/fan

180 W

Handling Precautions

When handling the board, it is important to observe static discharge precautions.

1. Overview

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Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board.

Caution: This development kit should not be operated in a vibration environment.

1. Overview

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2. Getting Started

2.1. Installing Intel Quartus® Prime Software

The new Intel Quartus® Prime Design Suite design software includes everythingneeded to design for Intel FPGAs, SoCs, and CPLDs from design entry and synthesis tooptimization, verification, and simulation. The Intel Quartus Prime Design Suitesoftware includes an additional Spectra-Q® engine that is optimized for future devices.The Spectra-Q engine enables new levels of design productivity for next generationprogrammable devices with a set of faster and more scalable algorithms, a hierarchicaldatabase infrastructure, and a unified compiler technology.

The Intel Quartus Prime Design Suite software is available in three editions based onspecific design requirements: Pro, Standard, and Lite Editions. The Intel Agilex I-Series FPGA Development Kit is supported by the Intel Quartus Prime Pro Edition.

Intel Quartus Prime Pro Edition: The Intel Quartus Prime Pro Edition is optimized tosupport the advanced features in Intel's next generation FPGAs and SoCs, startingwith the Intel Arria® 10 device family and requires a paid license.

Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software,Nios® II EDS, and the MegaCore IP Library. To install Intel's development tools,download the Intel Quartus Prime Pro Edition software from the Intel Quartus PrimePro Edition page in the Download Center of Intel's website.

2.1.1. Activating Your License

Before using the Intel Quartus Prime software, you must activate your license, identifyspecific users and computers, and obtain and install license file. If you already have alicensed version of the Intel Quartus Prime Standard Edition or Intel Quartus PrimePro Edition, you can use that license file with this kit. If not, follow these steps:

1. Log on at the My Intel Account Sign In web page and click Sign In.

2. On the My Intel Home web page, click the Self-Service Licensing Center link.

3. Locate the serial number printed on the side of the development kit box below thebottom bar code. The number consists of alphanumeric characters and does notcontain hyphens.

4. On the Self-Service Licensing Center web page, click the Find it with yourLicense Activation Code link.

5. In the Find/Activate Products dialog box, enter your development kit serialnumber and click Search.

2.2. Development Board Package

Download the Intel Agilex I-Series FPGA Development Kit package from the IntelAgilex FPGA Development Kit page of the Intel website.

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https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html

https://www.intel.com/content/www/sign-in.html

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Unzip the Intel Agilex I-Series FPGA Development Kit package.

Figure 2. Installed Development Kit Directory Structure

<package rootdir>

board design files

demos

documents

examples

factory recovery

Table 3. Installed Development Kit Directory Description

Directory Name Description of Directory Contents

board_design_files Contains schematic, layout, assembly, and bill of materialboard design files. Use these files as a starting point for anew prototype board design.

demos Contains demonstration applications when available.

documents Contains documentation.

examples Contains sample design files for this board.

factory_recovery Contains the original data programmed onto the boardbefore shipment. Use this data to restore the board with itsoriginal factory content.

Related Information

Intel® Agilex™ I-Series FPGA Development Kit

2.3. Installing the Intel FPGA Download Cable II Driver

The development board includes integrated Intel FPGA Download Cable II circuits forFPGA programming. However, for the host computer and board to communicate, youmust install the on-board Intel FPGA Download Cable II driver on the host computer.

Installation instructions for the on-board Intel FPGA Download Cable II driver for youroperating system are available on the Intel website.

On the Cable and Adapter Drivers Information web page of the Intel website, locatethe table entry for your configuration and click the link to access the instructions.

2. Getting Started

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https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-agi-fpga.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/drivers/dri-index.html


3. Development Board SetupThis chapter describes how to apply power to the development board and providesdefault switch and jumper settings.

3.1. Applying Power to the Development Board

This development kit is designed to operate in two modes:

As a PCIe Add-In Card

When operating the card as a PCIe system, insert the card into an available PCIe slotand connect a 2x4 pin PCIe power cable from the system to power connectors at J11of the board.

Note: When operating as a PCIe add-in card, the board will not power on unless power issupplied to J11.

In Bench-Top Mode

In bench-top mode, you must supply the board with the provided power 240W powersupply connected to the power connector J11. The following describes the operation inbench-top mode.

This development board ships with its switches preconfigured to support the designexamples in the kit.

If you suspect that your board may not be correctly configured with the defaultsettings, follow the instructions in the Default Switch and Jumper Settings on page10.

1. Connect the supplied power supply to an outlet and the DC Power Jack (J11) onthe FPGA board.

Note: Use only the supplied power supply. Power regulation circuits on the boardcan be damaged by power supplies with greater voltage.

2. Set the power switch (SW6) to the ON position.

When the board powers up, the blue power LED illuminates and the board is readyfor use.

The Blue LED (D6) should also illuminates indicating that all the power rails on theboard are good. If the POWER GOOD LED (D6) is not illuminated, it indicates that thepower supply malfunctioned, and the board will not power up.

Caution: The standby powers are always present as soon as the Aux power is applied to J11.Use power switch SW6 to start the board.

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3.2. Default Switch and Jumper Settings

This section guides you how to restore the default factory settings and provides theirfunctions.

3.2.1. Default Setting

The Intel Agilex I-Series FPGA Development Kit ships with its board switchespreconfigured to support the design examples in the kit. If you suspect your boardmight not be correctly configured with the default settings, follow the instructions inthe Table 4 on page 10 to return to its factory settings before proceeding.

Table 4. Factory Default Switch Settings

Note: X refers to Don't Care in this table.

For more information, refer to Figure 4 on page 15.

Switch Default Position Function

SW1[1:4] ON/OFF/OFF/OFF PCIe PRSNT x1/x4/x8/x16 settings. Default = x16.

PCIe PRSNT x16 PCIe PRSNT x8 PCIe PRSNT x4 PCIe PRSNT x1

ON OFF OFF OFF

SW2[1:4] ON/OFF/OFF/X Configuration mode setting bits.

Mode MSEL0 MSEL1 MSEL2 Reserved

JTAG OFF OFF OFF X

AVST x8 ON OFF OFF X

SW3[1:4] OFF/OFF/OFF/OFF Type ON (Close) OFF (Open)

1: Si5391 ClockEnable

Disable all clocks Enable all Clocks

2: CXL REFCLK Select On-board REFCLK CLK from CXLConnector

3: PCIe REFCLK Select On-board REFCLK CLK from PCIeConnector

4: Si52204 ClockEnable

Disable all clocks Enable all Clocks

SW4 OFF/OFF/OFF/OFF Type ON (Close) OFF (Open)

1: FPGA I2C Enable MAIN I2C bus disable MAIN_I2C busenable

continued...

3. Development Board Setup

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Switch Default Position Function

2: FPGA I2C_2 Enable I2C2 Bus disable I2C2 Bus enable

3: Main PMBUS Enable CORE PMBUS disable CORE PMBUS enable

4: FPGA PMBUSEnable

SDM_I2C Bus disable SDM_I2C Busenable

SW5[1:4] OFF/OFF/OFF/X On-board Intel FPGA Download Cable II is the JTAG master when theexternal JTAG header (J10) is unoccupied.

Type ON OFF

1: JTAG input source PCIe EP Edgeconnector

On-Board IntelFPGA DownloadCable II

2: FPGA Bypass Bypass FPGA FPGA in JTAG chain

3: Intel MAX® 10JTAG Select

Intel MAX 10 JTAGEnable

Intel MAX 10 JTAGDisable

4: Not used X X

SW6 ON/OFF Power ON or OFF the board.

Table 5. Connectors on the Development Kit

Board Reference Type Description

J11 Auxiliary power connector For the external 12V auxiliary powersupply or power adapter

J12 I2C/PMBus connector For accessing core power controller

J13 I2C connector For accessing to the main I2C1 bus

J3 QSFPDD_0 connector —

J4 QSFPDD_1 connector —

J8 USB connector For programming the FPGA using on-board Intel FPGA Download Cable II

J10 External JTAG header For use with the external downloadcable

J1 DIMM A connector DDR4/DDRT Dual DIMM A

J2 DIMM B connector DDR4/DDRT Dual DIMM B

J5 PCIe x16 Gold Finger —

J6, J7 CXL/PCIe connectors For connecting the external CXL/PCIecables

J24 Fan connector For connecting to the heatsink coolingfan


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Table 6. LEDs on the Development Kit


D1 QSFPDD_0 Link/Activity LED Green LED - User defined

D2 QSFPDD_0 Link/Activity LED (Dualcolor)

Yellow LED – User definedGreen LED - User defined

D3 QSFPDD_1 Link/Activity LED Green LED - User defined

D4 QSFPDD_1 Link/Activity LED (Dualcolor)

Yellow LED – User definedGreen LED - User defined

D5 USER LED 0 Green LED for USER LED 0




D6 POWER GOOD LED Blue LED:• ON: All powers are good.• OFF: Power failure

D11 CONFIG DONE LED Green LED:• ON: FPGA configuration successful• OFF: FPGA configuration failed

D9 Over Temp LED Red LED:• ON: FPGA over temperature

condition

Table 7. Push-Buttons on the Development Kit


S1 CPU Reset Push to reset FPGA

S2 PCIe Reset Push to reset PCIe bus

S3 CXL Reset Push to reset CXL bus

S4 USB PHY Reset Push to reset on-board USB PHY

S5 QSFPDD_1 Reset Push to reset F-tile for QSFPDD_1 port

3.2.2. Factory Reset

This section is part of the board test system (BTS) GUI that is currently indevelopment. This section will be updated when the information is available in thefuture version of this user guide.

3.2.3. Perform Board Restore through Board Test System (BTS) GUI

The development kit ships with FPGA design examples stored in the QSPI flash deviceand system Intel MAX 10 pre-programmed. If you want to restore board QSPI flashwith factory default image, follow these steps:

1. Connect the USB cable between J8 USB connector and your computer.

2. Open Intel Quartus Prime Programmer GUI, detect the JTAG chain, attach thefactory default image on system Intel MAX 10 device.

3. Select programming options and click the program button.


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3.2.4. Control On-Board Clock through Clock GUI

The Clock Controller application can change the on-board Si53XX programmableoscillators to any customized frequency between 0.2 MHz and 800 MHz.

The Clock Control application (ClockControl.exe) runs as a stand-alone applicationand resides in the <package dir>\examples\board_test_system directory.

The Clock Control communicates with the System Intel MAX 10 device through eitherUSB port J8 or 10 pin JTAG header J10. Then, System Intel MAX 10 controls theseprogrammable clock parts through a 2-wire serial bus.


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4. Revision HistoryTable 8. Revision History of the Intel Agilex I-Series FPGA Development Kit User

Guide

DocumentVersion

Changes

2021.11.17 Updated the PCIe REFCLK Select function in the SW3[1:4] switch row in Table: Factory Default SwitchSettings.

2021.09.24 Initial release.

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A. Development Kits ComponentsThis chapter introduces all the major components on the development board. Acomplete set of schematics, a physical layout database, and GERBER files for thedevelopment board reside in the development kit documents directory.

A.1. Board Overview

Images of the Intel Agilex I-Series FPGA development board are shown below.

Figure 3. Intel Agilex I-Series FPGA Development Board Image—Front

J12

J11

SW6

J7J9

J13J6J1J2J5

J8

J4

J3S1S2S3S4S5D6D9

D11D5D7D8

D10

Figure 4. Intel Agilex I-Series FPGA Development Board Image—Back

SW2

SW3

SW4

SW5

SW1

AGIPCIE8000001

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A.2. Intel Agilex I-Series FPGA

Intel Agilex I-Series FPGA 56 mm x 45 mm package:

• Part Number: AGIB027R29A1E2VR0

• 2957-Ball FBGA Package

• 2.7M LEs

• 8528 digital signal processing (DSP) blocks

• 17056 18x19 Multipliers

• LVDS pairs supporting 1.6 Gbps

• 3x R-tile supporting PCIe Gen5 x16 (32Gb/s) or CXL x16

• 1x F tile transceiver supporting 56Gbps NRZ

A.3. PCIe and CXL Interfaces

The Intel Agilex I-Series FPGA Development Kit supports two PCIe Gen5 x16interfaces using the FPGA’s two R-tiles, refer to Figure 1 on page 3.

1. One R-tile (14C) supports PCIe x16 connecting to the development kit's PCIe edgeconnector. This interface supports PCIe x1, x4, x8, and x16 PCIe Endpoint.

2. One R-tile (15C) connects to two 74-pin MCIO connectors that can be used as CXL(x8 or x16) or PCIe x16 interface in the Endpoint or Root Port mode. The MCIOconnectors also carry SMBus/I2C, clock, and GPIO signals.

A.4. MCIO Connector

The CXL or PCIe interface is connected to two 74-pin MCIO connectors for 16 channelsof transmit and receive signals of the R-tile (15C). Cables are used to connect this CXLor PCIe link from the development kit to the host board or application-specificdaughter cards.

A. Development Kits Components

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Figure 5. MCIO Connector

J7

J6

MCIO Connectors forCXL/PCIe Interface


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Figure 6. MCIO Connector CircuitJ6

GND_A1CXL_RX_P0CXL_RX_N0

CXL_RX_P1CXL_RX_N1

CXL_PRSNTx1_N

CXL_RX_P2

CXL_RX_P3

CXL_RX_N2

CXL_RX_N3

CXL_RX_P4CXL_RX_N4

CXL_RX_P5

CXL_RX_P6

CXL_RX_N5

CXL_RX_N6

CXL_RX_P7CXL_RX_N7

CXL_PERST1_NCXL_PRSNTx4_N

0, DNIR187

I2C2_SCL 27, 46, 50, 52I2C2_SDA 27, 46, 50, 52

CXL_PERSTn 33, 48, 52

RX0_0PRX0_0NGND_A4RX0_1PRX0_1NGND_A7SMB0_SCLSMB0_SDAGND_A10PERST0_NPRSNT0_NGND_A13RX0_2PRX0_2NGND_A16RX0_3PRX0_3NGND_A19RX1_0PRX1_0NGND_A22RX1_1PRX1_1NGND_A25SMB1_SCLSMB1_SDAGND_A28PERST1_NPRSNT1_NGND_A31RX1_2PRX1_2NGND_A34RX1_3PRX1_3NGND_A37

MH1MH3

GND_B1 CXL_TX_C_P0 C354 0.22uF SMC0201IA CXL_TX_P0

0.22uF SMC0201IA

49 CXL_SMB_ALERT_N

CXL_TX_N10.22uF SMC0201IA CXL_TX_P1

0.22uF SMC0201IA CXL_TX_N0CXL_TX_C_N0 C355

CXL_TX_C_P1 C356CXL_TX_C_N1

CLK_100M_CXL_CONN_C_P R185 0 45 CLK_CXL_CONN_PCLK_100M_CXL_CONN_C_N R186 0 45 CLK_CXL_CONN_N

C357

0.22uF SMC0201IA CXL_TX_P2CXL_TX_C_P2 C358

0.22uF SMC0201IA CXL_TX_P3CXL_TX_C_P3 C3600.22uF SMC0201IA CXL_TX_N3CXL_TX_C_P3 C361

0.22uF SMC0201IA CXL_TX_P4CXL_TX_C_P4 C3620.22uF SMC0201IA CXL_TX_N4CXL_TX_C_N4 C363





TX0_0PTX0_0N

GND_B4TX0_1PTX0_1N

GND_B7NC_B8

SMB0_ALERT_NGND_B10CLK0_DPCLK0_DNGND_B13

TX0_2PTX0_2N

GND_B16TX0_3PTX0_3N

GND_B19TX1_0PTX1_0N

GND_B22TX1_1PTX1_1N

GND_B25NC_B26


TX1_2PTX1_2N

GND_B34TX1_3PTX1_3N

GND_B37

MH2MH4

MCIO_74P_G97V22312HRK64129-002J7

GND_A1RX0_0PRX0_0NGND_A4RX0_1PRX0_1NGND_A7SMB0_SCLSMB0_SDAGND_A10PERST0_NPRSNT0_NGND_A13RX0_2PRX0_2NGND_A16RX0_3PRX0_3NGND_A19RX1_0PRX1_0NGND_A22RX1_1PRX1_1NGND_A25SMB1_SCLSMB1_SDAGND_A28PERST1_NPRSNT1_NGND_A31RX1_2PRX1_2NGND_A34RX1_3PRX1_3NGND_A37

MH1MH3

GND_B1TX0_0PTX0_0N

GND_B4TX0_1PTX0_1N

GND_B7NC_B8


TX0_2PTX0_2N

GND_B16TX0_3PTX0_3N

GND_B19TX1_0PTX1_0N

GND_B22TX1_1PTX1_1N

GND_B25NC_B26


TX1_2PTX1_2N

GND_B34TX1_3PTX1_3N

GND_B37

MH2MH4

MCIO_74P_G97V22312HRK64129-002

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37

MH1MH3

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37

MH2MH4

CXL_RX_P8CXL_RX_N8

CXL_RX_P9CXL_RX_N9

CXL_PRSNTx8_NCXL_PERST2_N

CXL_RX_P10

CXL_RX_P11

CXL_RX_N10

CXL_RX_N11

CXL_RX_P12CXL_RX_N12

CXL_RX_P13

CXL_RX_P14

CXL_RX_N13

CXL_RX_N14

CXL_RX_P15CXL_RX_N15

CXL_PERST3_NCXL_PRSNTx16_N

0, DNIR189

R188 0, DNI

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32A33A34A35A36A37

MH1MH3

CXL_TX_C_P8 C373 0.22uF SMC0201IA CXL_TX_P8

0.22uF SMC0201IA CXL_TX_N9

Design Note:Clock for RootPort mode.

0.22uF SMC0201IA CXL_TX_P9


CXL_TX_C_P9 C375CXL_TX_C_N9

44 REFCLK_CXL_RP_P144 REFCLK_CXL_RP_N1

C376

0.22uF SMC0201IA CXL_TX_P10CXL_TX_C_P10 C377

0.22uF SMC0201IA CXL_TX_P11CXL_TX_C_P11 C3790.22uF SMC0201IA CXL_TX_N11CXL_TX_C_P11 C380






B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37

MH2MH4

Design Note:Clock for RootPort mode.44 REFCLK_CXL_RP_P0

44 REFCLK_CXL_RP_N0

A.5. MCIO Cable Assembly Information

The cable is not provided with the development kit. For more information, contactIntel for support.

A.6. Network Interfaces

The development kit supports two QSFPDD connectors each, connecting to the IntelAgilex's F-tile (12A) transceivers. Each port can operate at 4x 58G or 8x 28G. Thesetwo ports support ZQSFP56 SR optical modules as well as the 3M DAC electricalcables. A Texas Instruments FPC202 dual-port controller serves as the low-speedsignal aggregator that makes up the Dual 100Gpbs Ethernet interfaces. The FPC202aggregates all low speed and I2C signals across two ports and presents it as a singlemanagement interface to the host.


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The F-tile (12A) of the FPGA provides 16 general-purpose (FGT) transceiver channels,each 8-channel group is routed to one QSFPDD. The transceiver bank requires 156.25MHz clocks for the 28 Gbps NRZ and 325.50 MHz clocks for the 56 Gbps PAM4. Theseclocks must have RPM jitter <250fs.

Figure 7. F-Tile Bank 12A Circuit

A.7. Port Controller

A Texas Instrument FPC202 dual-port controller serves as the low-speed signalaggregator for the two QSFP ports.


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Figure 8. Port Controller Circuit

U14VDD1_1 P0_S0_OUT_A

P0_S0_OUT_B

P0_S0_IN_C

P0_MOD_SCL

P0_S0_OUT_DP0_S0_OUT_C

P0_S1_OUT_BP0_S1_OUT_A

P0_S1_OUT_DP0_S1_OUT_C

P0_MOD_SDA

P0_S0_IN_BP0_S0_IN_A

P0_S1_IN_C

P0_AUX_SDAP0_AUX_SCL

P0_S1_IN_BP0_S1_IN_A

P1_S0_OUT_AP1_S0_OUT_B

P1_S0_IN_AP1_S0_IN_BP1_S0_IN_C

P1_MOD_SDAP1_MOD_SCL

P1_S0_OUT_CP1_S0_OUT_D

P1_S1_OUT_CP1_S1_OUT_D

P1_S1_OUT_AP1_S1_OUT_B

P1_S1_IN_BP1_S1_IN_C

P1_AUX_SCLP1_AUX_SDA

P1_S1_IN_A

40 QSFPDD0_3V3_RESET_L 25QSFPDD0_3V3_LPMODE 25QSFPDD0_3V3_INT_L 25QSFPDD0_3V3_MODPRS_L 25

QSFPDD0_I2C_SDA 25QSFPDD0_I2C_SCL 25

41

38

39373536

3433

5152

44

IO_3p3V45

VDD1_2VDD1_3VDD2_1VDD2_2

CTRL123242821

31

25

4253

819

30

IO_3p3V

22

29

32

5727 DAP (GND)

FPC202RHURQFN-58

C3052.2uF0402

10VX6S

R13710.0k, DNI04021%

R1354.70k04021%

R1344.70k04021%

R13810.0k04021%

GND

CAPL

TEST_N

EN

SPI_LED_SY_NC

GPIO[0]GPIO[1]GPIO[2]GPIO[3]

CTRL2CTRL3CTRL4

PROTOCOL_SEL

HOST_INT_N

IO_3p3V

94354

2026

32, 46, 50, 5232, 46, 50, 52

I2C 8-bit Addr = 0x1E

Place a 1uF and 0.1uF per VDD1 pinPlace a 1uF and 0.1uF per VDD2 pin

IO_3p3V

I2C2_SCLI2C2_SDA

R1314.70k04021%

IO_3p3V

47 QSFPDD_3V3_PORT_INT_N

47 QSFPDD_3V3_PORT_EN

QSFPDD1_3V3_RESET_L 26QSFPDD1_3V3_LPMODE 26QSFPDD1_3V3_INT_L 26QSFPDD1_3V3_MODPRS_L 26

QSFPDD1_I2C_SDA 26QSFPDD1_I2C_SCL 26

4849

56

552

1354

67171811131012141615

504746

IO_3p3V

R1334.70k04021%

R1324.70k04021%

C3040.1uF040225VX6S

C3031uF040225VX6S

C3020.1uF040225VX6S

C3000.1uF040225VX6S

C2991uF040225VX6S

C2971uF040225VX6S

C2951uF040225VX6S

C2980.1uF040225VX6S

C2960.1uF040225VX6S

C3011uF040225VX6S

A.8. FPGA Configuration

You can use the Intel Quartus Prime Programmer to configure the FPGA with yourSRAM Object File (.sof).

FPGA Configuration Setup

Ensure the following:

• The Intel Quartus Prime Programmer and the Intel FPGA Download Cable II driverare installed on the host computer.

• The micro-USB cable is connected to the FPGA development board.

• Power to the board is ON, and no other applications that use the JTAG chain arerunning.

Follow these steps:

1. Start the Intel Quartus Prime Programmer.

2. Click Auto Detect to display the devices in the JTAG chain.

3. Click Change File and select the path to the desired .sof.

4. Turn on the Program/Configure option for the added file.

5. Click Start to download the selected file to the FPGA. Configuration is completewhen the progress bar reaches 100%.

Using the Intel Quartus Prime Programmer to configure a device on the board causesother JTAG-based applications such as the Board Test System and the Power Monitorto lose their connection to the board. Restart those applications after configuration iscomplete.


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Programming the FPGA over Intel FPGA Download Cable II

Figure 9 on page 22 shows the high-level conceptual block diagram for programmingthe FPGA over the embedded Intel FPGA Download Cable II or external downloadcable.

A.9. Supported Configuration Modes

• The development board supports two configuration modes: Avalon®-ST (AVST) x8and JTAG.

• The default configuration is AVST x8 using a 2Gb QSPI flash device.

• JTAG configuration is supported by using either the embedded Intel FPGADownload Cable II or the Intel FPGA Download Cable II dongle.

Avalon-ST (AVST) x8 Mode

The SDM block in the Intel Agilex device controls the configuration process andinterface. The Intel MAX 10 System Controller (U34) interfaces to the Intel AgilexFPGA in the AVST x8 mode. The Intel MAX 10 also interfaces to the QSPI flash in theactive serial (AS) x4 mode. For the AS x4 mode, MSEL[2:0] configuration pinstrapping (SW2) must be set to [110]. The flash device is Micron Technology 1.8Vcore, 1.8V I/O 2 Gigabit CFI NOR-type device (P/N: MT25QL02GBB8E12-0).

JTAG Configuration Mode

The JTAG switch implemented in the Intel MAX 10 System Controller (U34) allows theselection of devices to be included in the JTAG chain. It is done by the settings of theDIP switch SW5. The embedded Intel FPGA Download Cable II (or external downloadcable) or PCIe JTAG can be selected as the source for programming the devices on thechain. The embedded Intel FPGA Download Cable II is the default setting for thisconfiguration mode.


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Figure 9. JTAG Block Diagram

PCIe EPEdge Connector

JTAGMUX

Intel MAX 10Download Cable

JTAG

Analog SWPD[3:0]

Download

Cable

DIP Switch DIP Switch

FPGA

Source Select Enable/Bypass

ExternalHeader

Download CablePHY

The on-board Intel FPGA Download Cable II is implemented in an Intel MAX 10 device.A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data toIntel MAX 10. This allows configuration of the FPGA using a USB cable directlyconnected to a PC running the Intel Quartus Prime software without requiring theexternal download cable dongle. An external download cable dongle can also be usedon J12 to configure the FPGA.

A.10. Memory Interfaces

Three independent memory interfaces are supported: Two independent on-boardDDR4 and one dual DIMM sockets for DDR4 or DDR-T.

• The on-board DDR4 uses five 16Gb DDR4 single rank devices connecting to Bank2B, 2E for memory component channel 0 and bank 2C, 2F for memory componentchannel 1. The total memory size of each channel is 16GB running at 1200MHz.

• The two 288-pin DIMM sockets interface to bank 3C, 3D for Dual DIMM memory.These sockets accept DDR4 module or Intel Optane Persistent memory module(requires Intel-licensed DDR-T protocol IP). These DIMM will support dual rank atfrequency 1200MHZ 16GB per channel, and will support single rank at 1200MHZ8GB per channel.


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A.11. I2C

I2C supports communication between integrated circuits on a board. It is a simpletwo-wire bus that consists of a serial data line (SDA) and a serial clock (SCL). TheIntel MAX 10 and the Intel Agilex devices use the I2C for reading and writing to thevarious components on the board such as programmable clock generators, VIDregulators, analog-to-digital converters (ADC), and temperature sensors.

You can use the Intel Agilex or Intel MAX 10 as the I2C host to access these devices,change clock frequencies or get status information of the board such as voltage andtemperature readings.

Table 9. I2C Device Address

Type Bus Address Device

FPGA/Intel MAX 10 I2CAddress

I2C1 0x74 Si5391

0x6A Si52204

0x4E EM2130H

0x42 EM2140P

0x45 EM2120L

0x46 EM2120L

I2C2 0x1E FPC202

0x57/0x5F M24128

0x38 MAX31730

0x3A MAX31730

0xA0 QSFPDD_0

0xA0 QSFPDD_1

I2C3 0xA0 DDR4_DIMM0

PCIE_EP_3V3_I2C 0xA2 DDR4_DIMM1

Intel MAX 10 I2C Address AVS_I2C 0x47 ED8401

Figure 10. I2C Chain

FPGA UNII MAX10

GPIO GPIO

SDM

DDR4 DMM_1

FPGA_I2C3 I2C3Level

ShifterLevel

ShifterADDR = A0h

DDR4 DIMM_2

ADDR = A2h

GPIO GPIO

GPIOen[3:0]

GPIO

FPGA_I2C3

FPGA_I2C1

I2C3

MAIN_I2C

LevelShifter

en3

LevelShifter

en3

LevelShifter

en3

ADDR = 1?h

QSFPDD_1

ADDR = A0h

QSFPDD_2

ADDR = 47h

EEPROMM24128

Core PowerRegulator

MAX31730#1

ADDR = 57h/5?h ADDR = 35h

MAX31730#2

ADDR = 3Ah

CXL Conn

ADDR = 74h

FPC202

LevelShifter

en1

Si5391

ADDR = 6Ah

Si52204

ADDR = 4Eh

EM2130H

ADDR = 42h

EM2140P

ADDR = 45h

EM2120L#1

ADDR = 45h

EM2120L#2 ADDR = A0h

PCIe_SMBus

PCIe EP Edge

EEPROM24AA024


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A.12. Clock Circuits

All clocks are supplied by three on-board low-jitter programmable clock generatorcircuits. The following is the clock connection diagram to the Intel Agilex FPGA. Fordetailed clock connections, refer to the schematic.

• Si5391 provides most of the clocks to the Intel Agilex I-Series FPGA includingreference clocks for memory interfaces, QSFP_DD, and the FPGA SDM/fabric core.

• Si52204 provides the dedicated reference clock as a local clock option for PCIeGen5 by selecting the inputs of a clock multiplex/buffer Si53307. Another input ofthe clock buffer is from PCIe Edge connector as a system clock of PCIe Gen5.

• Si510 provides a 50MHz clock to System Intel MAX 10 and power Intel MAX 10devices.

Figure 11. Clock Connection Diagram

2B2E2F2C

3A

SDM

12AF-Tile

14CR-Tile

Si53307Mux_buffer

15CR-Tile

3B3C3D

Intel Agilex FPGA

CXL CONN

Si510

Si52204Outputs x4

Si5391Outputs x12

Intel MAX 10Download Cable & Power

DDR4_COMP_CH0, 33.333 MHz, LVDS

DDR4/T_DDIMM, 33.333 MHz, LVDS

156.25 MHz, LVDS322.265625 MHz, LVDS322.265625 MHz, LVDS

156.25 MHz, LVDS156.25 MHz, LVDS

Sys Refclk from edge Conn, 100 MHz, HCSL

Refclk_PCIe Gen5 100 MHz, HCSL

Si53307Mux_buffer

Sys Refclk from CXL Conn, 100 MHz, HCSL

Refclk_PCIe Gen5 100 MHz, HCSL100 MHz, HCSL, for RP in CXL100 MHz, HCSL, for RP in CXL

CLK, 50 MHz, LVCMOS

OSC_CLK_1, 125 MHz, LVCMOS

DDR4_COMP_CH1, 33.333 MHz, LVDS

SYS_CLK, 100 MHz, LVDS

SYS_CLK_BAK, 100 MHz, LVDS

A.13. System Power

This section describes the Intel Agilex I-Series FPGA development board's powersupply.


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A laptop style DC power supply is provided with the development kit. Use only thesupplied power supply. The power supply has an auto sensing input voltage of 100 ~240 V AC power and will output 12 V DC power at 20 A to the development board. The12 V DC input power is then stepped down to various power rails used by the boardcomponents.

An on-board multi-channel analog-to-digital converter (ADC) measures both thevoltage and current for several specific board rails. The power utilization is displayedon a graphical user interface (GUI) that can graph power consumption versus time.

A.13.1. Power Guidelines

The Intel Agilex I-Series FPGA development kit has two modes of operation asdescribed below.

In a Standard PCIe-Compliant System

In this mode, plug the board into an available PCI Express* slot and connect thestandard 2x4 power cords available from the PC's ATX power supply to J11 on theboard. The PCIe slot together with the auxiliary PCIe power cords are required topower the entire board. If you do not connect the 2x4 auxiliary power connection, itwill prevent the board from powering on.

Figure 12. Powering Board Using Standard PCIe-Compliant System

PCIe Slot

ATX PowerSupply

As a Standalone Evaluation Board Powered by Included Power Supply

In this mode, plug the included power supply into the 2x4 pin connector (J11) and theAC power cord of the power supply into a power outlet. This power supply will providethe entire power to the board without the need to obtain power from the PCIe slot.The power switch SW6 controls powering of the board.


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Figure 13. Powering Board Using Included Power Supply

Included Power Supply

A.13.2. Power Distribution System

The following figure below shows the power distribution system on the Intel Agilex I-Series FPGA development board.


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Figure 14. Power Tree Diagram

VCC_HSSI_GXF_ENVCC_HSSI_GXR_ENVCCE_PLL_ENVCCERT_FGT_GXF_EN3p3V_ENIO_1p8V_ENVCCRT_GXR_EN1p2V_DDR4_CH2_EN2p5V_EN1p2V_DDR4_CH01_ENVCCED_GXR_EN1p8V_ENVCCCLK_GXR_ENVCCR_CORE_ENFPGA_VCC_EN

VCCH_ENIO_3p3V_ENVTT_DDR4_Ch2_ENVTT_DDR4_CH01_ENVCCFUSEWR_SDM_EN

VCCPT (4.38A)

VCCL_HPS / VCCH_SDM

VCCPLLDIG_HPS (0.02A)

VCCH_FGT_GXFL_12A (2.62A)

VCCCLK_GXFL (6.4mA)

VCCH (8.1A)

VCC_HSSI_GXRL14C/15A/15C(25.43A)

VCCA_PLL (6.9A)

VCCR_CORE (9.1A)

VCCRT_GXRR_15A/15C

VCCRT_GXRL_14C

1p2V_PRE

1p8V_PRE

2p5V_PRE

3p3V_STBY

VCCERT_FGT_GXFL_12A (6.72A)

VCC_HSSI_GXF_12A (17.26A)VCCL_SDM (0.39A)

DDR-T 12V

17.26A

1.8V1p8V

1.8VIO_1p8V

1p8V_VCCCLK_GXF

1p8V_VCCH_GXR

VCCH_FGT_GXF

1p8V_FLTR

0p9V_VCC_HSSI_GXR

0p9V_VCCL_HPS

0p9V_VCCED_GXR

0p8V_VCCH

1p0V_VCCFUSE_GXR1p0V_VCCCLK_GXRVCCFUSEWR_GXF

1p2V_DDR4_CH01

1p8V_VCCIO_EN

3.3V 0.5A

3.0A

3.0A

1p2V_DDR4_CH2_EN

VTT_DDR4_CH2_EN2p5V_EN0p6V_VREF_DDR4_CH2

0p6V_VTT_DDR4_CH2

VCCIO_PIO_3A/3B/3C/3D1p2V_DDR4_CH2 1p2V_DDR4_CH2

1.2V

0.6V

EN63A0QI

0.6V

EN_12V_G1G2_L

12V_GROUP212V_GROUP1

PWR ON/OFFSwitch

(For bench use)EN_SEQ

12V_GROUP1

5.4AU49

U44

12V_GROUP2

65W(5.4A) PCIe Slot

150W PCIe (12.5A) or240W (20A) Ext Pwr Adapter

U50

Q13

12V_G1

5V

12V

U45

0.9V

0.9V

0.9V

RevB=0.9VRevA=0.95V

RevA -1.8V (Group 2)RevB - 1.2V Group 3)

RevB=0.8VRevA = 0.9V0.8V/0.9V

VCC_HSSI_GXF_EN

4-phase0.8V

3A

0.8V

1.0V

FPGA_VCC_EN

12V

VCCERT_GXF_EN

VCCH_EN

VCC_HSSI_GXR_EN

VCCFUSEWR_SDM_EN

VCCL_HPS_EN

1.0V

2.5V

LDO

POWER_ONPower ON/OFF

Circuit

MAX10PWR SEQ

LTC4357Ideal Diode

Ctlr U51

12VPCIe Slot

Edge Conn

LTM4625 U61

LTC4365Selew Rate

Ctlr

EM2130HU64

LTC4365Selew Rate

Ctlr

ED8401+ET6160 x4

U56,U57,U58,U60

EM2120LU72

LTC7151SU68

LTC4357Ideal Diode

Ctlr

12VATX 2x4

Pwr Conn

LTC4359Ideal Diode

Ctlr U48POWER_ON

12V_G2

3p3V_EN

IO_3p3V_ENLTC4365

Selew RateCtlr

0.02AFB29

VCC (174A) / VCCP (21.34A)

VCCPLLDIG_SDM (0.02A)

VCCRT_FGT_GXF_EN

VCCR_CORE

VCCE_PLL_EN

VCCE_PLL_DTS_GXR

2p5V

VTT_DDR4_CH01_EN

0p6V_VREF_DDR4_CH01

0p6V_VTT_DDR4_CH010.6V

U83

UB4

J11

J5

SW6

0.6V

1.0V 0.3A1.0V 1.5A1.0V 0.3A

FB31

FB1

FB26

VCCR_CORE

VCCA_PLL_FLTR

FB30

FB32

FB33DNI

1.2V

U875.4A ( 2.7A x2)

IO_3p3V

3.3V 3p3V_STBY

1.2V 1p2V_PRE

1.8V

2.5V

12.28A1p0V_VCCRT_GXR

RevA -Use EM2120H

1.0V

1.2V/1.8V

1p8V_PRE

2p5V_PRE

2.4V

1.0VLDO

BuckLDO

1.0V1.0V

0 12V/5V/1p8V_PRE/3p3V_STBY/1p2V_PRE/2p5V_PRE

1 Group1 2 Group2 3 Group3

Board Power on

Power Sequence Start

Power-up Sequence: (No power down sequence requirment)

FLTR

FLTR

FLTR

FLTR

FLTR

FLTR

FLTR

Max 10W Class 5

UX

UX

Max 10W Class 5

QSFPDD0_VCC/QSFPDD0_VCCT/QSFPDD0_VCCR

QSFPDD1_VCC/QSFPDD1_VCCT/QSFPDD1_VCCR

VCCH_GXRL_14C/15A/15C (0.4A)

VCCFUSEWR_GXFL_12A (<1mA)/VCCFUSECORE_GXFL_12A

VCCCLK_GXR (VCCN1V_IO_GXR) (0.92A)VCCHFUSE_GXR (0.15A)

VCCIO_SDM (1mA)VCCIO_HPS (0.19A)VCCBAT (0.012mA)

VCCIO_PIO_2B/2E/2F/2C1p2V_DDR4_CH01

VCCED_GXR_EN

1p8V_EN3.3V

VCCCLK_GXR_EN

VCCFUSEWR_SDM (1mA)

EN63A0QI

LT3042U81

EN6337QIU86

U88

U52

U46U47

U82

U75

EZ6301QI3-output

U892p5V

VCCE_PLL_GXRL (1.3mA)

VCCE_DTS_GXRL (1.0mA)

EP53F8QIU62

EP53F8QIU79

EP53F8QIU77

VCCADC (0.014A)VCCPLL_SDM/ VCCPLL_HPS

(5mA/1mA)

LTC7151SU69

EP53F8QIU63

LTM4657U67

LTM4657U66

EN63A0U73

LT7151SU71

EM2140LU70

5V

12V

VCCED_GXR (2.55A)

EM2120LU65

1p2V_DDR4_ CH01_EN

EP53F8QIU80

EN6347QI

TPS51200

TPS51200U84

U85

U75

A.13.3. Power Sequence

Intel Agilex FPGA requires proper power-up sequencing.

For more details on the power sequencing groups, refer to Table: Voltage Rails Groupin the Intel Agilex Power Management User Guide.

For more information on the connection guidelines, refer to the Intel Agilex DeviceFamily Pin Connection Guidelines.


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https://www.intel.com/content/www/us/en/programmable/documentation/xal1549865615514.html#fbx1550738573705

https://www.intel.com/content/www/us/en/programmable/documentation/zfo1550730074483.html

https://www.intel.com/content/www/us/en/programmable/documentation/zfo1550730074483.html


Figure 15. Power Sequence

12V_PCIe Slot (Grp2)12V_AUX (Grp1)

5V12V

1p2V_PRE1p8V_PRE

3p3V_STBY2p5V_PRE

FPGA_VCC/CCPVCCPLLDIG_SDMVCCH/VCCH_SDM

VCCL_HPSVCCPLLDIG_HPSVCC_HSSI_GXF

VCCERT_FGT_GXFVCCRT_GXR

VCC_HSSI_GXR

VCCED_GXRVCCPT

VCCPLL_SDMVCCPLL_HPS

VCCADCVCCH_GXR

VCCCLK_GXRVCCHFUSE_GXR

VCCFUSECORE_GXFVCCFUSEWR_GXFVCCH_FGT_GXF

VCCEHT_FHT_GXFVCCE_PLL_GXRVCCE_DTS_GXR

2p5VVCCIO_SDM/VCCIO_HPS

VCCBATVCCFUSEWR_SDM

IO_3p3VQSFPDD0_VCC/VCCT/VCCRQSFPDD1_VCC/VCCT/VCCR

1p2V_DDR4_CH011p2V_DDR4_CH02

0p6V_VREF_DDR4_CH010p6V_VREF_DDR4_CH020p6V_VTT_DDR4_CH010p6V_VTT_DDR4_CH02

VCCPIOVCCR_COREVCCA_PLL

Group3_PG

Group2_PG

Group1_PG

Power OkGroup 1 Power On

Group 2 Power On

Group 3 Power On

Power Sequence

Power_On

Power In

A.13.4. Power Measurement

Power measurements are provided for six FPGA power rails by reading the powervalue of various power regulators via their I2C connection.


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The following power rails are monitored:

1. VCC, VCCP (Power sensing by I2C on ED8401

2. 0.8V (Power sensing by I2C on EM2120L (U72)

3. 1.2V (Power sensing by I2C on EM2120L (U65)

4. 0.9V (Power sensing by I2C on EN2340L (U70)

5. 3.3V (Power sensing by I2C on EM2130H (U64)

A.14. Temperature Monitoring

Temperature monitoring of the Intel Agilex FPGA device is done by a pair ofMAX31730ATC+ temperature sense devices. The Intel Agilex I-Series device has 6 dietemperature diodes that can be monitored via external temperature sensing devices.The MAX31730ATC+ senses these diodes and convert the signals to digital form forthe Intel MAX 10 to read via a I2C bus. Additionally, the THERMn signal from theMAX31730ATC+ are brought to the Intel MAX 10 to allow it to immediately sense atemperature fault condition. An over temperature warning LED D9 (Red-colored) iscontrolled by the Intel MAX 10 device to indicate an over temperature warning.Temperature fault set points can be programmed into the temperature sensing device.

Figure 16. Board Temperature Measurement Circuit

DXP1

EU1

DXN1

DXP2DXN2

DXP3DXN3

SDASCL

VDD

1

23

45

67

1112

9

10

813

3p3V_STBY 3p3V_STBY

THERM

ADD

GNDGND_EP

MAX31730ATC+

C5700.1µF

I2C ADDR = 3A

TEMP2_THERMn 51

7501%

R476

10.0K

???

<IFN>

DXP1

EU2

DXN1

DXP2DXN2

DXP3DXN3

SDASCL

VDD

THERM

ADD

GNDGND_EP

MAX31730ATC+<IFN>

35 FPGA_Temp0Ap35 FPGA_Temp0An29 FPGA_Temp0Cp29 FPGA_Temp0Cn28 FPGA_Temp1p28 FPGA_Temp1n

R454

C584 100pf

C588 100pf

C563 100pf

R454

R458R458

R459R461

00

00

00

27, 32, 46, 50, 52 I2C2_SDA27, 32, 46, 50, 52 I2C2_SCL

23

45

67

1112

31 FPGA_Temp3p31 FPGA_Temp3n33 FPGA_Temp6p33 FPGA_Temp6n34 FPGA_Temp4p

R Tile14C

R Tile15C

R Tile15A 34 FPGA_Temp4n

R470

C569 100pf

C571 100pf

C568 100pf

R471

R472R473

R474R475

00

00

DNIDNI

27, 32, 46, 50, 52 I2C2_SDA27, 32, 46, 50, 52 I2C2_SCL

1

9

10

813

3p3V_STBY 3p3V_STBY

C5650.1µF

I2C ADDR = 38

TEMP1_THERMn 51

R460 0

10.0K

R453

A.15. Mechanical Requirements

The board is a PCIe standard-height (4.376 in tall), 10” long, dual-slot (1.37 in highabove the top surface of the PCB) form factor as defined by the PCIe CEM specificationRevision 3.0.


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Figure 17. Mechanical Requirements

2.35[0.093]

See Note 6Detail EScale 7.000

0.35[0.014]

5.25[0.2.7]

13.40[0.528]

Datum W11.65[0.459]

3.65[0.144]

R1.59[0.063]

0.64[0.025]

8.25[0.325]

(2 Places)

2.03 Max [0.080]Restricted ComponentHeight Both Sides

8.89 Typ[0.350]

0.64[0.025]

See Note 2 Full Radius

3.45[0.136]

See Note 7

Configuration

Single Slot

Dual Slot

Triple Slot

Primary SideHeight Restriction

14.47 Max[0.570]

34.80 Max[1.370]

55.12 Max[2.170]

Detail FScale 3000

RestrictedComponent

HeightSee Table

for Details

2.67 Max (0.105)RestrictedComponentHeight

Secondary (Solder)Side

1.57 Ref(0.062)

Primary(Component)

Side

Datum V

A.16. Board Thermal Requirements

A thermal solution is designed to cool up to 250W total power of the board. An activecooling design is used. The heatsink is designed to meet the height constraints of a 2-slot PCIe card form-factor as defined by the PCIe CEM specification revision 3.0.

Figure 18. Board Thermal Requirements

RestrictedComponent

HeightSee Table

for Details

2.67 Max (0.105)RestrictedComponentHeight

Secondary (Solder)Side

1.57 Ref(0.062)

Primary(Component)

Side

Datum V

Configuration

Single Slot

Dual Slot

Triple Slot

Primary SideHeight Restriction

14.47 Max[0.570]

34.80 Max[1.370]

55.12 Max[2.170]

Detail FScale 3000

The heatsink is securely mounted to the board using screws for easy assembly andremoval. A thermal material is also used between the FPGA and heatsink to ensuregood thermal contact.


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Figure 19. Air-Cooled Heatsink Assembly

A.17. Board Operating Conditions

The board should be designed to operate within the below conditions while keepingthe FPGA die temperature within its recommended operating TJ as defined in the IntelAgilex Device Data Sheet (usually 100°C).

Table 10. Board Operating Conditions

Operating Condition Range

Maximum power dissipation 250W

Maximum ambient temperature 0°C to 35°C

FPGA junction temperature 85°C

A.18. Over Temperature Warning LED

A red colored LED (D9) is connected to the Intel MAX 10 to indicate when an overtemperature fault condition has been detected. The Intel MAX 10 can turn on this LEDto indicate an over temperature warning.


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Intel® Agilex™ I-Series FPGA Development Kit User Guide

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Transcript of Intel® Agilex™ I-Series FPGA Development Kit User Guide