Integrating and Algorithmic ADCs Voltage-to-Time...

Texas A&M University 1 Spring, 2013

Fundamentals on ADCs: Dual-Slope and Algorithmic Jose Silva-Martinez

Integrating and Algorithmic

ADCs

Voltage-to-Time Converters

Thanks to Dr. Sebastian Hoyos for providing part of this

material



Single-Slope Integrating ADC

• Counter keeps counting until comparator output toggles.

• Simple, inherently monotonic, but very slow (2N*Tclk/sample).

Vi

Control

CI

fclk Counter Do

VX

VY



Single-Slope Integrating ADC

• Precision capacitor (C) and current source (I) are required.

• INL depends on the linearity of the ramp signal.

• Errors due to current-source output impedance and leakage current

• Comparator must handle large common-mode input.

• Comparator’s voltage dependent offset

• Finite Switch Resistance

VX

VY

t

t

t1

start stop

slope=I/C

.

, 11

i

clk

o

clk

oi

VTI

CD

T

tDt

C

IV



Dual-Slope Integrating ADC

• CT RC integrator replaces the current integrator.

• Input and reference voltages experience the same signal path.

• Comparator only detects zero-crossing (constant input CM).

• Clock injection and charge injection effects?

• Noise effects due to R, opamp and Vref?

• OPAMP specifications? Reset needed?

Vi

Control

fclk

Counter Do

VX

R

C

-VR



Dual-Slope Integrating ADC

• Exact values of R, C, and Tclk are not required.

• Comparator offset doesn’t matter.

• Op-amp offset introduces gain error and offset.

• Op-amp nonlinearity introduces INL error.

.V

V

t

t

N

ND

tRC

Vt

RC

VV

R

ino

Rinm

1

2

1

2

21

VX

t

t1 t2

1 2Vm

Vos

pulsesclockthecounttousedwindowtimetheist

V

Vtt

R

in

2

12



Subranging Dual-Slope ADC

• Much faster conversion speed.

• Two matched current sources and two comparators are required.

Vi

Control

Logic

SHA

Cnt 1

(8 bits) MSB’s

VX

C2

I

CS

I

256

C1

Vt

Cnt 2

(8 bits)LSB’s

fclk CarryIf Vx>Vt, then use

both current sources

Slope is ~256 times

faster

When Vx<Vt, then

use the small current

only, better

resolution



Subranging Dual-Slope ADC

• Precise Vt is not required if carry is propagated.

• Matching between the current sources is critical

→ if I1 = I, I2 = (1+δ)·I/256, then |δ| ≤ 0.5/256.

.

256

2

,1

C

I

dt

dV

C

I

dt

dV

X

X

VX

t

t1 t2

1 2

Vt

21 NWNDo



Subranging Multi-Slope ADC

Vi

Control

Logic

SHA

Cnt 2 4 Bits

VX

I

CS

I

256

Cnt 3 4 BitsI

16

Cnt 1 4 Bits

fclk

Ref: J.-G. Chern and A. A. Abidi, "An 11 bit, 50 kSample/s CMOS A/D converter cell

using a multislope integration technique," in Proceedings of IEEE Custom

Integrated Circuits Conference, 1989, pp. 6.2/1-6.2/4.



Subranging Multi-Slope ADC

• Single comparator detects zero-crossing.

• Comparator response time is greatly relaxed.

• Matching between the current sources is still critical.

.

256

3

,16

2

,1

C

I

dt

dV

C

I

dt

dV

C

I

dt

dV

X

X

X

VX

t

t1 t3

1 2 3

t232211 NWNWNDo

Signal

Tracking

phase



Successive

Approximation

ADC



Successive Approximation ADC

• Binary search algorithm → N*Tclk to complete N bits.

• Conversion speed is limited by comparator, DAC, and SAR

(successive approximation register)

• Fundamental assumption: DAC is more precise than ADC!

Vi

...DAC Do

VDAC

VX

...

b1

bN Shift

Register



Binary Search

• DAC output gradually approaches the input voltage.

• Comparator differential input gradually approaches zero.

• Notice that errors in each computation get accumulated!

VDAC

t

Vi

0

VFS

1 0 0 1 1 0

MSB LSBTclk

VFS

2

1012

11

i

N

iiFSi

i b;,b;Vb

v



02121

1 21

tt

CC

YXCC

QQV

CC

CV



Charge Redistribution ADC

• 4-bit binary-weighted capacitor array DAC.

• Capacitor array samples input when Φ1 is asserted (bottom-plate).

• Extremely power efficient (mainly passive)

• Medium resolution; speed is limited by switch velocity

SAR

Do

Φ1e

VX

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1

021 112480

tVC...QQ ittCC



02121

1 21

tt

CC

YXCC

QQV

CC

CV

VX



Charge Redistribution ADC

• 4-bit binary-weighted capacitor array DAC.

• Capacitor array samples input when Φ1 is asserted (bottom-plate).

• Extremely power efficient (mainly passive; Dynamic Power (?))

• Medium resolution; speed is limited by switch velocity

SAR

Do

Φ1e

VX

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1



Charge Redistribution (MSB)

SAR

Do

Φ1e

VX

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1

iR

j

j

j

jiRX

j

jXXR

j

ji VV

CCVCVVCVCVVCV

2

4

0

4

0

4

3

0

4

4

0



Comparison (MSB)

• If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR.

• If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground.

VX

t0

1

MSBSample

1

iR

X VV

V 2

:TEST MSB



Charge Redistribution (MSB-1)

iRiRXXXRi VVCCVCVVCVCVVCV 4

316161241216

SAR

Do

Φ1e

VX

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1



Comparison (MSB-1)

• If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR.

• If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground.

iRX VVV 4

3 :TEST MSB

VX

t0

1 0

MSBSample

1 2



Charge Redistribution (Other Bits)

Test completes when all four bits are determined w/ four charge

redistributions and comparisons.

SAR

Do

Φ1e

VX

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1



After Four Clock Cycles…

• Usually, half Tclk is allocated for charge redistribution and half for

comparison + digital logic.

• VX always converges to 0 (Vos if comparator has nonzero offset).

VX

t0

1 0 0 1

MSB LSBSample

1 2 3 4



Bottom-Plate Parasitics

• If Vos = 0, CP has no effect; otherwise, CP attenuates VX.

• AZ can be applied to the comparator to reduce offset.

SAR

Do

Φ1e

2C C C8C 4C

VR

Vi

Φ1 Φ1 Φ1 Φ1 Φ1

CP

Vos



Summary on SA ADC

• Power efficiency – only comparator consumes DC power.

• DAC nonlinearity limits the INL and DNL of the SA ADC

– N-bit precision requires N-bit matching from the cap array.

– Calibration can be performed to remove mismatch errors (Lee, JSSC 84 at the expenses of speed).

• If CP=0, comparator offset Vos introduces an input-referred offset Vos;

for nonzero CP, input-referred offset is larger than Vos (δ~CP/ΣCj).

• If Vos=0, CP has no effect (VX→0 at the end of search); otherwise,

charge sharing occurs at summing node (VX is attenuated).

• Binary search is sensitive to intermediate errors made during search

– DAC must settle into ½ LSB within the time allowed.

– Comparator offset must be constant (no hysteresis).

– Nonbinary search can be used (Kuttner, ISSCC, 2002).



References

1. R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp. 379-385, issue 6, 1975.

2. J. L. McCreary and P. R. Gray, JSSC, pp. 371-379, issue 6, 1975.

3. H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp. 813-819, issue 6, 1984.

4. M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp. 455-461, issue 4, 1993.

5. C. M. Hammerschmied and H. Qiuting, JSSC, pp. 1148-1157, issue 8, 1998.

6. S. Mortezapour and E. K. F. Lee, JSSC, pp. 642-646, issue 4, 2000.

7. G. Promitzer, JSSC, pp. 1138-1143, issue 7, 2001.

8. F. Kuttner, ISSCC, 2002, pp. 176-177.



Algorithmic ADC

Re-using the building

blocks



MSB=1 Vin-VFS/2 2(Vin-VFS/2)

MSB=0 Vin 2(Vin)

VFS

3VFS/4

VFS/2

VFS/4

0

VFS

3VFS/4

VFS/2

VFS/4

0

VFS

3VFS/4

Vin

VFS/2

VFS/4

0

VFS

3VFS/4

VFS/2

VFS/4

Vin

0

Algorithmic ADC: Basic Operations



Algorithmic (Cyclic) ADC

• Input is sampled first, then circulates in the loop for N clock cycles.

• Conversion takes N cycles with one bit resolved in each Tclk.

Vi

VFS/2

Vo

bj

1-b

DACVFS/2 0

SHA 2X

VX

Sample

mode



Modified Binary Search Algorithm

• If VX < VFS/2, then bj = 0, and Vo = 2*VX.

• If VX > VFS/2, then bj = 1, and Vo = 2*(VX-VFS/2).

Conversion

modeVi

VFS/2

Vo

bj

1-b

DACVFS/2 0

SHA 2X

VX



Modified Binary Search Algorithm

• Constant threshold (VFS/2) is used for each comparison.

• 2X gain is provisioned each time residue circulates around the loop.

VX

Vi

0

VFS

1 0 0 1 1 0MSB LSBTclk

VFS

2

X2 X2 X2 X2 X21 42 63 5



Chapter 13, Johns and Martin Book



Algorithmic ADC

• Block diagram of switched-capacitor algorithmic ADC

• Operates with two non-overlapping clock phases

• The converter reaches its final output in N cycles

• Capacitors C0, C1 and C2 are all nominally equal

• The C3 capacitor is used for sampling and canceling the amplifier offset

bc

Ssb

QQ

VQVQQ

21



• The input is sampled during clock phase Qs

• During clock phase Q1, the previous output is sampled onto capacitor C2.

The purpose of this is to multiply the output by a factor of two during the next clock phase

• The output bit from the previous cycle determines if Vref or ground is connected to C1

This process subtracts or adds Vref to the analog output of the amplifier, Vout

• During clock phase Q2, the new analog output Vout is available and the comparator produces

the next digital output bit

• This is repeated for N cycles to produce the final output word for N-bit resolution

Clock phase Q1 Clock phase Q2



• The input is sampled onto only one capacitor, reducing the input capacitance

• The amplifier operates in both clock phases and there are no wasted cycles where the amplifier is idle

• Switch configuration makes the amplifier insensitive to parasitics at the input

• The analog output of the first cycle can be expressed as

A

CCC

CCCVV

A

CCC

CV offsetinout

100

210

100

1]1[

• The output of cycle n can then be expressed as

A

CCCC

VCCVCDnVA

CCC

nV

offsetrefnout

out210

0

21110

20 ]1[

][

• Main source of error caused by capacitor mismatch and finite amplifier gain



Loop Transfer Function

• If VX < VFS/2, then bj = 0, and Vo = 2*VX.

• If VX > VFS/2, then bj = 1, and Vo = 2*(VX-VFS/2).

Vi

VFS/2

Vo

bj

1-b

DACVFS/2 0

SHA 2X

VX

Vi

Vo

VFS/20 VFS

VFS

bj=0 bj=1



Offset Errors

Ideal RA offset CMP offset

Vo = 2*(Vi - bj*VFS/2) → Vi = bj*VFS/2 + Vo/2

Vi

Vo

VFS/20 VFS

VFS

b=0 b=1

Vi

Vo

VFS/20 VFS

VFS

b=0 b=1

Vi

Vo

VFS/20 VFS

VFS

b=0 b=1Vos

Vos

Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS



The Multiplier DAC (MDAC)

• 2X gain + 3-level DAC + subtraction all integrated.

• A 3-level DAC is perfectly linear w/ fully-differential signals.

Vo

Vi

0-VR

VR

Decoder

Φ1 C1

Φ1 C2

Φ2

Φ1e

A

Φ2

-VR/4

VR/4



The 1.5-Bit Architecture

• 3 decision levels → ENOB = log23 = 1.58.

• Max tolerance on comparator offset is ±VR/4.

• An implementation of the Sweeny-Robertson-Tocher (SRT) division principle.

• The conversion accuracy solely relies on the loopgain error, i.e., the gain error and nonlinearity.

• A 3-level DAC is required.

Architecture can be generalized to n.5-b per conversion.

-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=2b=1

Vo

00 1001



Error Mechanisms of RA

• Capacitor mismatch

• Op-amp finite-gain error and nonlinearity

• Charge injection and clock feedthrough

• Finite circuit bandwidth

R

1

2i

1

21o V

C

C1bV

C

CCV

i

o

211

R2i21o VΔV

VA

CCC

VC1bVCCtV

Vo

Vi

0-VR

VR

Decoder

Φ1 C1

Φ1 C2

Φ2

Φ1e

A

Φ2

-VR/4

VR/4



RA Gain Error and Nonlinearity

Raw accuracy is usually limited to 10-12 bits w/o error correction.

-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=2b=1

Vo

0

Vi-VR VR

Do



1N

1N

2

110N2b2b2bb

2

1Do

1N

1N

2

110N3b3b3bb

3

2Do

1 bit and 1.5-b with Offset Tolerance1.5-b without Offset Tolerance



Effect of Offset



References

1. P. W. Li, et al., JSSC, vol. 19, pp. 828-836, issue 6, 1984.

2. C. Shih, et al., JSSC, vol. 21, pp. 544-554, issue 4, 1986.

3. H. Ohara, et al., JSSC, vol. 22, pp. 930-938, issue 6, 1987.

4. H. Onodera, et al., JSSC, vol. 23, pp. 152-158, issue 1, 1988.

5. B.-S. Song, et al., JSSC, vol. 23, pp. 1324-1333, issue 6, 1988.

6. B. Ginetti, et al., JSSC, vol. 27, pp. 957-964, issue 7, 1992.

7. S. H. Lewis, et al., JSSC, vol. 27, pp. 351-358, issue 3, 1992.

8. A. N. Karanicolas, et al., JSSC, vol. 28, pp. 1207-1215, issue 12, 1993.

9. H.-S. Lee, JSSC, vol. 29, pp. 509-515, issue 4, 1994.

10.S.-Y. Chin et al., JSSC, vol. 31, pp. 1201-1207, issue 8, 1996.

11.O. E. Erdogan, et al., JSSC, vol. 34, pp. 1812-1820, issue 12, 1999.



Algorithmic ADC

• Hardware-efficient, but relatively low conversion speed.

• Binary search algorithm.

• Loopgain (2X) requires the use of a residue amplifier, but greatly simplifies the DAC – 1-bit, inherently linear.

• Residue gets amplified each time it circulates the loop; the gain makes the later conversion steps (the LSB’s) insensitive to circuit noise and distortion.

• Conversion errors (residue error due to loopgain nonidealities and comparator offset) made in the earlier conversion cycles also get amplified again and again – overall accuracy is usually limited by the MSB resolving and residue generation step.

• Digital redundancy is often used to treat comparator/loop offsets.

• Trimming/calibration/ratio-independent techniques are often used to treat loopgain error.



Precision Techniques



Ratio-Independent Multiply-By-N Circuit

• Steps (1) and (2) are repeated for N times.

• C2 functions as a temporary charge storage.

Sampling Charge transfer C1-C2 exchanged

Vi Vo(1) Vo(2)

C2

A

C1

C2

A

C1

Vo(3)

C1

A

C2

(1) (2) (3)



RA Gain Trimming

• Precise gain-of-two is achieved by adjustment of the trim array.

• Finite-gain error of op-amp is also compensated (not nonlinearity).

C1/C2 = 2

nominallyVo

-

Vo+

Vi+

Vi-

Trim

array

VX+

VX-

A

C2C1

C2C1



Split-Array Trimming DAC

• Successive approximation is performed to find the correct gain setting.

• Coupling cap is slightly increased to ensure segment overlap.

2C1.2C

8C4C2CC8C4C2CC

2C1.2C

8C4C2CC8C4C2CC

VX+

VX-

Vi+

Vi-

8-bit gain

setting + sign



Digital Calibration

• RA gain is set lower than 2X, forcing missing codes but NOT

missing decision levels.

• Calibration is performed by measuring distance between S1 and S2;

(S2-S1) is later subtracted from Do (gain error and offset remain).

0Vi

-VR

VR

VR

MSB=0 MSB=1Vo

0

Vi-VR VR

Do

S1

S1

S2

S2

MSB=0

MSB=1



Digital Calibration

• C1 = C2

• C3 = βC1

• AZ SC amplifier

β1

V12b2V

CC

VC12bVCCV

Ri

32

R1i21o

Residue Amplifier

Vo

Vi

-VR

VR

Φ1 C2

Φ1 C1

Φ2

A

C3

Φ1e

Decoder

Φ1e

Φ2

Φ2



Capacitor Error-Averaging

,VVδV2V

C

VCVCCV RiRi

1

R2i21x1

Vx1VR Vx2

VR

A1

C1

C2

A1

C2

C1

Vi

A1

C1

C2

Φ1 Φ2 Φ3

Vx1

Φ1 Φ2

+Δ-Δ

Φ3

2Vi-VR

Vx2 .VVδV2V

C

VCVCCV RiRi

2

R1i21x2

,Cδ1C 12

Inherently linear capacitor error-averaging techniques for pipelined A/D conversion Yun Chiu;Circuits and Systems II:

Analog and Digital Signal Processing, IEEE Transactions on Volume 47, Issue 3, March 2000 Page(s):229 - 232

http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=82

http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=17931




,V2V2

VVV Ri

x2x1o

Φ2 Φ3

,CVCVCCV 4x23o43x1

,C2C 43

Vo

A2

C3

C4

-1

A2

C3

C4

-1Vx1 Vx2

Φ1 Φ2

Vo

Φ3

2Vi-VR




33 δ1C2C 44 δ1CC 11 δ1C C 22 δ1C C

Assume are zero mean Gaussian with

variance .

Find an expression for Vo and comment on the effectiveness of the capacitor

error-averaging technique.

4321 δδδδ and,,

2



References

1. P. W. Li, et al., JSSC, vol. 19, pp. 828-836, issue 6, 1984.

2. C. Shih, et al., JSSC, vol. 21, pp. 544-554, issue 4, 1986.

3. H. Ohara, et al., JSSC, vol. 22, pp. 930-938, issue 6, 1987.

4. H. Onodera, et al., JSSC, vol. 23, pp. 152-158, issue 1, 1988.

5. B.-S. Song, et al., JSSC, vol. 23, pp. 1324-1333, issue 6, 1988.

6. B. Ginetti, et al., JSSC, vol. 27, pp. 957-964, issue 7, 1992.

7. S. H. Lewis, et al., JSSC, vol. 27, pp. 351-358, issue 3, 1992.

8. A. N. Karanicolas, et al., JSSC, vol. 28, pp. 1207-1215, issue 12, 1993.

9. H.-S. Lee, JSSC, vol. 29, pp. 509-515, issue 4, 1994.

10.S.-Y. Chin et al., JSSC, vol. 31, pp. 1201-1207, issue 8, 1996.

11.O. E. Erdogan, et al., JSSC, vol. 34, pp. 1812-1820, issue 12, 1999.



Subranging ADC



Subranging ADC Architecture

Vi

VRT

VRB

Co

ars

e E

nco

de

r

Fine Encoder

MSB’s

LSB’s

Fine

Flash

Coarse

Flash



Subranging ADCPros

• Reduced complexity – 2*(2N/2-1) comparators

• Reduced Cin, area, and power consumption

• No residue amplifier required

Cons

• Typically 3 clock phases per conversion

– Sample

– Coarse comparison

– Fine comparison

• THA required (two-stage S/H if the front-end SHA only holds for one phase)

• Offset tolerance on fine comparators is at N-bit level.

• Offset tolerance on coarse comparators is also at N-bit level without digital redundancy.



Example Block Diagram

Do

Re

fere

nce

La

dd

er Coarse

ADC

En

co

de

r

Fine ADC

ViVRT

MSB’s

LSB’s

SHA

VRB

SHA

MUX

4 bits

5 bits

8 bits

Redundancy in fine ADC provided by over- and under-range comparators



Digital Redundancy of Fine ADC

Search range of the fine ADC is extended on both sides.

…

Vi

Fine Encoder + Error Correction

Extra

CMP’s

Extra

CMP’s

…

…

To

Coarse

CMP’s

… …

VR1

VR2



Two-Step ADC

Coarse

ADC

Fine

ADCVi

MSB’s

LSB’sSHA

VR

RA

2n1

D/A

SHA

VR

• Coarse-fine two-step subranging architecture

• Conversion residue is produced instead of switching reference taps.

• A DAC and a subtraction circuit are required.

• Residue gain can be provisioned to relax offset tolerance in fine ADC.



Timing Diagram

Sample

Vi

Coarse

ADC

DAC + RA

Fine ADC

• Four conversion steps can be pipelined.

• Usually DAC + RA settling takes the longest time.

• RA is often omitted (residue gain of one) to speed up conversion.



References

1. A. G. F. Dingwall et al., JSSC, vol. 20, pp. 1138-1143, issue 6, 1985.

2. J. Doernberg et al., JSSC, vol. 24, pp. 241-249, issue 2, 1989.

3. B.-S. Song et al., JSSC, vol. 25, pp. 1328-1338, issue 6, 1990.

4. T. Matsuura et al., CICC, 1990, pp. 6.4/1-6.4/4.

5. B. Razavi et al., JSSC, vol. 27, pp. 1667-1678, issue 12, 1992.

6. C. Mangelsdorf et al., ISSCC, 1993, pp. 64-65.

7. W. T. Colleran et al., JSSC, vol. 28, pp. 1187-1199, issue 12, 1993.

8. K. Kusumoto et al., JSSC, vol. 28, pp. 1200-1206, issue 12, 1993.

9. K. Sone et al., ISSCC, 1993, pp. 66 - 67, 264.

10.R. Jewett et al., ISSCC, 1997, pp. 138-139, 443.

11.B. P. Brandt et al., JSSC, vol. 34, pp. 1788-1795, issue 12, 1999.

12.H. Pan et al., JSSC, vol. 35, pp. 1769-1780, issue 12, 2000.

13.R. C. Taft et al., JSSC, vol. 36, pp. 331, issue 3, 2001.

14.H. van der Ploeg et al., JSSC, vol. 36, pp. 1859-1867, issue 12, 2001.

15.J. Mulder et al., JSSC, vol. 39, pp. 2116-2125, issue 12, 2004.

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