Integrated Process Technology Development for the sub … · Integrated Process Technology...

Integrated Process Technology Development

for the sub 7nm Era July 12, 2017

Alex Oscilowski President TEL Technology Center, America, LLC.

Alex Oscilowski/TTCA/July 12, 2017 2

imec (Belgium)

Taiwan

Korea

CEA-Leti (France) SUNY Poly/CNSE

(US)

TEL R&D base Consortium

TEL Technology Center Korea

TEL Technology Center, Taiwan

TEL Technology Center, America

TEL’s Global R&D Operations U.S.

IME (Singapore)

Tokyo Electron Yamanashi Ltd. Tokyo Electron Kyushu Ltd. Tokyo Electron Tohoku Ltd. Tokyo Electron Miyagi Ltd.

Japan


TEL R&D programs target key industry challenges

Disruptive changes for N7/N5… Patterning methods Device architectures Material schemes

… are addressed through unique capabilities @ TTCA in Albany World class engineering talent Leading-edge process access

Process/Metrology tools Competitive Benchmarking EUV

Integrated flows and e-test

N14 N10 N7 N5 N3.5

Patterning (Logic M1 pitch)

SADP, LEn SADP, LEn SAQP, LEn SAQP, LEn SAOP, LEn

ArF immersion ArF-i/EUV/DSA

Material: Channel, Contact plug, Interconnect metal Si/Si Si/Si Si/SiGe III-V/SiGe, Ge III-V/SiGe, Ge

W W, Co W, Co Co Co

Cu Cu Co, Cu Co, Ru Co, Ru

Device FinFET FinFET FinFET FinFET, Nanowire FinFET, Nanowire

64-56nm 48-40nm 38-28nm 28-20nm 20-14nm Technology Roadmap (by Mx pitch)


TTCA R&D strategy for <7nm Develop integrated process

technology modules… …through key

R&D partnerships…

…that deliver value to TEL and our customers


Integrated process technology modules for <7nm

Lithography/Patterning Deposition Etch Cleans

Process technology

Integrated process technology modules

Gate Contact Interconnect

Test structures Wafer processing/Access Test data (electrical/rel.) Metrology

Integration capability Lithography/Patterning Deposition Etch Cleans

Process technology


TTCA key R&D partnerships

SUNY Poly/CNSE Infrastructure Technology FEOL materials EUV extension Transistor data Novel devices Supplier partners

JDPs EUV patterning Transistor data Electrical/rel. data

Internal R&D

JDPs Advanced patterning Integrated modules Demos

IBM alliance

Module development Fast cycle feasibility Electrical/rel. data Test structures Wafer processing Competitive Benchmarking

Customer focused R&D


Advanced Patterning Examples


CD ~ 16.8nm; L(S) CDU ~ 0.7 (0.9) nm

Treatment 1 Treatment 2

Improved verticality

Standard Photoresist mandrel challenge

Mandrel hardening

SAQP using a photoresist mandrel

CDU, LER comparable to double hard mandrel SAQP

SiARC ODL

Si

PR PR

SiN

A-Si Oxide

SiARC ODL

Si

SiN

A-Si Oxide

SiARC ODL

Si

PR PR

SiN

A-Si Oxide

SiARC ODL

Si

SiN

A-Si Oxide

Si

SiN Oxide

Si

SiN Oxide

Si Si

SiN Oxide

LWR LER

Ave line 1.5 nm 1.2 nm Ave space 0.6 nm 1.3 nm

LWR/LER for 4 line and 4 space features

H. Kang, SMC-2017, Seoul


Fewer Steps for Same Results:

S. Thibaut et al, SPIE 2017

Demonstrated Spacer-on-Spacer for SAQP cost reduction


Self-Aligned Block for critical sub-40nm pitch Mx patterning

A. Raley et al, SPIE 2017


Advanced Gate Stack Examples


Engineered HfO2 – Anneal, etc.

Doped HfO2 – Zr, Al, Gd, La, Si, Sr and Y

Ferroelectricity in HfO2 origin is assumed attributed to the non centrosymmetric phase/orthorhombic phase

Currently Ferroelectric films are considered for Ferroelectric RAM (FeRAM) and as gate dielectrics for negative capacitance FETs (NCFETs)

Ferroelectricity in Hafnium Oxide based Thin Films

Source: J. Muller, SEMICON Europa 2012 T.S. Boscke et al. Appl. Phys. Lett. 2011


Negative Capacitance FET (NCFET) Electrical Performance

Steep sub-threshold slope demonstrated with ALD HZO thickness scaling Steep switching only occurs when device swept beyond coercive voltage. Dipole switching is essential for onset of NC effect.

LG = 2 μm LG = 1 μm

IDS-VGS Characteristics Scaling effect

Sharma et al, VLSI-2017, Kyoto


Advanced Contact Examples


ALD Ti vs PVD Ti: wrap around contact NMOS – Si:P

15

RFIN – RC PLOTS

0.2 0.4 0.6 0.8 1.00.0

1.0k

2.0k

3.0k

4.0k

Spacing (µm)

4Fin

-TLM

resi

stan

ce (Ω

) ALD Ti PVD Ti + extra HF ALD Ti + extra HF

ALD Ti ALD TI + Extra HF

ALD Ti

PVD Ti + extra HF

ALD Ti + extra HF

• ALD Ti wafers have lower Rc as compared to PVD Ti wafers • Conformal Processes for Contact Cleans and Metals enable

Wrap Around Contacts

IITC - 2017


Etch Challenges for EUV Based Contact Patterning Etch Innovation required to break these tradeoffs and to

help correct incoming variability

Quasi-ALE

Concept / Model

TEL DC Superposition with Q-ALE Technology enable Concurrent attainment of • High Selectivity • Symmetric Shrink • LER smoothing & and

wiggle mitigation

A. Metz, SPIE 2017


Advanced Interconnect Examples


Integrated area under XRD peaks

ALD TaN and TaAlN show better barrier performance than PVD TaN

Tc = 695ºC

Al/(Al+Ta)% = 0.33

Barrier layers investigated using in-situ ramp anneal synchrotron XRD (Advanced Photon Source at Argonne National Lab)

Physical Characterization: ALD barrier testing: In-situ Ramp Anneals

S. Consiglio et al. ECS Trans Fall (2015)


Lower RC and Via Resistance plus Superior TDDB with ALD-Ta(Al)N

compared to POR PVD-TaN

100

101

102

103

4 5 6

PVD-TaN 2nmALD-TaN 2nmALD-TaN 1nmALD-TaAlN 2nmALD-TaAlN 1nm

Tim

e to

50%

failu

re [

sec]

Electric field [MV/cm]

L/S=60nm/60nm peri.=30mm temp.=125degC

Y. Kikuchi et al., IITC/AMC 2016

Electrical Characterization: ALD barrier / CVD-Ru liner (2nm) / Cu-fill

3.5 4.0 4.5 5.0140

160

180

200

220PVD-TaN 2nmALD-TaN 2nmALD-TaN 1nmALD-TaAlN 2nmALD-TaAlN 1nm

Capacitance [pF]

Resis

tanc

e [k

ohm

]

L/S=60nm/60nm [kO

hm] TDDB

0 10 20 30.1

1

5102030507080909599

99.9

PVD-TaN 2nmALD-TaN 2nmALD-TaN 1nmALD-TaAlN 2nmALD-TaAlN 1nm

Via resistance [ohm]C

umul

ativ

e pr

obab

ility

[%

]

Via size=64nm

[kOhm]

Presenter / Division / Date (e.g., October 1, 2015) / Serial number 20

TTCA unique capabilities

Key R&D partnerships

TTCA

Joint development with all key customers, partners, suppliers on site

Extensive data sharing/learning

Patterning capability

World class team

Full flow tool/Process access

Rapid cycles of learning

Electrical/Reliability data

Leading edge litho ASML XT1950 ArFi- 193i ASML NXE3300B – EUV DSA

Film deposition, etch, and clean expertise

Structures for gates, contacts, interconnects, 3DI

Novel structures

Cross disciplinary/multi BU Breadth and depth Customer, supplier, consortia

experience

Leading edge patterning Ge and III-V epi, BDIII, PVD,

LSA/RTA Secure, TEL controlled full flow

24/7 process/tool access FEOL/MOL/BEOL/3DI All TEL/competitor tools Metrology/test

Competitive Benchmarking Available to all TEL businesses

Fast demo and feasibility data Local CIP/manufacturability data Hardware prototype enablement 24/7 operation TEL controlled IP protection

CD variation/defectivity Vt, Vfb, Ion/Ioff, Dit, EOT, Jg, Ig,

Rc, reliability for FEOL RC, Leakage, Rvia, Rline, SS,

DIBL, BTI Via chain yield and reliability for

BEOL

Up and down stream integration flexibility

Clustered processing, precursor delivery development


TEL and CNSE – a long history of success!

The SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s Albany NanoTech Campus

New Zero Energy Nanotechnology (ZEN) Building

2003 04 05 06 07 08 09 10 11 12 13 14 15

TTCA* Founded

NanoFab South Annex 13 TEL tools in a 4000+ sq ft cleanroom

NanoFab South 6 TEL tools in a 2000+ sq ft cleanroom

NanoFab North 40 TEL tools in a 4000+ sq ft cleanroom

First MOSCAP Data

First Full Flow Transistor Data

First Full Flow FinFET Data

NanoFab Central 18 TEL tools in a 4000+ sq ft cleanroom

New Fab NFX 50,000 sq ft cleanroom 300/450mm compatible 3 TEL tools installed

First III-V Data First DSA Data

DCS Enabled LFLFLE Solid Source Fin Doping 7nm SiN/SiO2 ALE

A WORLD-CLASS TEAM 90+ engineers 60+ service/support

INTEGRATED PROCESSING – TEL TOOLS Coater/Developer Tools FEOL/BEOL Tools Metrology/Test Tools

12 42 26

LITHOGRAPHY ACCESS ASML 1700i 1.2NA/50nm l/s ASML 1950i 1.35NA/35nm l/s ASML NXE3300B 0.33NA/18nm l/s

A B

C

D

E

E

A

B

C

D

12+ Years of LEADING-EDGE R&D CAPABILITY

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