Sparse Grids

IMOS-Based Inverter SimulationSam MaurusMatthias Ritter

1

NMOS vs. PMOSOnly dependant on geometry (gate placement)NMOSPMOSAn n+, or n-type semiconductor is a type of extrinsic semiconductor where the dopant atoms (donors) are capable of providing extra electrons to the host material. This creates an excess of negative n-type electron charge carriers.A p+ or p-type semiconductor is a type of extrinsic semiconductor where the dopant atoms (acceptors) are capable of taking away weakly-bonded electons from the semiconductor atoms. This creates more hole charge carriers, hence p+.

Why is it called NMOS? Is it just because the gate is on the RHS?2Sweep Source Voltage

Were sweeping the source voltage negative, so that means that the electrons will be pushed away from the source. At a certain point they will have enough energy to cause breakdown.

When we sweep the source voltage to -9, is it true that the electrons go from L->R until they have enough energy to cause breakdown?Is it impact-ionization?

3Sweep Drain Voltage

Here were sweeping the drain voltage positive, hence the positive charge carriers will be pushed away from the drain. At a certain level, the positive charge carriers will have enough energy to cause breakdown.

Same idea with positive charge carriers?4PMOS Gate-Modulated Breakdown

Here, as we modulate the gate voltage negative, positive charge carriers will accumulate underneath the gate. This will then form a conduction channel in the intrinsic material and hence gate-modulated breakdown will occur.

Here we create more positive charge carriers under the gate. How exactly does this cause the breakdown?5Breakdown PMOS

6Electron/Hole Density PMOS

Electron densityHole density

GateGateNMOS Gate-Modulated Breakdown

Samehere we create more negative charge carriers under the gatehow does this cause breakdown?8Breakdown NMOS

Also the same slope here.9Electron/Hole Density NMOSElectron densityHole density

GateGateElectron density in NMOS is higher?10Symmetry

Not perfectly symmetrical because:Biasing voltages arent the same.Electrons are different to holes, so the accumulation behaviour is different, they have different alphas/betas etc.11Inverter using Dessis Mixed-ModeVinVddVssVoutnmospmosVinVddVssVoutnmospmosVddVssVddVinVddVssVoutnmospmosVddVssVddVinVddVssVoutnmospmosVddVddVssVinBreakdown mechanismh12Inverter using Dessis Mixed-ModeVinVddVssVoutnmospmosDevice NMOS {File {...}Electrode {...}Physics {...}}

Device PMOS {File {...}Electrode {...}Physics {...}}

System{ NMOS a1 ( "source"=vss "drain"=out "gate"=in box=0 ) PMOS a2 ( "source"=out "drain"=vdd "gate"=in box=0 )}Output Voltage Inverter

Output Current Inverter

SummarySimulation of n-channel IMOS and p-channel IMOSBreakdown slope of ~0.13dec/mVSymmetric characteristics could in future be achieved by choosing appropriate work functions and biasing voltagesSymmetry is an enabling characteristic for creating basic logic gatesSimulation of IMOS-based inverterBasic inverter output characteristics seen from simulationsSentaurus editor provides flexibility to define arbitrary devicesNotes for the inverter curve: Amplification?16Thanks for listening