High-k Gate Dielectrics for Future CMOS Technology

1

High-k Gate Dielectrics for Future CMOS Technology

T.P. Ma Yale University, Center for Microelectronics, and Department of Electrical Engineering

New Haven, CT 06520-8284

Introduction High-k dielectrics are being actively pursued by the semiconductor industry to replace SiO2 as the gate dielectric for future generations of CMOS transistors. The 2004 ITRS [1] calls for gate dielectrics of less than 1 nm in equivalent oxide thickness (EOT) in the near future, with a very low gate leakage current. Most experts believe that only some sort of high-k gate dielectrics will be able to fulfill these requirements. The first group of high-k dielectrics that was proposed to replace SiO2 in recent years consisted of silicon nitride or silicon oxynitride [2,3]. The concept of using a high-k dielectric’s larger physical thickness to achieve the same EOT so as to reduce the tunneling leakage current was clearly presented in [2], and the search for the best high-k gate dielectric has continued ever since.

As a result of intense research efforts throughout the world, significant progress has been made, and there is a clear understanding of the important scientific as well as technological issues that need to be resolved before a viable high-k gate dielectric technology may be implemented in production.

Among these issues, the gate leakage problem seems to be mostly under control, as essentially all research groups have reported high-k gate leakage currents several orders of magnitude lower than their SiO2 counterparts of the same EOT’s. In contrast, other issues such as thermal stability, interfacial layer control, EOT control, reactions with polySi, and metal gate electrodes are still posing varying degrees of challenges that require more R&D to overcome, and this talk will give an overview of these challenges and the progress that has been made by various R&D groups. Because of the space limitation, this extended abstract cannot cover all of the research results that will be reviewed at the oral presentation; instead, only a few examples will be given here in this written document, and an emphasis will be given on the electrical characterization of high-k gate stacks because of the author’s expertise.

Materials and Processing Related Issues

Figure 1 shows a schematic cross-section of a MOSFET, where some key regions surrounding the high-k gate dielectric are highlighted. Of these regions, the high-k/substrate interface is of utmost importance, as it could significantly affect the over-all EOT of the gate stack, as well as the MOSFET’s electrical properties and

reliability. Since it was suggested that HfO2 and ZrO2 should be thermodynamically stable on Si [4], these two dielectrics quickly replaced TiO2 and Ta2O5 as the favorite high-k dielectrics among various R&D groups. Later on it was found that an interfacial layer inevitably formed between HfO2 or ZrO2 and Si substrate, despite the theoretical thermodynamic predictions. By then, the momentum was so high that the R&D community decided to lock in the HfO2 system (as it has a more stable interface with Si than ZrO2), and tried to use silicate or nitridation to stabilize the interface [7]. Similarly, the electrode/high-k interface is also very important, as the formation of an interfacial layer there normally lowers the effective dielectric constant, and could cause degraded electrical performance. In severe cases, the so-called Fermi-level pinning phenomenon could occur which adversely affects the threshold voltage [5]. Thus, proper engineering of the electrode/high-k interface is another important issue that is being actively pursued. In addition to the two interfaces described above, the bulk of the high-k film must be thermally stable. While no consensus has reached, many hold the opinion that the high-k gate dielectric must be either amorphous or single crystalline. Since the viability of single-crystalline high-k gate dielectric is still in the distant future, amorphous high-k gate dielectric has become the desired form, instead of the polycrystalline alternative. This is primarily based on the uniformity argument. Essentially, it is known that some properties, such as the dielectric constant and leakage current, are different between the crystalline regions and the grain boundaries, and therefore one would expect significant non-uniformities of EOT, threshold voltage, and gate leakage distributions in high-density integrated circuits containing numerous small-size devices, of which some devices may contain primarily crystalline high-k gate dielectrics while others are primarily around grain boundaries. Given the requirement for an amorphous high-k gate dielectric, the ranking of HfO2 as a desired high-k gate dielectric drops considerably, because it tends to crystallize at a relatively low process temperature (< 500 °C) [6]. In order to overcome this problem, one may add Al in HfO2 to form HfAlO [6], or use Hf oxynitride, Hf silicate, or nitrodized Hf silicate [7-9]. All of these approaches raise the crystallization temperature at the expense of reducing the dielectric constant. Figure 2 shows that the dielectric constant is reduced, and the bandgap is increased, with the addition of Al in HfO2, along with an increase in the crystallization

2

temperature.

Charge Trapping and Mobility Degradation It is now well known that the channel mobility in a high-k gated MOSFET is typically lower than its SiO2-gated counterpart. Since it is also well known that high-k gated MOSFET tends to have more oxide charge and interface traps than its SiO2-gated counterpart, it’s not surprising that many attribute the degraded channel mobility to Coulomb scattering by oxide charge and interface traps. Upon more careful examination, however, we found that part of the degradation may arise from the soft optical phonons in the high-k gate dielectric that act as “remote phonon scattering centers” and reduce the channel mobility, which is consistent with the theory proposed by Fischetti et al [10] In the course of our study of channel mobility to determine the possible scattering mechanisms, we found that the conventional methodology used to obtain the channel mobility in high-k gated MOSFET gives rise to very large errors, due to the trapping of carriers. Basically, the use of the conventional split C-V method to extract the carrier concentration in the conduction channel over estimates that concentration due to trapping of carriers, which results in an underestimate of the channel mobility [11]. This error could be as high as 30-50%, based on the typical interface trap density of high 1011/cm2 to low 1012/cm2 [11]. Therefore, we have introduced a modified split C-V method to more accurately extract the channel mobility [11], and this methodology is briefly depicted in Fig. 3.

It should be noted that trapping/detrapping time constants for some of the high-k gate dielectrics, including HfO2 and Al2O3, are much shorter than those for SiO2 [12], and therefore the DC measurement methodology commonly used for MOS devices with SiO2 gate dielectric will likely to miss these traps. A transient (pulsed) measurement methodology has been introduced to reveal more fully the traps in high-k gate dielectrics [12]. Using the more accurately determined mobility data, we have analyzed the possible scattering mechanisms that may have caused the degraded mobility in high-k gated MOSFETs, and concluded that Coulomb scattering indeed plays a critical role in reducing the channel mobility in high-k gated MOSFET, as expected. Figure 4 shows the strong correlation between the channel mobility and the density of interface traps which serve as Coulomb scattering centers. In addition, we have also gathered evidence that supports the “remote phonon scattering” theory proposed by Fischetti, et al [10]. Figure 5 shows that, compared to its SiO2 counterpart, the sample made of HfO2 as the gate dielectric suffers from additional source of phonon scattering, which can be attributed to the “remote soft optical phonons” in the

HfO2 layer

Inelastic Electron Tunneling Spectroscopy (IETS) This section introduces a novel technique to probe phonons, traps, microscopic bonding structures, and impurities in high-k gate dielectrics with a versatility and sensitivity that are not matched by other techniques. This technique is called the Inelastic Electron Tunneling Spectroscopy (IETS), which basically takes the 2nd derivative of the tunneling I-V characteristic of an ultra-thin MOS structure. The basic principle of the IETS technique is illustrated in Fig.6, where one can see that, without any inelastic interaction, the I-V characteristic is a smooth curve, and its 2nd derivative is zero. When the applied voltage causes the Fermi-level separation to be equal to the characteristic interaction energy of an inelastic energy loss event for the tunneling electron, then an additional conduction channel (due to inelastic tunneling) is established, causing the slop of the I-V characteristic to increase at that voltage, and a peak in its 2nd derivative plot, where the voltage location of the peak corresponds to the characteristic energy of the inelastic interaction, and the area under the peak is proportional to the strength of the interaction. In a typical MOS sample, there are more than one inelastic mode, as a wide variety of inelastic interactions may take place, including interactions with phonons, various bonding vibrations, bonding defects, and impurities. Therefore, Fig.7 is shown to represent the typical IETS spectrum that one expects to see. Figure 8 shows an actual IETS spectrum taken on an Al/HfO2/Si sample, where the features below 80 meV correspond to Si phonons and Hf-O phonons, and the features above 120 meV correspond to Hf-Si-O and Si-O phonons. The significance of this IETS spectrum is that it confirms the strong electron-phonon interactions involving optical phonons in HfO2, and that the Hf-O phonons have very similar energy range as Si phonons which we know are a source of scattering centers that degrade the channel mobility. Therefore, these data indirectly support Fischetti’s “remote phonon scattering model” [10]. Figure 8 also shows features corresponding to Hf-Si-O and Hf-O phonons. Since these phonons have much higher energies than kT at room temperature, they are not effective scattering centers at room temperature.

IETS can also be used to probe electronic traps in gate dielectrics. Figure 9 shows stress-induced trap features in a set of Al/HfO2/Si samples, where one can see the increase of trap density as the electrical stress time increases. We have found that it’s possible to reveal the spatial locations and energies of these traps by analyzing the IETS spectra in both voltage polarities [13], and the details of which will be presented at the conference.

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Acknowledgment

The author would like to thank former and current graduate students, Wenjuan Zhu, Whye-Kei Lye, Wei He, and Miaomiao Wang, for their contributions to this paper, and SRC and Sematech for their financial support.

References 1. The national technology roadmap for semiconductors

technology needs: Semiconductor Industry Associations (SIA), 2004

2. Kukesh Kahare, Xiewen Wang, and T.P. Ma ``Extending Gate Dielectric Scaling Limit by Use of Nitride or Oxynitride', 1995 International Symposium on VLSI Technology, Kyoto, Japan, June 6-8 (1995).

3. T. P. Ma, “Making Silicon Nitride Film a Viable Gate Dielectric”, IEEE Transactions on Electron Device, Vol.45, pp680-690, 1998

4. K.J. Hubbard, and D.G. Schlom, “ Thermodynamic stability of binary oxides in contact with silicon”, J. Mater. Res., Vol.11, No. 11, p2757-2776, 1996

5. C. Hobbs, L. Fonseca, V. Dhandapani, et al. “Fermi Level Pinning at the PolySi/Metal OixdeInterface". In Digest of IEEE VLSI Technology Symposium, pp. 8-9, Kyoto, 2003.

6. W. Zhu, T. Tamagawa, M.Gibson, T. Furukawa, and T.P. Ma, “Effect of Al inclusion in HfO2 on the physical and Electrical Properties of the Dielectrics”, IEEE Electron Device Letters, vol.23(11), 649 (2002).

7. Jack C. Lee, H. J. Cho, C. S. Kang, S. J. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. H. Choi, and M. Akbar, “High-K Dielectrics and MOSFET Characteristics, IEDM Tech. Dig., p.95 (2003).

8. M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hongo, S. Inumiya, M. Takayanagi and A. Nishiyama, “Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics”, IEDM Tech. Dig. p.849 (2002).

9. L. P. Rotondaro, M. R. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. T. Laaksonen, L. Tsung, M. Douglas,R. Kuan, M. J. Bevan, T. Grider, J. McPherson, L. Colombo, “Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric”, Symp. VLSI Tech., p.148 (2002).

10. M. Fischetti, D. Neumayer and E. Carttier, “ Effective electron mobility in Si inversion layers in MOS systems with a high-k insulator: the role of remote phonon scattering”, J. Appl. Phys., Vol.90, pp.4587, 2001

11. W.J. Zhu, J.P. Han, and T.P. Ma, “Accurate measurement of mobility in MOSFETs made with ultra-thin high-k dielectrics”, IEEE Trans. Electron Devices, Vol.ED-51, No.1, pp.98-105 (2004)

12. Kerber, E. Cartier, R. Degraeve, Ph. Roussel, L. Pantisano, T. Kauerauf, G. Groeseneken, H.E. Maes, U. Schwalke, “Charge Trapping and Dielectric Reliability of SiO2 / Al2O3 Gate Stacks with TiN Electrodes", IEEE Transaction on Electron Devices, Vol. 50, No. 5, pp. 1261 - 1269, (2003).

13. Miaomiao Wang, Wei He, and T.P. Ma, “Electron Tunneling Spectroscopy Study of Traps in High-k Gate Dielectrics: Determination of Physical Locations and Energy Levels of Traps”, to be published in Applied Physics Letters

Cross-sectional View of a MOSFET

Upper interfacial region

Bulk high -k film

Lower interfacial region

Gate electrode, poly

Substrate

Source Drain

Spacer

High -k Gate Dielectric Stack


Bulk high -k film



Substrate

Source Drain

Spacer

High -k Gate Dielectric Stack

Fig.1 Cross-sectional view of a MOSFET with high-k gate dielectric

• Al inclusion in HfO2 results in: higher crystallization temperaturlarger bandgap, but lower dielectric constant

-20 0 20 40 60 80 100

8

12

16

20

24

Die

lect

ric

Con

stan

t

Al Percentage (%)

400

600

800

1000

1200

1400HfAlO, ~80nm

Cry

stal

lizat

ion

Tem

pera

ture

(o C)

0 20 405.05.56.06.57.0

Al Percentage (%)

Ban

dgap

(eV

)

Fig.2 Crystallization temperature, bandgap, and dielectric constant as a function of Al concentration.

Mobility from Split CV-Interface trap correction for mobility extraction

0

50

100

150

200-0.5 0.0 0.5 1.0 1.5 2.0

(a)

MeasuredWith N

it

Idealw/o Nit

Vg1 Vg2

Vg (V)

Cgc

/Are

a (x

10-8F/

cm2 )

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

50

100

150

200

MeasuredWith Nit

Idealw/o N

it

(b)Q1 Q2

Cgc

/Are

a (x

10-8F/

cm2 )

Qinv

(µC/cm2)

-0.5 0.0 0.5 1.0 1.5 2.00

5

10

15

20

25

(d)(c)

I d (µA

)

Vg (V)0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

100

200

300

W/O Nit Correction

With Nit Correction

µ1

µ2

Qinv (µC/cm2)

Effe

ctiv

e M

obili

ty µ

eff (c

m2 /V

-s)

• Q1, not Q2, should be used for mobility extraction

)()(

ginvd

gdeff VQV

VIwL⋅=µ

Fig.3 Illustration of the modified split CV method for extracting the carrier concentration and channel mobility.

4

Scattering Rate due to PhononsThe difference between HfO2 and SiO2 is attributed to

soft optical phonons in HfO2

100 150 200 250 300 3500.000

0.001

0.002

0.003

0.004

0.005 0.85MV/cm 0.75MV/cm 0.65MV/cm

HfO2

difference betweenHfO2 and SiO2

SiO2

1/µ ph

(cm

2 /V-s

)

Temperature (K)

0.00

1.00

2.00

3.00

4.00 Scattering R

ate (x1013 s -1)

The scattering rate by the additional soft optical phonons in HfO2 is a weak function of temperature, which is consistent with theoretical calculation.

Mobility vs Interface Traps as Coulomb Scattering Centers

0.0 0.4 0.8 1.2 1.6 2.0 2.40

100

200

300

400

500

600SiO2

HfO2, 700oC

HfAlO, 700oC

HfO2, 600oC

HfAlO, 600oC

nMOSFET

Dit from Swing (x1013cm-2eV-1)

µ eff (

cm2 /V

-s) @

Eef

f=0.

1MV

/cm

• The effective mobility is highly correlated with the interface trap density, suggesting that Coulomb scattering is one major degradation mechanism for these high-k dielectrics

Inelastic Electron Tunneling SpectroscopyAn Inelastic Tunneling Event at E=eV = hν Causes

(a) I-V to increase slope;(b) a step in dI/dV;(c) a peak in d2I/dV2

I dI/dV d2I/dV2

eV=hνElastic

Inelastic

Elastic

ElasticInelastic

V

Various Inelastic Modes in the Barrier (Left)May Be Reflected in IETS (Bottom Right)

d2IdV2

IETS probes phonons, bonding vibrations, impurities, and Traps

IETS Signals for HfO2/Si

0 6 0 1 2 0 1 8 0

IETS

(A.U

.)

0 20 40 60 80

IETS

(A. U

.)

Voltage (mV)120 130 140 150 160

IETS

(A. U

.)

Voltage (mV)

Si-O-Hf Si-O

Si

Hf-O Hf-O

Lower energy peaks are Si and HfO2 phonons; Higher energy peaks are Si-O and SiO-Hf phonons

Si-OSi-O-Hf

Hf-OHf-O

Si

IETS Reveals Stress-Induced Traps

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30

After 800s 1.2V stress After 200s 1.2V stress Original

d2 I/dV2 (A

.U.)

Voltage (V)

IETS has high sensitivity in detecting traps.

Traps

Increasing Stress

Fig. 4 Channel mobility is strongly correlated to the interface trap density

Fig.5 Additional phonon scattering in HfO2-gated MOSFET is attributable to soft optical phonons in HfO2.

Fig.6 Inelastic interaction causes a slope increase of I-V, a step in dI/dV, and a peak in 2nd derivative, all occurring at the voltage corresponding to the characteristic energy.

Fig.7 Typical IETS spectrum (lower right curve) reveals the various inelastic modes depicted in the energy diagram on the left.

Fig. 8 IETS spectrum for Al/HfO2/Si sample, revealing Hf-O phonons between 15 and 75 meV, and Si-O, Si-Hf-O phonons at higher energies.

Fig. 9 IETS spectrum for Al/HfO2/Si sample, showing stress-induced trap features.

High-k Gate Dielectrics for Future CMOS Technology

T.P. MaT.P. MaYale UniversityYale University

Center for MicroelectronicsCenter for Microelectronics

Contributors:Wendy Zhu, Wei He, Mukesh Khare

MOS Transistor Gate Stack


Bulk high-k film



Substrate

Source Drain

Spacer

High-k Gate Dielectric Stack


Bulk high-k film


Gate electrode, Poly or Metal

Substrate

Source Drain

Spacer

High-k Gate Dielectric Stack

<± 4<± 4<± 4<± 4<± 4Thickness control EOT (% 3s)

3.01.01.01.01.0Gate Dielectric Leakage (pA/µm) LSTP

0.9-1.31.2-1.61.4-1.81.6-2.01.8-2.2Equivalent physical oxide thickness for low standby power Tox (nm)

3.01.00.70.30.1Gate dielectric leakage at 100°C (mA/µm) High-performance

0.5-0.80.6-1.10.7-1.20.8-1.30.9-1.4Equivalent physical oxide thickness for MPU/ASIC Tox (nm)

1825283237Physical Gate Length MPU/ASIC (nm)45 nm65 nm70 nm80 nm90 nmDRAM ½ Pitch

20102007200620052004Year of Production

ITRS Gate Stack Parameters Tunneling current increases exponentially with decreasing oxide thickness

Taur, IEEE Spectrum, July 1999

Metal/Oxide/Semiconductor (MOS) Transistor

• Speed Increases with Charge Carrying Capacity, Q.

Q = CVDielectric constant

where C = ε/d Oxide thickness

• To Increase C:– Decrease d– Increase ε (ε = k εo)

⇒High-k dielectrics

2 nm

εox: 3.9 εni: 7.8

)exp( 23

ox

ox

VT

bcJ ⋅⋅−∝ φ

Thermal Oxide Silicon Nitride

C = εT εni = 2.εox

Tphysical= 2.TEOT

4 nm Silicon Nitride has 2nm of Equivalent Oxide Thickness (EOT)

4 nm

First viable high-k gate dielectric – Si3N4

Silicon Nitride Shows Lower Gate Tunneling Currents

(Theoretical)

Yale Group, VLSI Technology Symposium, June 1995

0 1 2 3 4 5 610-1210-1110-1010-910-810-710-610-510-410-310-210-1100101102103104105106

10 A

20 A

30 A 40 A

: Oxide: Nitride

Nitride ε=6.5

Gat

e C

urre

nt D

ensi

ty(A

/cm

2 )

Dielectric Voltage (V)

Top View of JVD System

JVD Silicon Nitride on Si

-3 -2 -1 0 1 20.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

EOT = 4.5 nm

JVD Silicon Nitride

Ave. Nit = 6 X 1010 /cm2/eV

Cap

acit

ance

( X

100

0 pF

)

Gate Voltage ( V )

0.12 0.16 0.20 0.24-21

-20

-19

-18

-17

-16

-15

-14

-13

JVD Nitride

Physical Thickness: 8.9nmEquivalent Oxide Thickness: 5.0nm

log(

J/E2 )

1/E (cm/MV)

Fowler-Nordheim Plot of Current ThroughJVD Silicon Nitride

0 1 2 3 4 5 610 -9

10 -8

10 -7

10 -6

10 -5

10 -4

10 -3

10 -2

10 -1

10 0

10 1

10 2

39 A

40 A28 A

29 A

21 A

21 A

O xide

JVD n itrideGat

e C

urre

nt D

ensi

ty (A

/cm

2 )

D ie lectric V o ltage (V )

Comparison of Measured Gate Leakage Current

10-14

10-12

10-10

10-8

10-6

10-4

10-2

100

-1.5 -1 -0.5 0 0.5 1 1.5 2

Dra

in C

urre

nt [I

d, A

]

Gate Voltage [Vg, V]

Vd=50mV

Vd=1.5 V

S.S.=72.0 mV/dec.

W/L=10/0.15 µm

0

2

4

6

8

10

0 0.5 1 1.5 2

Dra

in C

urre

nt [I

d, m

A]

Drain Voltage [Vd, V]

Vg - Vth

0.5V

1.0V

1.5V

W/L=10/0.15 µm

0

20

40

60

80

100

120

-0.5 0 0.5 1 1.5 2 2.5

Gm

x T

ox (m

S x

Å )

Vg - Vt ( V )

W/L=10/0.15 µmTeq,ox=2.5 nm

Vd=0.1-1.7Vstep = 0.4V

Transistor Characteristcsof Sematech’s 0.15 um Technology with 2.0 nmJVD Silicon Nitride

Karamcheti et al., MRS Fall Meeting, Nov. 1999

Dielectric Constants of Some High-k Materials

Challenges of High-k Dielectrics

• EOT Control

• Thermal Stability

• Mobility & Threshold Voltage

• Trapping Induced Instability


• EOT Control




(After Garfunkel)


• EOT Control




HfO2 crystallizes between 300 and 400ºC

20 30 40 500

100

200

300

400

500

600 (110)

As-deposited

300oC

400oC

500oC

HfO2 100nm

Cou

nts (

A.U

.)

2 Theta (degree)

Thermal stability of high-k oxides

520 525 530 535 540 545 550 555 560

CC

D C

ount

s (a

.u.)

Energy Loss (ev)

p1

p2

as-deposited

520 525 530 535 540 545 550 555 560

CC

D C

ount

s (a

.u.)

Energy Loss (eV)

p2

annealed

p1 p

3

O K-edge

O K-edge

As-deposited film:• Low leakage and low EOT• Amorphous• Thin interfacial SiO2 layer• Broad ELNES

Annealed film (700 °C/N2):• Leaky, increased EOT • Partially crystallized• Thicker interfacial SiO2

layer• Narrower ELNES

Hf-aluminate films grown at RT by jet-vapor deposition (T.P.Ma, Yale U.) w. 6.8 at% Al


• EOT Control



• Trapping Induced Instability0

100

200

300

400

0 0.5 1 1.5

FG 400°CFG 500°CFG 600°CUniversal

Mob

ility

(cm

2 /V-s

)

Effective Field (MV/cm)

NMOS W/L = 150/10 µmEOT ~ 13 Å

0

100

200

300

400

500

600

0 0.5 1 1.5

UniversalNo annealFG anneal

Mob

ility

(cm

2 /V-s

)


Degradation of Channel Mobility in High-k Gated MOSFETs

SiON

HfO2

Common Errors in MeasuringHigh-k Gated MOSFET Mobility

• Trapping causes overestimation of carriers and thus underestimation of mobility

• High gate leakage current that results in underestimation of mobility at high fields

Mobility of HfO2-Gated MOSFET-Effect of Trapping

• Corrected curves are higher• Both show a peak, as predicted by scattering theory

0.0 0.5 1.0 1.5 2.0 2.5 3.00

50

100

150

200

250

Correction

PDA temperature 700oC 600oC

w/o Nit

With NitCorrection

nMOSFET,HfO2W/L=20µm/15µm100KHz

Mob

ility

(cm

2 /V-s

)

Qinv (µC/cm2)

Scattering mechanisms

(a) Coulomb scattering due to trapped charge in dielectrics(b) Coulomb scattering due to ionized impurities in depletion layer(d) Surface roughness scattering(e) Phonon scattering due to lattice vibration

Mobility of nMOSFET with various gate dielectrics

0.0 0.5 1.0 1.5 2.00

100

200

300

400

500

600

SiO2

HfO2, 700oC

HfAlO, 700oC

HfO2, 600oC

HfAlO, 600oC

Universal Mobility

nMOSFETAfter Nit correction

Mob

ility

(cm

2 /V-s

)

Effective Vertical Field (MV/cm)• The mobility of nMOSFET with SiO2 are much higher than the one of

HfO2 and HfAlO. • The mobility of nMOSFET with HfO2 or HfAlO annealed at 700oC are

higher than the one annealed at 600oC

The relation between mobility and interface trap density

0.0 0.4 0.8 1.2 1.6 2.0 2.40

100

200

300

400

500

600SiO2

HfO2, 700oCHfAlO, 700oCHfO2, 600oCHfAlO, 600oC

nMOSFET

Dit from Swing (x1013cm-2eV-1)

µ eff (

cm2 /V

-s) @

Eef

f=0.

1MV

/cm

• The higher the interface trap density, the lower the effective mobility, indicating that coulomb scattering is one major degradation mechanism of these high-k dielectrics

Remote Phonon Scattering

Temperature dependence of mobility

0.0 0.5 1.0 1.5 2.00

50100150200250300350400450500

UniversalMobility

Temperature: 120K 160K 200K 240K 280K 320K

HfO2with Correction

HfO2, w/o Correction

µ eff (c

m2 /V

-s)

Effective Vertial Field (MV/cm)

• Effective mobility for HfO2 is lower than universal mobility even after interface correction.

Extraction of mobility limited by phonon scattering

0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

1200nMOSFET, T=240K

µSR

µph

µeff

µcoul µ (c

m2 /V

-s)


srcouleffph µµµµ1111

−−=

• The mobility limited by phonon is extracted according to Matthiessen’s rule.

Temp. dependence of mobility limited by phonon scattering

100 150 200 250 300 3500

500

1000

1500

2000

2500nMOSFET Eeff=0.65MV/cm

Eeff=0.75MV/cm Eeff=0.85MV/cm

HfO2

SiO2

µ ph (c

m2 /V

-s)

Temperature (K)

• Mobility limited by phonon scattering for HfO2 sample is much lower than that for SiO2 sample

The difference between HfO2 and SiO2 is attributed to soft optical phonons in HfO2

100 150 200 250 300 3500.000

0.001

0.002

0.003

0.004

0.005 0.85MV/cm 0.75MV/cm 0.65MV/cm

HfO2

difference betweenHfO2 and SiO2

SiO2

1/µ ph

(cm

2 /V-s

)

Temperature (K)

0.00

1.00

2.00

3.00

4.00

Scattering Rate (x10

13 s -1)

• The scattering rate by the additional soft optical phonons in HfO2 sample is a weak function of temperature, which is consistent with theoretical calculation.

)]()1([1 ωτ

η−++∝ EuNN RRop

11

/ −= kTR e

N ωη

kTxwhere

eeN x

x

Rop

ωτ

η=

−+

=+∝11)12(1

kT<<ωη Top

∝τ1

kT>ωηopτ1

The scattering rate due to optical phonons:

is phonon occupation number

u(x) is the unit step function.

E<ωη

≈constant

Where

1) For

When

2) For


• EOT Control




Drain current instability

Instability is unacceptably large

0 1 2 30

50

100

150

200

up traces identical

VBase=-1.5V

Chemical oxide / 5 nm HfO2 / N2 PDA / poly gate

VD=0.1V

FET: 10x1 µm2

Dra

in C

urre

nt (µ

A)

Gate Voltage (V)

A. Kerber, E. Cartier et al., EDL 2003

……

Gate Voltage

timeVbase

Vt-instability in scaled SiO2/HfO2 stacks:Comparison to SiO2

All SiO2/HfO2 stacks studied show comparable instabilityInstability is much larger than for SiO2 control

0 1 2 3 4 5 610-3

10-2

10-1

100

HfO2

O3 clean, 3 nm, PDA: N2 600 OC for 1 min 4 nm, no PDASC1/SC2, 3 nm, 4 nm, 6 nm, no PDA

4.5nm SiO2Operating condition Detection limit

delta

VT (

V)

ESi_max (MV/cm)

Pulsed and ‘DC’ measurements

• Vt instability due to charging is underestimated by ‘DC’measurements

• Charging is leaking out during slow measurements• For application, pulsed result more relevant

0 2 4 60.01

0.1

1Operating condition

delta

VT (V

)

ESi_max (MV/cm)

Pulsed

DC

Stress and sensemeasurements

0.0 0.5 1.0 1.5 2.0 2.50

50

100

150

200

shifted up-trace

delta VT

O3 clean, 4 nm HfO2, PDA: O2 at 500 OC

Pulsed: open symbolsDC: (up-trace) solid symbols

FET: W=10 µm L=1 µm

VD=0.1V

Dra

in C

urre

nt (µ

A)

Gate Voltage (V)

Lifetime Extraction Charge Trapping vs TDDB

0.0 0.5 1.0 1.5 2.0 2.5-4

-2

0

2

4

6

8

10

B

A

VOP=0.63V

VOP=1.14V

polySi

nMOSFET∆Vth=50mV

TaSiN

10-year lifetime from trapping

log

(Str

ess

Tim

e (s

))

VSTRESS-Vth (V)

0 1 2 3 4 5 6100101102103104105106107108109

1010

B

A

nMOSFET

VOP=2.4VpolySi

VOP=2.9VTaSiN

10-year lifetime from TDDB

T 63(s

)

VSTRESS-Vth (V)

It is charge trapping rather than TDDB that limits device lifetime.

Trapping TDDB

Examples of Innovative Approaches

• Ultra Rapid Thermal Annealing• Inelastic Electron Tunneling

Spectroscopy (IETS)• MAD




Atmospheric Hot Gas Annealing Concept

-

Wafer Holdero Non-Contact (using high-speed He gas)o Controlled Scanningo Active, feedback cooling

Hot Gas Streamo ~700 – 1,100 deg Co Inert gas (He)o Large heat flux rangeo High stability / uniformity

Wafer

Inherent Advantages for Hot Gas RTP

• Heat transfer by gas conduction, not surface topography/material dependent

• Very Rapid Heating• Very Rapid Cool-down

Wafer Heating & Coolingat 5x107 W/m2 for 3msec

• - GaAs

0

200

400

600

800

1000

0 10 20 30 40

Time [msec]

Tem

pert

ure

[deg

rees

C]

Front surfaceBack surface




Inelastic Electron Tunneling SpectroscopyAn Inelastic Tunneling Event at E=eV = hν Causes

(a) I-V to increase slope;(b) a step in dI/dV;(c) a peak in d2I/dV2

I dI/dV d2I/dV2

eV=hνElastic

Inelastic

Elastic

ElasticInelastic

V

Various Inelastic Modes in the Barrier (Left)May Be Reflected in IETS (Bottom Right)

d2IdV2

IETS probes phonons, bonding vibrations, impurities, and Traps

Interactions Detectable by IETS

• Substrate Silicon Phonons• Gate Electrode Phonons• Dielectric Vibrations (Phonons)• Impurity Bonding Vibrations• Trap States

IETS Spectrum of SiO2/Si

∆G i [A

rbitr

ary

Uni

ts]

75x10 -3 6560555045403530Voltage Bias [Volts]

600550500450400350300250Wave Number [cm -1 ]

36.8

mV

43.6

mV

53.6

mV

59.4

mV

63.4

mV

Siliconphonons Si-O

modes

Siliconphonons

Si-Omodes

0.135 0.140 0.145 0.150 0.155 0.160 0.165 0.170

165

155

150

144

Voltage (V)0.01 0.02 0.03 0.04 0.05 0.06 0.07

63

59

53

44

21enter text here

IETS

(Arb

itrar

y U

nits

)

Voltage (V)

Si phonons SiO2 vibrations

21 mV: Si TA mode44 mV: Si LA mode53 mV: Si LO mode59 mV: Si TO mode

63 mV: Si-O LO1 mode (Rocking)144 mV: Si-O AS1 mode (Asymmetric Stretch)150 mV: Si-O AS2 mode (Asymmetric Stretch)155 mV: Si-O LO3 mode (Symmetrric Stretch)165 mV: P-O mode

Si phonons and SiO2 vibration modes

20 40 60 80 100 120 140 160 180 200

Si(T

O)

Si(L

O)

Si(T

A)

Si(L

A)

SiO

2

SiO

2

63

58

53

44

21enter text here

10 20 30 40 50 60 70

63

58

53

43

37

33

27

21

Voltage (mV)

W/O HF Vapor

With HF Vapor

Si-F mode

W/O HF Vapor

With HF Vapor

IETS

Voltage (mV)

IETS can detect structure changes caused by different processing conditions.(a) SiO2/Si without HF vapor pre oxidation cleaning (b) SiO2/Si with the HF vapor pre oxidation cleaning

(a)

(b)

(a)

(b)

0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16

-1.2x10-9

-8.0x10-10

-4.0x10-10

0.0

4.0x10-10

8.0x10-10

Si-O

( L

O1

)

780

mV

650

mV

Si-H

Si-F

Si-N

Si-H

Si-O

( L

O4

)

Si-O

( L

O3

)

Si (

TA

)

Dono

r

Si (

LA

)

Si (

LO

)Si

( T

O )

Si3N4

SiO2

IETS

(Arb

itrar

y U

nits

)

Voltage (V)

IETS of Thermal SiO2/Si and CVD Si3N4/Si

SiO2

Si3N4

IETS of Al/HfOIETS of Al/HfO22//SiSi

0 .0 5 0 .1 0 0 .1 5

A l-OH f-O -S i

6 7 .0 m vT e tr a g o n a l

7 1 .0 m vM o n o c lin ic

5 3 .3 m vM o n o c lin ic

3 3 .7 m vM o n o c lin ic 9 1 m v

M o n o c lin ic 1 0 2 m v

M o n o c lin ic

P o s iv ite B ia s (v o lt )

A l/H fO 2 /S i 6 0 0 o C a n n e a lin g in N 2

Theoretical (LDA and GGA) and experimental Theoretical (LDA and GGA) and experimental (Raman and IETS) of phonon modes in HfO(Raman and IETS) of phonon modes in HfO22

637(79mv)

640

627

667

Moniclinic Bg

572(71mv)

551

529

570

Monoclinic Bg

Tetragonal

Monoclinic Bg

Monoclinic Ag

Monoclinic Ag,Bg

Monoclinic Bu

Modes(cm-1)

536(66.4mv)

822(109mv)

725(91mv)

411(51mV)

270(33.7mv)

IETS

773672382,398256Raman

716640382,385252GGA

536821738423,424261LDA

------Xinyuan Zhao Xinyuan Zhao and David and David VanderbitVanderbit, Physical Review B,vol. 65, 2002, Physical Review B,vol. 65, 2002

Remote Phonon Scattering

IETS Signals for HfO2/Si

0 6 0 1 2 0 1 8 0

IETS

(A.U

.)

0 20 40 60 80

IETS

(A. U

.)

Voltage (mV)120 130 140 150 160

IETS

(A. U

.)

Voltage (mV)

Si-O-Hf Si-O

Si

Hf-O Hf-O

Lower energy peaks are Si and HfO2 phonons; Higher energy peaks are Si-O and SiO-Hf phonons

Si-OSi-O-Hf

Hf-OHf-O

Si

[M. Fischetti, et.al, J. Appl. Phys.,Vol.90, p4587, 2001]

))(( 0

0

oxsioxsi

oxox

εεεεεε

++−

∞∞∞

∞

Scattering strength ∝

e

p-Si Substrate

Source Drain

Gate

Dielectric

Mobility Reduction due to Soft Phonon Scattering

HfO2 gated MOSFET might have reduced mobility due to soft phonon scattering.

B)

A) Phonon energies close to kT at room temp.

Gate Dielectric SiO2 HfO2

Bond strength Strong Si-O bond Weak Hf-O bondOptical phonon energy ( meV) 138 34, 48, 70Rate of emission/absorption

phononLow High

Static permittivity εox0 /εo 3.9 22.0

Optical permittivity εox∞ /εo 2.5 5.03

Electron phonon couplingstrength

Low High

Mobility limited by remotephonon scattering

High Low

0 20 40 60 80 100 120 140 160 180 200-6.00E-008

-4.00E-008

-2.00E-008

0.00E+000

2.00E-008

4.00E-008

6.00E-008

8.00E-008

1.00E-007

1.20E-007

1.40E-007

~15A HfO2 600C N2 2min ~25A HfO2 600C RTA N2 2min

IETS

(A.U

.)

Voltage (mV)

IETS sensitive to process variationsfor Al/HfO2/Si structure (1)

Post-deposition annealing: Furnace vs. RTA

Furnace anneal

RTA


20 40 60 80 100 120 140 160 180

Voltage (V)

Si-O

Si-O-Hf

Hf-O

Hf-O

~10Å HfO2N2 600C 3mins + WV 600C 2mins

Thermal Oxide Reference

~15Å HfO2 N2 600C 3mins

Hf-O

20 40 60 80 100-2.00E-008

0.00E+000

2.00E-008

4.00E-008

6.00E-008

8.00E-008

1.00E-007

Si

Si

Hf-OHf-OHf-O

300C

400C

500C

600C

~25A HfO2 RTA in N2

IETS

(A. U

.)

Voltage (mV)

• Hf-O peaks stronger with increasing PDA temperature• Linked to more HfO2 crystallization at higher temperatures.


0 .0 2 0 .0 4 0 .0 6 0 .0 8 0 .1 0 0 .1 2 0 .1 4 0 .1 6

T rap o r d e fec t A ss is ted

T rap o r d e fec t A ss is ted T u n n e lin g

A l-OS i-O -H f

S i-OS i

O r ig in a l, F o rw a rd B ia s A fte r 2 0 s 2 .5 V S tre s s A fte r 2 0 0 s 2 .5 V S tre s s A fte r 6 0 0 s 2 .5 V S tre s s

IETS

(A.U

.)

V o ltag e (V )

Voltage Stress Induced EffectFeatures at 0.07V and 0.16V indicate trap assisted tunneling.

IncreasingStress

-0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16

Trap Assisted TunnelingSi-OSi-O-HfSi

Original, Reverse Bias After 20s 2.5 V Stress After 200s 2.5 V Stress After 600s 2.5 V Stress

Voltage (V)

IETS

(A.U

.)

Voltage Stress Induced Effect(Reverse Bias)

IncreasingStress

Trap Related Effect from IETSI

V

V

∆Gi

Trap Assisted Tunneling

Background I-V

Charge Trapping

Charge Trapping

Trap Assisted Tunneling

IETS Reveals Stress-Induced Traps

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30

After 800s 1.2V stress After 200s 1.2V stress Original

d2 I/dV2 (A

.U.)

Voltage (V)

IETS has high sensitivity in detecting traps.

Traps

Increasing Stress

Strong Trap Assisted Tunneling Effect Revealed by IETS

Forward-bias trap features are stronger than reverse-bias ones, due to asymmetry of the barrier.

-0.4 -0.2 0.0 0.2 0.4 0.6

IETS

(A. U

.)

Voltage (V)

Trap

Trap

HfO2/SiStressed at 1.6V800s

Determining Trap Energy and its Physical Locationfrom Forward and Reverse IETS

Assume non-uniform dielectric constant: ε=ε(x).Vt = Vf Vr / (Vf+Vr) dt = d0Vf / (Vf+Vr)

where d0 = ∫0

0

xdx/ε(x) dt = ∫

xt

0 dx/ε(x),

----By Wei,He

xt is the physical location of the trap (assume total physical thickness is x0).eVt is the trap energy above the Fermi level (at zero bias).Vf is the forward bias voltage required for the Fermi level to reach the trap. Vr is the reverse bias voltage required for the Fermi level to reach the trap.

**

*

Vf

Vr

xt

Vt

x0

Trap Energy and its Physical Location for a Particular Trap

-0.4 -0.2 0.0 0.2 0.4 0.6

IETS

(A. U

.)

Voltage (V)

Trap

Trap

HfO2/SiStressed at 1.6V800s Vf = 0.58 V

Vb = 0.32 V

V0 = 0.21 Vd = 0.36

The EOT of the dielectric is ~2.5 nm.

The trap is located ~ 0.9 nm from the dielectric/Si interface

Conclusion

Extensive R&D Efforts for High-k Gate Dielectrics Are Needed to Realize• EOT << 1 nm• Low Gate Leakage Current• Good Thermal Stability• Desired VT for Both Channels• High Drive Current andTransconducctance

• Good Reliability

Worldwide IC Sales (C. Osburn)

(a) (b)

Fig. 12 Drain current characteristics of transistor with <2nm (EOT) of RTCVD silicon nitride asgate dielectric: (a) NMOSFET, (b) OMOSFET [12].

N-Channel and P-Channel Transistors with < 2nm (EOT) of RTCVD Silicon Nitride as Gate Dielectric

Song, et al., IEDM Technical Digest, Dec. 1998

(Adapted from E. Garfunkel) Mobility measurement

∫∞−

=Vg

gggcinv dVVCQ )(

)V-(VCQ Tgoxinv =Conventional

Split CV:

• Cgc is not step function of Vg at VT => need split CV

)()(

ginvd

gdeff VQV

VIwL

⋅=µ

Effective mobility:

Inversion charge density:

Standard split CV method is inadequate for high-k dielectrics with high Nit

oxtrapinvg CdQdQdV /)( +−=

Problem 1. Nit can respond to ac signal

itDinvox

itinvoxgc CCCC

CCCC+++

+=

)(

Problem 2. Nit can respond to dc signal

Solution: Higher frequency for split CV

Solution ?

Vg

Eit

Cox

CD

Cinv

CitEc

EF

Ev

Gate substrateDielectric

Nit responseto DC signal

Nit responseto ac signal

Ideal

Cgc

Vg

Mobility from Split CV-Interface trap correction for mobility extraction

0

50

100

150

200-0.5 0.0 0.5 1.0 1.5 2.0

(a)

MeasuredWith Nit

Idealw/o Nit

Vg1 Vg2

Vg (V)

Cgc

/Are

a (x

10-8F/

cm2 )

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

50

100

150

200

MeasuredWith Nit

Idealw/o Nit

(b)Q1 Q2

Cgc

/Are

a (x

10-8F/

cm2 )

Qinv (µC/cm2)

-0.5 0.0 0.5 1.0 1.5 2.00

5

10

15

20

25

(d)(c)

I d (µA

)

Vg (V)0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

100

200

300

W/O Nit Correction

With Nit Correctionµ1

µ2

Qinv (µC/cm2)

Effe

ctiv

e M

obili

ty µ

eff (c

m2 /V

-s)

• Q1, not Q2, should be used for mobility extraction

)()(

ginvd

gdeff VQV

VIwL

⋅=µ

s

invinv d

dQCψ

=

Mobility from Split CV (cont’d)-Interface trap correction for mobility measurement

Dinvox

invoxgc CCC

CCC++

=

At high frequencies, gate-channel capacitance

where

is the same with or w/o interface traps for the same Qinv

At same Cgc, Q1 extracted from ideal Cgc and Q2 from measured Cgc contain the same amount of mobile inversion charge,while Q2 contains extra interface trapped charge

Vg

Eit

Cox

CD

Cinv

Ec

EF

Ev

Gate substrateDielectric

Mobility of HfO2-Gated MOSFET-Effect of Interface Traps

• Corrected curves are higher• Both show a peak, as predicted by scattering theory

0.0 0.5 1.0 1.5 2.0 2.5 3.00

50

100

150

200

250

Correction

PDA temperature 700oC 600oC

w/o Nit

With NitCorrection

nMOSFET,HfO2W/L=20µm/15µm100KHz

Mob

ility

(cm

2 /V-s

)

Qinv (µC/cm2)

Difference between interface traps causes mobility “underestimation” and mobility “degradation”

e

p-Si Substrate

Source Drain

Gate

Dielectric 1

2

• 1: Charge trapping causes carrier loss and mobility underestimation

• 2: Trapped charge causes Coulomb scattering and mobility degradation

Hall Mobility vsEffective Mobility from split CV

0.1 0.2 0.3 0.4 0.5 0.6 0.710

100

1000

nMOSFET, poly gate

µeff-correction

µeff-No-correction

µHallµeff

µHall

HfO2

SiO2

Mob

ility

(cm

2 /V-s

)

Qinv (x10-6C/cm2)

Normalized Inversion Charge Density

0.0 0.2 0.4 0.6 0.80.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

split CVwithcorrection

Halleffect

split CVw/o correction

HfO2

Qin

v/Cin

v (V

)

Vg-VT (V)

IncreasingStress

Electrical Stress Alters the Si-O Modes But Leaves the Si Phonons Unchanged

Si-O modes

Si phonons

IETS can detect changes caused by elctrical stressIETS reveals changes in SiO2/Si interface after AC stress. Possible explanation is that AC stress breaks weak bonds and cause positive charges at the interface. The positive chargeswill modify the bonding structure for SiO2 near the interface.

A:Initial; B-D:After 103,104,105 sec +0.5V 1kHz square wave stress;E:After 103 sec +2V 1us 1kHz pulses;F: After 103 sec -2V 1us 1kHz pulses.

IncreasingAC Stress

Bias Polarity Dependence

Electrons have higher

probability to interact witha vibration

located near the positively

biased electrode.

20 40 60 80 100 120 140 160 180-1.00E-009

-8.00E-010

-6.00E-010

-4.00E-010

-2.00E-010

0.00E+000

2.00E-010

4.00E-010

6.00E-010

8.00E-010

S i S iS i S i-OSi-O

Si-O -Hf

H f-O

Hf-O

Hf-O

Si

S i

Reverse B ias

Forward B ias

IETS

(A.U

.)

Vo ltage (m V)

Bias Polarity Dependence of IETS for Al/HfO2/Si

• Results suggest significantly different microstructures near Al-HfO2 interface and Si-HfO2 interface.

• HfO2/Si interface is more SiO2-like. • HfO2/Al interface is more HfO2-like.

~15A JVD HfO2 on Si, annealed in N2 600C 3min

High-k Gate Dielectrics for Future CMOS Technology

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Transcript of High-k Gate Dielectrics for Future CMOS Technology