The Process and Stress-Induced Variability Issues of Trigate CMOS Devices Steve S. Chung

Department o/Electronic Engineering, National Chiao Tung University, Taiwan email: schung@cc.nctu.edu.tw Abstract- Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the hot carrier stress induce the V1h variations. This paper will address the importance of these effects and the experimental demonstration of the process- and trap-induced fluctuations. The boron clustering, sidewall roughness, and the electrical stress effects can all be justified by the theory and the method. This method provides us a valuable tool for the understanding of the process and stress induced variability in 3D devices (e.g., FinFET).

Keywords: Trigate CMOS, Variability, Variation, Reliability

1. Introduction One of the most significant issues in the CMOS scaling is

the variability induced by the process and device design [1-2], especially the random dopant fluctuation (RDF) [1], the major source of Vlh variation. To solve RDF, several approaches by using different transistor architecture or process [3-5] have been proposed to remedy the problem. Among them, FinFET or FDSOI [4] has been evolved as a better choice for 20nm and beyond. A similar effect called random trap fluctuation (RTF) caused by the HC-stress will also lead to Vth variations. [6] In this paper, both the process and stress-induced Vlh variation will be demonstrated by the theory and experimental verifications in trigate devices.

2. The Theoretical Basis Fig. 1 illustrates a device with existing random dopant and

oxide traps especially near the drain region. Fig. 2 shows the cross-sectional view of the experimental trigate device. The profiling of random dopant distribution along the channel of the device can be obtained experimentally by combining a theoretical model [7-8]. By varying the source-to-drain bias in Fig. 3, the peak position of the channel barrier can be calculated. To achieve this purpose, the channel barrier can be considered as a second order curve, in which the peak position can be detennined from the experimental measured DIBL and lateral length, LetI', based on the fonnulae in Eqs. (1) and (2), Fig. 4. The discrete dopant can be modeled as a delta function derived in Table 1. The local crVth(x) was first calculated and then the dopants distribution can be determined. Eq. (5).

3. Process-Induced Random Dopant Variation The random fluctuation can be gauged by the Pelgrom plot [9]

or Takeuchi plot [10]. The comparison shown in Fig. 5 is the

Pelgrom plot, in which the Vlh variation is compared for the

control n- and p-MOSFETs. The A VI of nMOSFET is larger than

that of pMOSFET. To explain the larger value of nMOS, a boron

clustering model was reported in [11]. In general, the boron atoms

with high concentration are clustered in silicon. Some boron atoms

of channel dopants are grouped together with weak bonding and

act as one boron cluster which then leads to the larger fluctuation

of dopants in the channel.

To prove the existence of the boron clustering, experimental

result was demonstrated in Fig. 6, where the large fluctuation in

nMOSFETs was observed. Also, very high dopant distributions

are found near the drain side that are attributed to the diffused

atoms of drain impurities into the channel. Fig. 7 shows the

comparison of the dopant distribution in conventional and trigate

978-1-4673-2523-3/13/$31.00 ©20 13 IEEE

nMOSFETs. It was found that the experimental results of trigate

device shows much less fluctuation, which should be from the

suppression of the dopant fluctuation by the larger electrical field

as a result of a better chancel controllability in the trigate.To study

the sidewall roughness effect in trigate devices, the trigate devices

with 3 different fin heights are evaluated. Fig. 8 shows the

structure and the profiling results for both n- and p-trigate. It

reveals that larger fin height device shows a much larger dopant

fluctuation, as a result of the sidewall roughness effect.

4. Stress-Induced Variation in Trigate MOSFETs From Pelgrom plot [9], bulk trigate devices exhibit better

Vlh variation because a good control of the short channel effect which led to the suppressed RDF.(Fig. 3) But, after the stress, Vllt variation of trigate devices was much worse than that of control due to RTF, resulting in an increase of Vllt variation. (Fig. 9) The amount of increased traps can be extracted by crVlh after the stress in Table 2.

To characterize the oxide trap spatial distribution, random trap profiling was perfonned after hot carrier(HC) stressed the planar and trigate nMOS devices. In planar devices, it was found that the local Vlh variation fluctuated more heavily near drain edge after the stress, showing where the traps were generated due to a high electric field.(Fig.lO) But, for trigate devices after HC stress (Fig.ll), not only the local Vlh variation was observed near the drain edge but also on the sidewall, meaning that the sidewall creates another effect. We suspect that the sidewall corner effect induced a high electric field and generated the traps. As a result, in trigate nMOS devices, the trap density was much higher than that of the planar after the HC stress. (Fig.l2) To examine the sidewall effects, pMOS devices with three different sidewall heights, under NBTI stress, have been compared, Fig. 13, in which the higher the sidewall is, the more device degradation becomes as a result of the sidewall roughness and a high electric field on the sidewall corner. The results shown in Fig. 14 confirm these reasonings.

In summary, a random trap profiling technique has been implemented successfully to identify the oxide trap distribution in a small dimension bulk trigate device. Trigate devices show better RDF variability but poorer reliability than the planar devices. From the reliability aspects, we conclude that NBTl stress dominates the degradation of trigate devices due to the sidewall roughness effect. (Fig. 14) Through the above experiments, it provides us a more specific evidence to con finn the traps which results from the electrical stress could enhance Vlh variation, i.e. cr(Vlh)2 = cr(dopant)2 + cr(Nilt These results provide us a direction on a good control of the reliability for future 3D trigate CMOS devices.

Acknowledgments This work was support in part by the National Science

under contract NSC99-222i-E009-i92 and NSCiOO-222i-E009-0i6-MY3, the

MoE ATU program .

References: [I] F. Yang et aI., VLSi, 208,(2007). [2] A. Asenov, VLSI, 86(2007). [3] T.

Tsunomura et aI., VLSi, 110(2009). [4] A. V -Y Thean et aI., iEDM, 881 (2006).

[5] S. Kamiyama et aI., IEDM, 431 (2009). [6] E. R. Hsieh et aI., IRPS, 941

(20 II). [7] E. R. Hsieh et aI. , VLSI, 184 (20 II). [8] H. M. Tsai et aI., VLSI,

194 (2012). [9] M. 1. M. Pelgrom et aI., iEEE JSSC, 1433 (1989). [10] K.

Takeuchi et aI., IEDM, 467 (1997). [II] K. Takeuchi et aI., IEDM, 467(2007).

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