Towards Electronics at 1000 °C

D. Maier(l),*, M. Alomari(l), N. Grandjean(2), J-F Carlin(2),

M-A Diforte-Poisson(3),C. Dua(3), S.L. Delage(3), E. Kohn(l)

(1) Institute of Electron Devices and Circuits, University of Ulm, 89069 Ulm, Germany (2)Ecole polytechnique fedirale de Lausanne, 1015 Lausanne, Switzerland

(3)1l1lV Lab, 91461 Marcoussis, France * E-mail: david.maiet@uni-ulm.de, Phone: +49-731-50-26187

High temperature electronics is up to now essentially limited to approx. 500°C by the high temperature properties of the active semiconductor elements mostly based on SiC [1]. Sensing at even higher temperature relies therefore mostly on non-semiconductor components essentially limiting the systems complexities. However in recent years III-Nitride heterostructures, namely lattice matched InAIN/GaN heterostructures, have become an alternative. In an initial proof-of-concept experiment in 2006 [2] 1000 °C operation could be demonstrated for a short period of time.

Triggered by this experiment, commonly used HEMT processing steps have been refmed to stabilize the high temperature device performance. This has resulted in 1 MHz large-signal operation for 50 hrs at 900°C [3]. It was felt, that fmal failure was caused by metal electromigration and cracks formed in the passivation layer. In the first generation of experiments Au had been used as conductive overlayer material, limiting operation to approx. 700°C. In the second generation technology the Au overlayer was replaced by Cu, allowing to extend testing to 900°C, however already approaching its melting temperature of 1084 °C. Refining the contact technologies further has now resulted in a first large signal 1 MHz operation at 1000 °C (in vacuum) for 25 hrs. No significant change in pinch-off voltage could be observed, indicating no change in the heterostructure polarization properties and thus its structural integrity. It appears therefore that this heterostructure possesses indeed ceramic-like stability and device properties are essentially linked to the contact technologies, overlay metallization materials and passivation dielectrics used.

The devices were fabricated on MOCVD grown InAIN/GaN on sapphire with a barrier layer thickness of 12 nm . Device insulation was achieved by dry mesa etching in Argon plasma. Ohmic contact stack is Til Al/NilPt annealed at 800°C; the gate metal used was Mo; the device passivation was 30 nm ShN4 deposited by PECVD at 340°C. The devices have 2 parallel gate fingers without field-plate and air-bridge. Device geometry is LG = 0.25 /lm and WG' = 2 x 50 /lm. The initial device pinch-off voltage is Vp = -2.1 V. The maximum drain current of the semi-enhancement mode device was 400 mAlmm at VGS = +2 V, the maximum transconductance was 150 mS/mm.

In the experiment the temperature has been ramped up to 1000 °C within 48 hrs. Precision in temperature reading at 1000 °C is thought to be Ll T = 30°C. The devices were tested in vacuum in 1 MHz large-signal class-A operation between Vg = +1 V and Vg = -2 V. The drain-source voltage was VDS = 10 V, the external drain load resistor was RJ = 620 n. During testing, the mean DC output current (Mean ID) has been recorded every 60 sec (see fig 1).

During the ramping period the channel sheet resistance increased from 700 n (RT) to 3.9 kn (1000 0C). The open channel output current decreased from 400 mA/mm to 200 mA/mm, dominated by the change in 2DEG mobility. The pinch-off voltage remained essentially unchanged at Vp = -2.1 V up to 1000 °C. During 1000 °C operation, buffer layer and gate leakage became noticeable. Fig. 2 shows the development of the mean output current (Mean ID) with testing time, where the steady increase could be correlated with increase in buffer and gate leakage. This may be illustrated with the inserts of DC output characteristics measured initially at 1000 °C and after 1 st hr, 3rd hr and 25 hrs respectively when the test was terminated (inserts fIg.2). Despite of the degradation in electrical performance, no major effect of metal accumulation or depletion due to electromigration could be noticed (see fig 3).

To our knowledge his test represents the first semiconductor large signal operation of any semiconductor transistor at a temperature of 1000 0c. Certainly life time is still limited and especially contact technologies need further refmement. Nevertheless the experiment may serve as feasibility study towards the development of electronics at very high temperatures.

This work was in part supported by the European Union Project MORGAN (FP7 contract 214610).

[1] Neudeck, P.G.; Spry, OJ.; Liang-Yu Chen; Beheim, G.M.; Okojie, RS.; Chang, C.W.; Meredith, RD.; Ferrier, T.L.; Evans, LJ.; Krasowski, MJ.; Prokop, N.F.; , "Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500°C," Electron Device Letters, IEEE, vo1.29, no.5, pp.456-459, May 2008. doi: 1O.l109ILED.2008.919787

[2] Medjdoub, F.; Carlin, J.-F.; Gonschorek, M.; Feltin, E.; Py, M.A.; Ducatteau, D.; Gaquiere, C.; Grandjean, N.; Kobn, E., Electron Devices Meeting, 2006. IEDM '06. International , vol., no., pp.l-4, 11-13 Dec. 2006

[3] Maier, D.; Alomari, M.; Grandjean, N.; Carlin, J.-F.; Diforte-Poisson, M.-A.; Dua, C.; Chuvilin, A.; Troadec, D.; Gaquiere, C.; Kaiser, U.; Delage, S.L.; Kohn, E.; IEEE TDMR, vol.lO, no.4, pp.427-436, Dec. 2010. doi: 1O.l109ffDMR201O.2072507

978-1-61284-244-8/11/$26.00 ©2011 IEEE 73

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