© 2007 IBM Corporation IBM Systems1

IBM System z: a mainframe for everyone

A rapid look at

Mainframe Today s Technology

Angelo Barbarino

Senior Consultant I/T Specialist

IBM STG IMT Italy

IBM Systems2

The Mainframe Story has started forty-three years ago (1964 2007)The most recent Mainframes Families .....

S/390S/390--G5 S/390G5 S/390--G6 Z900 Z800 G6 Z900 Z800 Z990 Z890 Z9Z990 Z890 Z9--109 Z9 BC&EC 109 Z9 BC&EC

2000 2001 202000 2001 2002 2002 2003 2004 02 2002 2003 2004 2005 20062005 2006

IBM Systems3

IBM Recent Background : The Mainframe Charter (2003) The Systems Agenda (2005)

The Mainframe CharterInvesting in the future

Innovation Value Community

Deliver IBM Systems and initiatives that encourage and accelerate innovation.

Collaborate to Innovate

Go beyond just industry standards to deliver a choice of innovative systems based on open designs that fit within any IT environment.

Openness

Expand the IBM Virtualization Engine to provide simplified server, storage, networking and data management and new levels of functionality and value.

Virtualize everything

Deliver IBM Systems and initiatives that encourage and accelerate innovation.

Collaborate to Innovate

Go beyond just industry standards to deliver a choice of innovative systems based on open designs that fit within any IT environment.

Openness

Expand the IBM Virtualization Engine to provide simplified server, storage, networking and data management and new levels of functionality and value.

Virtualize everything

IBM Systems4

The Mainframe Power

IBM Mainframes Power

0

100

200

300

400

500

600

700

800

900

1000

1997 1998 1999 2000 2002 2003 2005

Anno

MIP

S

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

MIP

S

MIPS TOT MIPS UNI

IBM mainframes are CISC (Complex Instruction Set Computer) architecture based machinesThe base Technology for chip building is today CMOS (Complementary Metal Oxide Semiconductor)

The basic metric for the Processor Power is MIPS (Millions of [CISC] Instructions per Second)

Year

IBM Systems5

The Mainframes Power for CMOS models

IBM Mainframes CPU

0,00

2,004,00

6,008,00

10,00

12,0014,00

16,0018,00

20,00

R1 R2 R3 G3 G3 G3 G4 G4 G4 G5 G5G5 T G6

G6 TZ8

00Z9

00

Z900

TZ8

90Z9

90 Z9

CMOS Generation

Nan

oS

ecs

Cycle

IBM Systems6

The Mainframes Power for CMOS models

IBM Mainframes CPU

0,00

0,200,40

0,60

0,80

1,001,20

1,40

1,601,80

2,00

R1 R2 R3 G3 G3 G3 G4 G4 G4 G5 G5G5 T G6

G6 TZ8

00Z9

00

Z900

TZ8

90Z9

90 Z9

CMOS Generation

Gig

aHer

tz

1/Cycle

IBM Systems7

The Mainframes Power for CMOS models

MIPS x Uni Processors

0

100

200

300

400

500

600

700

R1 R2 R3 G3 G3 G3 G4 G4 G4 G5 G5G5 T G6

G6 TZ8

00Z9

00

Z900

TZ8

90Z9

90 Z9

CMOS Generation

MIP

S

MIPS x UNI

IBM Systems8

The Mainframe Today = IBM System z9

The IBM System z9 Enterprise Class (z9 EC) formerly called z9-109and the new IBM System z9 Business Class (z9 BC) deliver excellence in

enterprise computing and are designed and optimized for on demand business

z9 Enterprise Class z9 Business Class

New

Now there is a System z9 for everyone

Built on more than 40 years of industry leadership and taking that leadership to new levels

ScalabilityAvailability Security

It s time to rethink the role of the mainframeHelping to drive increased value from data and applications Helping to simplify management and reduce costs

IBM Systems9

The Mainframe Technology Building Blocks The Z Processor

Source : IBM J. RES. & DEV. VOL. 48 NO. 3/4 MAY/JULY 2004

T. J. Slegel ,E. Pfeffer,J. A. MageeThe IBM eServer z990 microprocessor

IBM Systems10

The Mainframe Technology Building Blocks Multiple Chip Module

MSC MSC

CLK

SD SD

SD

SD

SC

PUPU

PU

PU

PUPU

PU

PU

IBM Systems11

The Mainframe Technology Building Blocks Multiple Chip Module

MSC MSCPU PU

PU

PU

PU PU

PU

PUSD SD

SD SD

SCCLK

z9 EC 12-way MCMAdvanced 95mm x 95mm MCM

102 Glass Ceramic layers16 chip sites, 217 capacitors0.545 km of internal wire

CMOS 10Ks0 chip TechnologyPU, SC, SD and MSC chipsCopper interconnections, 10 copper layers8 PU chips/MCM

15.78 mm x 11.84 mm121 million transistors/chipL1 cache/PU

256 KB I-cache256 KB D-cache

0.58 ns Cycle Time4 System Data (SD) cache chips/MCM

15.66 mm x 15.40mmL2 cache per Book

660 million transistors/chip40 MB

One Storage Control (SC) chip16.41mm x 16.41mm162 million transistorsL2 cache crosspoint switchL2 access rings to/from other MCMs

Two Memory Storage Control (MSC) chips14.31 mm x 14.31 mm24 million transistors/chipMemory cards (L3) interface to L2L2 access to/from MBAs (off MCM)

MSC MSCPU PU

PU

PU

PU PU

PU

PUSD SD

SD SD

SCCLK

MSC MSCPU PU

PU

PU

PU PU

PU

PUSD SD

SD SD

SCCLK

z9 EC 12-way MCMAdvanced 95mm x 95mm MCM

102 Glass Ceramic layers16 chip sites, 217 capacitors0.545 km of internal wire

CMOS 10Ks0 chip TechnologyPU, SC, SD and MSC chipsCopper interconnections, 10 copper layers8 PU chips/MCM

15.78 mm x 11.84 mm121 million transistors/chipL1 cache/PU

256 KB I-cache256 KB D-cache

0.58 ns Cycle Time4 System Data (SD) cache chips/MCM

15.66 mm x 15.40mmL2 cache per Book

660 million transistors/chip40 MB

One Storage Control (SC) chip16.41mm x 16.41mm162 million transistorsL2 cache crosspoint switchL2 access rings to/from other MCMs

Two Memory Storage Control (MSC) chips14.31 mm x 14.31 mm24 million transistors/chipMemory cards (L3) interface to L2L2 access to/from MBAs (off MCM)

IBM Systems12

The Mainframe Technology Building Blocks The Book

Each Book can contain one MCM with 8 CPUs Dual Core

Memory CardsUp to 128 GB

MCM

"D6"

"D4" "D5"

"F1" "D1" "D2"

"D3"

"D7" "D8"

Up to 8Hot pluggable MBA/STI fanout cards

Side viewFront view

MSC

MSC

CP 2

CP CP

HitachiCP HitachiCP

SD

SD SD

SD

SC

MSC

MSC

CP 2

CP CP

HitachiCP HitachiCP

SD

SD SD

SD

SC

Books may be able to be inserted into orremoved from the ring non disruptively

IBM Systems13

The Mainframe Technology Building Blocks System Components

CPU s

Central & Expanded Storage

Level 1,2 Chaches MBA STI

I/O Cards

I/O Cards

I/O Cards

I/O Devices

ISC

Other

Spec Conn

IBF SEPower & Cooling

Specialized CPUsHSA

IBM Systems14

The Mainframe Technology Building Blocks Specialized Engines

MCM can deploy 16 Processors Engines:

Engines can be active or inactive.

When activated each Engine can be specialized as :

General Purpose (CPU)

Standard architecture Processor

Integrated Coupling Facility (ICF)

Related to Clustering Technology

Integrated Facility for Linux (IFL)

Runs only Linux Workloads

Z Application Assist Processor (zAAP)

Runs only Java Workloads

Z Integrated Information Processor (zIIP)

Runs only Data Base & Utility Workloads

Service Assist Processor (SAP)

Related to the I/O Services

Spare

Automatically activated in case of failures

Configuration rules:

2 SAP per Book

2 Spare per System

The zAAP number must be less or equal to CPU.

The zIIP number must be less or equal to CPU.

Systems with IFL or ICF only can be built.

IBM Systems15

The Mainframe Technology Building Blocks How Specialized engines work - zAAP & zIIP

zIIP & zAAP are co-processors

zAAP can run only Java Code related TCBsI/O instructions are not allowed

zIIP can run only DB2 Code related SRBsI/O instrctions are not allowed

CentralStorage

Dispatcher

CPU CPU zAAP

I/O I/O

Memoria

Dispatcher

CPU CPU zAAP

I/O I/O

CentralStorage

Dispatcher

CPU CPU zIIP

I/O I/O

IBM Systems16

The Mainframe Technology Building Blocks How Specialized engines work - SAP ICF IFL - Spare

SAP processor runs only microcode related to I/O operations management User cannot access the SAP SAPs processors (2 per book on EC ) are mandatory.

ICF processor runs a specific code named Coupling Facility Control Code (CFCC) ICFs processors are required and used only by Parallel Sysplex Cluster Technology. (see later). ICFs are optional.

IFL is a standard processors with a specific filter able to execute only LINUX code or LINUX virtualized code. IFLs are optional.

Spare processors can be activated automatically in case of CPU failure they assume the specialization of the failing processor. Spare processors (2 per System on EC) are mandatory.

The activation and use of Specialized CPU isn t only a technical issue (SAP,ICF,Spare), but also related to TCO reduction (IFL,zAAP,zIIP)

IBM Systems17

Use of Specialized Engines to reduce TCOExample (Five Processors System)

CP zIIP SzAPP CP

CP zAPP SCPCP

CP SCPCP CP

IFLCP zAPP SCP

IFL zIIP SCPIFL

IFL SCPIFL IFL

IFLIFL SIFL IFL

Power = 4 - Sw Charge = 4

Power = 4 - Sw Charge = 3

Power = 4 - Sw Charge = 2

Power = 4 - Sw Charge = 2

Power = 4 - Sw Charge = 1

Power = 4 - Sw Charge = 1

Power = 4 - Sw Charge =0

IBM Systems18

Use of New Software Charge Schemas to reduce TCONew Workloads License Charge is now Sub Capacity deliverable

System z New Application License Charges (zNALC)

Attractive pricing for z/OS operating system to drive qualified new workloads to the System z platform

Announce: 9 January 2007 // GA: 16 March 2007

Satisfies the SoD Announced with z/OS 1.7 (July 2005)IBM plans to announce a version of New Application License Charges (NALC) intended to help

improve the price performance of z/OS in certain new workload environments by delivering subcapacity pricing. . .

$ K

$20 K

$40 K

$60 K

$80 K

$100 K

$120 K

$140 K

$160 K

1 501 1001 1501 2001 2501MSUs

zNALC NALC

$ K

$20 K

$40 K

$60 K

$80 K

$100 K

$120 K

$140 K

$160 K

1 501 1001 1501 2001 2501MSUs

zNALC z/OS.e EWLC

IBM Systems19

The Mainframe Technology Building Blocks Configuration Options System z9-EC

Machine Type2094

5 ModelsS08, S18, S28, S38 and S54

Processor Units (PUs)12 (16 for Model S54) PUs per book2 SAPs per book, standard2 spares per server8, 18, 28, 38 or 54 PUs available for characterization

Central Processors (CPs), Integrated Facility for Linux (IFLs), Internal Coupling Facility (ICFs), System z Application Assist Processors (zAAPs), System z9 Integrated Information Processor (zIIP), optional System Assist Processors (SAPs)

MemoryMinimum of 16 GBUp to 128 GB per bookUp to 512 GB for System

16 GB incrementsI/O

Up to 16 STIs per book @ 2.7 GB/s eachTotal system I/O bandwidth capability of 172.8 GB*Up to 4 Logical Channel Subsystems (LCSSs)

* z9 EC exploits a subset of its designed I/O capability

IBM Systems20

IBM System z9 EC

Hybrid Cooling

CPU Books Memory

CEC Cage

STI

SE

3x I/Ocages

PowerSupplies

InternalBatteries

180 Cm

210 Cm

IBM Systems21

IBM System z9 EC

Hybrid Cooling

CPU Books Memory

CEC Cage

STI

SE

3x I/Ocages

PowerSupplies

InternalBatteries

180 Cm

210 Cm

IBM Systems22

The Mainframe Technology Building Blocks Configuration Options System z9-BC

z9 BC is an only one book system

Each book contains 8 processors

Machine Type2096

ModelR07

Processor Units (PUs)8 PUs per System1 SAP per book, standardNo dedicated spares 7 PUs available for characterization

1 to 3 (CPs)IFLs, ICFs ,zAAPs, zIIPs),or optional SAPs

Up to 15 LPARsMemory

Minimum of 8 GBUp to 64 GB per System

8 GB incrementsI/O

Up to 16 STIs per System @ 2.7 GB/s eachTotal system I/O bandwidth capability of 43.2 GBUp to 2 Logical Channel Subsystem (LCSS)Up to a maximum of 4 I/O Domains

Up to 240 channels dependent on Channel types

Machine Type2096

ModelS07

Processor Units (PUs)8 PUs per System1 SAP per book, standardNo dedicated spares 7 PUs available for characterization

0 to 4 (CPs)IFLs, ICFs ,zAAPs, zIIPs),or optional SAPs - IFL-only allowed Up to 30 LPARs

MemoryMinimum of 8 GBUp to 64 GB per System

8 GB incrementsI/O

Up to 16 STIs per System @ 2.7 GB/s eachTotal system I/O bandwidth capability of 43.2 GBUp to 2 Logical Channel Subsystems (LCSSs)Up to a maximum of 7 I/O Domains

Up to 420 channels dependent on Channel types

IBM Systems23

IBM System z9 BC

IBM Systems24

IBM System z9 BC

I/O Cage

PowerSupplies

InternalBatteries(optional)

Single Processor Book and Memory

CEC Cage

I/O Cage

PowerSupplies

InternalBatteries(optional)

Single Processor Book and Memory

CEC Cage

IBM Systems25

Mainframe Capacity Options

*A01 *J01 *A02 *F02 *A03 *D03

1-way 2-way 3-way

IBM Systems26

Mainframe Capacity Options

*K04 *Z04*R01 *Z01 *N02 *Z02 *L03 *Z03

1-way 2-way 3-way 4-way*K04 *Z04*R01 *Z01 *N02 *Z02 *L03 *Z03

1-way 2-way 3-way 4-way

IBM Systems27

Mainframe Capacity Options

401501601701

402502602702

403503603703

404504604704

405505605705

406506606706

407507607707

408508608708

1-way 2-way 3-way 4-way 5-way 6-way 7-way 8-way

401501601701

402502602702

403503603703

404504604704

405505605705

406506606706

407507607707

408508608708

1-way 2-way 3-way 4-way 5-way 6-way 7-way 8-way

IBM Systems28

Mainframe Capacity Options

701 710702

703

704705

706

707708

709

713714

715711

712

716717

718

719720

721

722723

724

725726

727

728729

730

731732

733

734735

736

737738

Model S18

Model S38

Model S28

Model S08

*CI

Model S54

754

IBM Systems29

The Mainframe Technology Building Blocks Capacity On Demand

Matching resource acquisition to business needs

Provides nondisruptivegrowth, limited downtime and payment when activated

Assures capacity is always available and allows for reduced purchased or financed capacity

Provides processing for planned and unplanned spikes to improve cost control

Cost-effective disaster recovery resources

Permanent capacity upgrade

Capacity Upgrade

on Demand

Standby Capacity

on Demand

On/Off Capacity

on Demand

Capacity backup

Temporarycapacity

Permanent capacity upgrade

Capacity Upgrade

on Demand

Standby Capacity

on Demand

On/Off Capacity

on Demand

Capacity backup

Temporarycapacity

Enables scale up on same hardware

Little impact on current operations

Predictable pricing model

Protects business continuity

Cost efficient

Rapidly available

Predictable workloads

Unpredictable or variable workloads

Predictable workloads

Unpredictable or variable workloads

IBM Systems30

The Mainframe Technology Building BlocksIntegrated Virtualization (PR/SM)

Multi-dimensionalvirtualization technology

zSystem provides logical (LPAR) and software (z/VM)PartitioningPR/SM enableshighly scalablevirtual serverhosting for LPAR and z/VM virtual machineenvironmentsIRD coordinatesallocation of CPU and I/O resources among z/OS and non-z/OS LPARsI/O can be shared directly by partitions

IFL Processors

Memory

z/VM

Linux Linux CMS Linux

L P A R

Memory

z/OS

L P A R

Control Program

WebSphere

Memory

L P A R

Processor Resource / System Manager (PR/SM)

Traditional OLTP and

BatchApacheSysAdmin

Tools

WebSphere

Test

HiperSockets & Virtual Networking and Switching

WLM WLM

I/O & Network

Intelligent Resource Director (IRD)

Processors

z/OS

z/VM

Linux

FTP

z/OS

Test

Memory

L P A R

IBM Systems31

The Mainframe Technology Building BlocksIntegrated Clustering

32 System Images2+ Coupling Facility 2 Sysplex Timers

Full Data Sharing Support

Parallel Sysplex ClusterIBM System z

IBM System z

IBM System z

IBM System z

IBM System z

CF

z/OS

z/OS

z/OS

z/OS

CF

100 Km

100 Km

100 Km

100 Km

IBM Systems32

The Mainframe Technology Building BlocksConnections Example

CF

CF

ISC3ISC3

FCP

ISC3

ESCON

FICON

PARALLEL

OSA

ESCON

FICON

IBM Systems33

Mainframe Technology Uniqueness

Integrated Crypto/SSL

Specialized Engines

On Demand Engines Dynamic Reconfiguration

I/O Dedicated Engines

Integrated HW Compression

z/OS Operating System and Features

IBM Systems34

Mainframe ArchitectureBasics

The IBM Mainframe machines are based on CISC processor built on CMOS chip technology.

The System basic concepts and architecture are based on the z/Architecture.

IBM has defined the z/Architecture rules on the z/Architecture Principle of Operation book . It covers:

System design

Memory Management

I/O Subsystem

Instruction Set (64bit CISC)

Integrated Cryptography

Computer Operation and Error Handling

The z/Architecture is backward compatible with previous defined IBM architectures:

ESA/390 (1990)

S/370 XA (1980)

S/370 (1970)

IBM Systems35

Mainframe ArchitectureMain Characteristics

Binary Code compatibility between architecture compatible computers.

Virtual Memory Management (Paging, Swapping).

Trimodal Addressing (24,31,64 bit).

PSW Precise Interruption

CISC Instruction set (21 Format and about 640 complex instructions).

Integrated Hardware Compression

Integrated Cryptography

Proven Availability and Reliability

Integrated Security

Proven high efficiency

Open Standard and new Workloads Support: Java, TCP/IP,Linux,SOA)

System Integrity and Logical Partition Isolation

Operating Environment

Extended and accurate debugging tools

Business Continuity Capabilities

Advanced Workload Management

I/O Management efficiency

IBM Systems36

Mainframe ArchitectureI/O Management

CPUChannel Based

System

Channel PGM

CUSub Channel

SAP

DeviceCU-Firmware

Dynamic PathReconnect

Disconnect

Sub Channel

Disconnect Path

Interrupt

USER PGM

FREE

FREE

Interrupt

USER PGM

Z Architecture

IBM Systems37

The Mainframe is today Open System

Native Linux support

Specialty engines for Linux

up to 7-way Linux only systems

Industry standards support

zICF

1997

zIFL

2001

zAAP

2004

zIIP

2006Linux

Java

J2EE

Grid

Web Services

SQL

UNIX

Autonomic Sys. Mgmt

SOA

© 2007 IBM Corporation IBM Systems38

IBM System z: a mainframe for everyone

A rapid look at

Mainframe Today s Technology

Angelo Barbarino

Senior Consultant I/T Specialist

IBM STG IMT Italy