High speed InP-basedheterojunction bipolar transistors

Mark Rodwell

University of California, Santa Barbara

rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax

2001 ISCS Conference, October, Tokyo

How to Improve the Bandwidth of Bipolar Transistors ?

collex

Ebc

Ejecollectorbase RR

qI

kTC

qI

kTC

f

2

1

Thinner base, thinner collector higher f , but higher Rbb, Ccb

what parameters are really important in HBTs ?how do we improve HBT performance ?

HBT scaling: transit times

WE

WBC

WEB

x

L E

base

emitter

base

collector

WCreduce Tb by 2:1

b improved 2:1

reduce Tc by 2:1

c improved 2:1

note that Ccb has been doubled ..we had wanted it 2:1 smaller

nbb DT 2/2

satcb vT 2/

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

EC WW ~ Assume

HBT scaling: lithographic dimensions

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

Ccb/Area has been doubled ..we had wanted it 2:1 smaller…must make area=LeWe 4:1 smallermust makeWe & Wc 4:1 smaller

Everticalcsheet

contact

contactspreadgapbb

L

R

RRRR

2,

Base Resistance Rbb must remain constant Le must remain ~ constant

reduce collector width 4:1reduce emitter width 4:1keep emitter length constant

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

EC WW ~ Assume

HBT scaling: emitter resistivity, current density

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

Emitter Resistance Rex must remain constantbut emitter area=LeWe is 4:1 smallerresistance per unit area must be 4:1 smaller

increase current density 4:1reduce emitter resistivity 4:1

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

Collector current must remain constantbut emitter area=LeWe is 4:1 smallerand collector area=LcWc is 4:1 smallercurrent density must be 4:1 larger

EC WW ~ Assume

for x 2 improvement of all parasitics: ft, fmax, logic speed…base 2: 1 thinnercollector 2:1 thinneremitter, collector junctions 4:1 narrowercurrent density 4:1 higheremitter Ohmic 4:1 less resistive

Scaling Laws for fast HBTs

Challenges with Scaling:Collector mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer lengthsets minimum size for collector Emitter Ohmic: hard to improve…how ?Current Density: dissipation, reliabilityLoss of breakdownavalanche Vbr never less than collector Egap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power

emitterbase contact

collectorcontact

SI substrate

InGaAs subcollector

InP collector

InGaAscollector

InP subcollector

InGaAs base

undercutcollector junction

base contactemitter

base contact

SI substrate

base

sub collector

base contact pad

collectorcontact

polymer polymer

collector-base junction

Narrow-mesa with 1E20 carbon-doped base

undercut-collector

transferred-substrate

Transferred-Substrate HBT Process Flow UCSBONR

Ultra-high fmax Transferred-Substrate HBTs

• Substrate transfer provides access to both sides of device epitaxy

• Permits simultaneous scaling of emitter and collector widths

• Maximum frequency of oscillation

• Sub-micron scaling of emitter and collector widths has resulted in record values of extrapolated fmax

• Extrapolation begins where measurements end

• New 140-220 GHz Vector Network Analyzer (VNA) extends device measurement range

0

5

10

15

20

25

30

10 100 1000

Gai

ns,

dB

Frequency, GHz

fmax = 1.1 THz ??

f = 204 GHz

Mason's gain, U

H21

MSG

Emitter, 0.4 x 6 m2

Collector, 0.7 x 6 m2

Ic

= 6 mA, Vce

= 1.2 V

3000 Å collector400 Å base with 52 meV gradingAlInAs / GaInAs / GaInAs HBT

cbbbCRff 8/max

Michelle Lee

140-220 GHz network analysis

HP8510C network analyzer & Oleson Microwave Lab frequency Extenders

GGB waveguide-coupled probes

75-100 GHz network analysis

GGB waveguide-coupled probes HP W-band test set

1-50 GHz network analysis

GGB coax-connectorized probes HP 0.045-50 GHz test set

220 GHz On-Wafer Network AnalysisMiguel Urteaga

0

5

10

15

20

25

30

35

1 10 100Frequency, GHz

MSG

h21

Mason'sGain, U

• Submicron HBTs have very low Ccb (< 5 fF)

• HBT S12 is very small

• Standard 12-term VNA calibrations do not correct S12 background error due to probe-to-probe coupling

Solution

Embed transistors in sufficient length of transmission line to reduce coupling

Place calibration reference planes at transistor terminals

Line-Reflect-Line Calibration

Standards easily realized on-wafer

Does not require accurate characterization of reflect standards

Characteristics of Line Standards are well controlled in transferred-substrate microstrip wiring environment

Accurate Transistor Measurements Are Not Easy

Transistor in Embedded in LRL Test Structure

230 m 230 m

Corrupted 75-110 GHz measurements due toexcessive probe-to-probe coupling

140 150 160 170 180 190 200 210 220

freq, GHz

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

freq (75.00GHz to 110.0GHz)

Can we trust the calibration ?

freq (140.0GHz to 220.0GHz)

S11 of throughAbout –40 dB

140-220 GHz calibration looks OK75-110 GHz calibration looks Great

S11 of openAbout 0.1 dB / 3o error

dBS21 of through line is off by less than 0.05 dB

S11 of openS11 of short S11 of through

75 80 85 90 95 100 105 110

freq, GHz

-70

-65

-60

-55

-50

-45

-40

Probe-Probe couplingis better than –45 dB

Miguel Urteaga

Submicron transferred-substrate HBTs

0.25 m emitter-base junction

0.4 m Schottky collector

Emitter: 0.3 x 18 m2, Collector: 0.7 x 18.6 m2

Ic = 5 mA, Vce = 1.1 V

Submicron InAlAs/InGaAs HBTs: Unbounded (?!?) Unilateral power gain 45-170 GHz

Gains are high at 200 GHzbut fmax can’t be determined

1E10 1E11 1E12

Freq.

-5

0

5

10

15

20

25

30

35

40

RF G

ains

U

MAG/MSG

h21

unbounded U

UCSBONR

emitter

collector

Miguel Urteaga

Negative Unilateral Power Gain ???

YES, if denominator is negative

This may occur for device with a negative output conductance (G22) or some positive feedback (G12)

12212211

2

1221

GGGG4

YY

U

1221L2211

2

1221

GGGGG4

YY

U

2-portNetwork G L

Select GL such that denominator is zero:

Can U be Negative?

What Does Negative U Mean?

Device with negative U will have infinite Unilateral Power Gain with the addition of a proper source or load impedance

AFTER Unilateralization• Network would have negative output resistance

• Can support one-port oscillation

• Can provide infinite two-port power gainU

Simple Hybrid- HBT model will NOT show negative U

Ccb Cancellation by Collector Space-Charge

collector space-charge layer

cbV

sat

cc

cbccb

base

v

TI

VT

A

V

Q

2

cb

cc

ccb V

IT

AC

1.8

2

2.2

2.4

2.6

2.8

0 1 2 3 4 5 6 7

IC, mA

measured0.64 fF decrease

Ccb

tota

l

Ic

Collector space charge screens field, Increasing voltage decreases velocity, modulates collector space-chargeoffsets modulation of base chargeCcb is reduced

Moll & Camnitz, Betser and Ritter

175 GHz Single-Stage AmplifierSubmicron HBT Program

UCSBMiguel Urteaga

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200 210 220

S21S11S22

dB

Freq. (GHz)

0.2pF

50 301.2ps

50

300.2ps

801.2ps

0.6ps

801.2ps

50

IN

OUT

6.3 dB gain at 175 GHz

295 GHz f, & fmax HBT UCSBYoram Betser

Emitter 1 x 8 m2, Collector 2 x 8.5 m2.0

10

20

30

40

50

1 10 102

Gai

ns

(dB

)

Frequency (GHz)

h21

U

VCE

= 1 V, JC = 1.5 mA/um2

fMAX

= 295 GHz

f = 295 GHz

2000 Å collector300 Å base with 52 meV gradingAlInAs / GaInAs / GaInAs HBT

1E9 1E10 1E11 1E12

freq, Hz

-20

-15

-10

-5

0

5

10

15

20

dB(h

21)

UdB

(sho

rt..S

(2,1

))

m1freq=303.0GHzdB(short..S(2,1))=0.000

m1

m2freq=165.0GHzdB(short..S(2,1))=0.000

m2

0

1

2

3

4

5

6

7

8

0 1 2 3 4 5 6

Ic - V

ce characteristics

I c (m

A)

Vce

(volts)

IB in steps

of 20 uA

Fast InP DHBTs

f= 165 GHz; fmax = 303 GHz

5 V breakdown at 105 A/cm2

>9 V at 2*104 A/cm2

UCSBpk SundararajanM Dahlstrom

1x 8 micron emitter, 2x 10 micron collector

3 kÅ collector, 400 Å base

1E9 1E10 1E11 1E12

freq, Hz

-20

-15

-10

-5

0

5

10

15

20

dB(h

21)

UdB

(sho

rt..S

(2,1

))

m1freq=216.0GHzdB(short..S(2,1))=-1.086E-10

m1

f= 216 GHz;fmax = 210 GHz

0

2 104

4 104

6 104

8 104

1 105

0 1 2 3 4 5

Jc - V

ce characteristics

J c (A

/cm

2)

Vce

(volts)

4 V breakdown at 105 A/cm2

>6 V at 2*104 A/cm2

2 kÅ collector, 400 Å base

1x 8 micron emitter, 2x 10 micron collector

0

1

2

0 2 4 6 8

I C (

mA

)

VCE

(V)

Ib step = 20 A

0

10

20

30

40

1 10 100

Ga

ins

(dB

)Frequency (GHz)

U

h21

UCSBSangmin Lee

fmax = 425 GHz, ft = 139 GHz

InGaAs/InP DHBT, 3000 Å InP collector

0.5 m x 8 m emitter (mask)0.4 m x 7.5 m emitter (junction)1.2 m x 8.75 m collectorIc=4.5 mA, Vce=1.9 V

BVCEO = 8 V at JE =5*104 A/cm2

Is low DHBT f due to base-collector grade ?

480 Å grade 100 Å grade

collector velocity and grade: InP has higher Gamma-L separation than InGaAs→ Vsat should be higher in InP → ft should be higher, not lowerslow transport in InAlAs ? → thin grade !

0.5 m emitter, 0.25 m basecontacts

Narrow-Mesa HBTs: high fmax if high base doping

InP/InGaAs/InP Metamorphic DHBTon GaAs substrate

UCSB

165 GHz ft

92 GHz fmax

triple-mesa device(not transferred-substrate)

Growth: 400 Å base, 2000 Å collector GaAs substrate InP metamorphic buffer layer

(high thermal conductivity)Processing conventional mesa HBT narrow 2 um base mesaResults 165 GHz ft, 92 GHz fmax,

6 Volt BVCEO, =27

High Speed Amplifiers

18 dB, DC--50+ GHz

UCSBDino Mensa

PK Sundararajan

8.2 dB, DC-80 GHz

-20

-15

-10

-5

0

5

10

15

20

0 10 20 30 40 50

>397 GHz gain x bandwidth from 2 HBTs

S22

S11

S21

HBT distributed amplifier UCSBPK Sundararajan11 dB, DC-87 GHz

AFOSR

TWA with internal ft-doubler cells

18 GHz ADC

Design comparator is 75 GHz flip flop DC bias provided through 1 K resistors Integration obtained with 3 pF capacitors RTZ gated DAC

Integrated Circuit150 HBTs, 1.2 x 1.5 mm, 1.5 W

gm2

Bias

Bias

C

C

Rz

Rz

Integrator-1 Integrator-2

Bias

Bias

C

C

Master-Slave

Flip-flop

Clock

Out

Idac

gm1

DelayedClock

Vin

CurrentSumming

node

RL

RLRL

RL

UCSBS Jaganathan

75 GHz HBT master-slave latchconnected as Static frequency divider

technology: 400 Å base, 2000 Å collector HBT 0.7 um mask (0.6 um junction) x 12 um emitters 1.5 um mask (1.4 um junction) x 14 um collectors 1.8105 A/cm2 operation, 180 GHz ft, 260 GHz fmax

simulations: 95 GHz clock rate in SPICE

test data to date:tested, works over full 26-40 and 50-75 GHz bands

UCSBThomas Mathew

Hwe-Jong Kim

-0.14

-0.12

-0.1

-0.08

-0.06

-0.04

-0.02

0

0 50 100 150 200

fin=75GHz, f

out=37.5GHz

Vo

ut

(Vo

lts)

Time(ps)

-0.11

-0.1

-0.09

-0.08

-0.07

-0.06

-0.05

-0.04

-0.03

0 50 100 150 200

fin=69GHz, f

out=34.5GHz

Vo

ut(

Vo

lts)

Time(PS)

modulation is synthesizer 6 GHz subharmonic

3.92 V, 224 mA, 0.88 W

~3.5 dBm input power

MHBT slide

State-of-art in HBTs, 2000: cutoff frequencies

InP HBTs today 2x faster, & more scalable: Johnson limit, 2x faster at 5x larger dimensions

0 50 100 150 200 250 300 350

Frequency, GHz

SiGe

InP

AlGaAs/GaAs & GaInP/GaAs

f

fmax

f

f

fmax

fmax

~1 um emitters

~1 um emitters(0.4 um)

~0.1 um emitters

(UCSB t.s.device)

State-of-Art in HBTs, 2000: small-scale circuits

0 20 40 60 80 100

Frequency, GHz

A

SiGe

InP

amplifiers

logic

logic

amplifiers

Si / SiGe has rough parity in logic with InP despite lower f, fmax

due to higher current density, better emitter contacts

Si/SiGe has significantly slower amplifiers

Neither f nor fmax predicts digital speed

CcbVlogic/Ic is very important

collector capacitance reduction is critical increased III-V current density is critical

Rex must be very low for low Vlogic at high Jc

InP: Rbb , (b+c) , are already low, must remain so

What do we need for fast logic ?

clock clock clock clock

inin

out

outECL M-S latch

cexLOGIC

LOGIC

Ccb

becb

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

6

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitancDepletion

swing logic the through

charging ecapacitancDepletion

:by DeterminedDelay Gate

bb

depletion,bb

depletion,

What HBT parameters determine logic speed ?

exCicex

bbcbc

cbdiffcbje

RIqkTVR

RIV

CCC

/6 as effect,indirect strong very has

from 17% ,)( from 12% ,/ from 68%

:imes transit tand sresistanceby Delays Sorting

) (e.g. charging 18%only , charging 38% , charging 44%

:escapacitancby Delays Sorting

log

logic

Caveats: assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 3kÅ thick, 400 Å base, 1.5E5 A/cm^2)

ignores interconnect capacitance and delay, which is very significant

Cje Ccbx Ccbi b+c) ( I/V) totalV/ I 33.5% 6.7% 27.8% 68.4%V/ I 12.3% 12.3%(kT/q) I 1.4% 0.1% 0.4% 0.5% 2.5%Rex -1.3% 0.1% 0.3% 0.9% 0.1%Rbb 10.2% 2.8% 3.7% 16.7%total 43.8% 6.8% 31.3% 17.5% 100.0%

38%

Why isn't base+collector transit time so important ?

reductionsuch no see escapacitancDepletion

1:10~ is which ,/

of ratioby reduced ecapacitancdiffusion signal-Large

)()(Q

:Operation Signal-LargeUnder

/

)()()(Q

:Operation Signal-SmallUnder

base

base

qkT

V

VV

II

VqkT

IV

dV

dII

LOGIC

LOGICLOGIC

dccbCcb

beCcb

bebe

CcbCcb

Very strong features of Si-bipolars

Emitter Width:0.1 um

Emitter Current Density10 mA/um2

Polysilicon Emitter Contactmetal-semiconductor contactarea >> emitter junction area low Rex

Polysilicon base contactlow sheet resistance in extrinsic basesmall extrinsic collector-base junction area

InP HBT limits to yield: non-planar processEmitter contact

Etch to base

Liftoff base metal

Failure modes

Yield degrades as emitters arescaled to submicron dimensions

base contact

emittercontact

base contact

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

emitter

S.I. substrate

base

sub collector

Emitter planarization, interconnects

base contact

liftoff failure:emitter-baseshort-circuit

S.I. substrate

base

sub collector

base contact

excessiveemitter undercut

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

planarization failure: interconnect breaks

Submicron HBT scaling:

Scaling HBTs for 2 x increased speed:2 x thinner layers, 4 x narrower junctions4 x higher current density, 4 x improved vertical contacts

Results with submicron III-V HBT scaling:300 GHz f, high (unmeasurable) fmax

6-dB 175 GHz amplifiers, 75 GHz true digital ICs

Challenges with HBT scaling for fast digital :collector width scaling, current density, emitter resistivityhigh-yield submicron emitter & collector processes

In Case of Questions

Scaling Laws, Collector Current Density, Ccb charging time

base

emitter

collector

subcollector

base

emitter

collector

subcollector

Base Push-Out (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 dxqNvJV dsatcb

)2/)(/( 2 dxvJqNV satdcb 2

minmax /)(4 dcbsat xVvJJ

Collector capacitance charging time is reduced by thinning the collector while increasing current

sat

C

CB

LOGICCLOGICcCLOGICcb v

T

A

A

V

VIVTAIVC

22

1/

emitter

collectorcollector