Transistor and Circuit Design for 100-200 GHz ICs

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

Mark Rodwell University of California, Santa Barbara

V. Paidi, Z. Griffith, D. Scott, Y. Dong, M. Dahlström, Y. Wei, N. ParthasarathyUniversity of California, Santa Barbara

Lorene Samoska, Andy FungJet Propulsion Laboratories

M. Urteaga, R. Pierson , P. Rowell, B. BrarRockwell Scientific Company

S. Lee, N. Nguyen, and C. NguyenGlobal Communication Semiconductors

2004 IEEE Compound Semiconductor IC Symposium, October, Monterey

Potential applications for 100-300 GHz Electronics

Optical Fiber Transmission

40 Gb/s: InP and SiGe ICs commercially available

80 & 160 Gb/s is feasible80-160 Gb/s InP ICs now clearly feasible ~100 GHz modulators demonstrated (KTH Stockholm)100 + GHz photodiodes demonstrated in 1980'schallenge: limit to range due to fiber dispersionchallenge: competition with WDM using 10 Gb CMOS ICs

Radio-wave Transmission / Radar / Imaging

65-80 GHz, 120-160 GHz, 220-300 GHz100 Gb/s transmission over 1 km in heavy rain300 GHz imaging for foul-weather aviation

sciencespectroscopy, radio astronomy

Mixed-Signal ICs for Military Radar/Comms

direct digital frequency synthesis, ADCs, DACshigh resolution at very high bandwidths sought

40 Gb/s InP HBT fiber chip set (Gtran Inc.)

100 Gb/s over 1 km in heavy rain : 250 GHz carrier

300 GHz imagining radar for foul-weather aviation

Fast IC Technologies

InP HBT:

Advantages 3.5x107 cm/s collector velocity 500 Ohm/square base sheet

Performance 500 nm scaling generation: 400 GHz f / 500 GHz fmax

4 V breakdown 150 GHz static dividers 178 GHz amplifiers

Comments scaling will improve bandwidth scaling can reduce power small market <-> high cost

SiGe HBT:

Advantages superior scaling extrinsic parasitic reduction CMOS integration

Performance 130 nm scaling generation: 210 GHz f / 270GHz fmax

96 GHz static dividers 77 GHz amplifiers 150 GHz push-push VCO- 75 GHz fundamental

SOI CMOS:

Advantages cost, power, integration scales

Performance 90 nm scaling generation: ~200 GHz f & fmax

60 GHz 2:1 mux 91 GHz amplifiers

Optical Transmitters / Receivers are Mixed-Signal ICs

TIA: small-signal

aa

routebuffer

SwitchWideband Optical Transceiver

clockPLL

AD

DMUX

O/E, E/O interfaces

MUX

AD

AD

IQ

I

Q

DMUX

DMUX

mm-wave interfaces

I

Q

DA

DA

IQ

electronicor optical

Wideband mm-Wave Transceiver

Electronics for GigaHertz Communication

poweramplifier

MUX

addressdetect

PLL

Switches:network protocols,digital control, fast ICs,optical, electronic switches

Rf

Rc

Q1

Q2

I1

I2

Rf

Rc

Q1

Q2

I1

I2

  LIA: often limiting MUX/CMU & DMUX/CDR:mostly digital

Small-signal cutoff frequencies (ft , fmax) are ~ predictive of analog speed

Limiting and digital speed much more strongly determined by I/C ratios

We design HBTs for low gate delay, not for high f & fmax

clock clock clock clock

inin

out

out

cexLOGIC

LOGIC

Ccb

becbi

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

4

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitanc on Depleti

swing logic the through

charging ecapacitanc on Depleti

:by ermined Delay DetGate

bb

depletion,bb

depletion,

JVR

v

T

A

A

V

V

I

VC

T)V(VvεJ

CI

CCIV

f

ex

electron

C

CE

LOGIC

C

LOGICcb

cceceelectronKirk

cbC

becbCLOGIC

cb

highat low for low very bemust

22

/2

objective. design key HBTa is / High

total.of 80%-55% is

withcorrelated not well Delay

delay; totalof 25%-10y typicall)(

logic

emitter

collector

min,

2depletion full,operating ,max,

depl,

1:10~ is which ,/

of ratioby reduced

ecapacitancdiffusion signal-Large

)(

)(Q

:Operation Signal-LargeUnder

swing. voltage/over only ...active

/

)(

)(

)(Q

:ecapacitancDiffusion

base

base

qkT

V

VV

I

I

qkT

VqkT

I

VdV

dI

I

LOGIC

LOGICLOGIC

dccb

Ccb

beCcb

bebe

Ccb

Ccb

Why isn't base+collector transit time so important for logic?

Depletion capacitances present over full voltage swing, no large-signal reduction

Vin

Vout

Vin(t)

t

t

Vout(t)

diffusion+ depletioncapacitance

only depletioncapacitance

Scaling Laws, Collector Current Density, Ccb charging time

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2min, cTqNV dcb

0 mA/m2

10 mA/m2

0 mA/m2

10 mA/m2

GaAsSb base InGaAs base

sat

C

CECE

LOGICCLOGICcCLOGICcb v

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,collector

2min,max /)2(2 ccbcbsat TVVvJ

cecbbe VVV )( hence , that Note

Collector capacitance charging time scales linearly with collector thickness if J = Jmax

.1 where; 2max,

emitter

logiccollectorlogicce

eCCcb /TJ

AJ

V

T

εA

I

VC

ex 7 m2 needed for 200 GHz clock rate

ECL delay not well correlated with f or fmax

Key HBT Scaling Limit Emitter Resistance

Io

RL

Rex

Noise margin

2kT/q+IoRex

Vin

Vout

Vlogic=IoRL

Vlogic

Largest delay is charging Ccb

Je 10 mA/m2 needed for 200 GHz clock rate

Voltage drop of emitter resistance becomes excessive

RexIc = exJe = (15 m2) (10 mA/m2) = 150 mV

considerable fraction of Vlogic 300 mV

Degrades logic noise margin

Breakdown: Thermal failure is more significant than BVCEO

0

2

4

6

8

10

12

0 1 2 3 4 5 6

device failure

18 mW/um2

design limit 10 mW/um 2

J max

(m

A/u

m2)

Vce

(V)

8 m emitter metal length, ~0.6 m junction width

biased without failure (DC-IV)

No RF driftafter 3-hr burn-in ECL

bias points

0

2

4

6

8

10

12

14

0 1 2 3 4 5 6 7 8

J e (m

A/

m2 )

Vce

(V)

Ajbe

=0.6 x 7 m2 Ib step

= 0.4 mA0.5 um X 7 um emitter junction0.5 um base contact width

~6.8 V low-currentBVCEO

resistance lmW therma/m)( K7~ 2

2max

2

/1

densitypower limits nDissipatio

clockja

CEclockceEE

fV

VfVJAP

collectors thin withincreases because

nslowly tha more decreases

relevantnot often breakdowncurrent -low

high requires and High

low at measured is -or -Breakdown

max

1collectormax,

max

,,

E

fTEV

Jff

JVV

clockceobr

e

ecbobrceobr

Low thermal resistance is critical.DHBTs are superior to SHBTs.

Bipolar Transistor Scaling Laws & Scaling Roadmaps

key device parameter required change

collector depletion layer thickness decrease 2:1

base thickness decrease 1.414:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter resistance per unit emitter area decrease 4:1

current density increase 4:1

base contact resistivity (if contacts lie above collector junction)

decrease 4:1

base contact resistivity (if contacts do not lie above collector junction)

unchanged

Scaling Laws:design changes required to double transistor bandwidth

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

InP Technology Roadmap 40 / 80 / 160 Gb/s digital clock rate

Key scaling challengesemitter & base contact resistivitycurrent density→ device heatingcollector-base junction width scaling & Yeild !

key figures of merit

for logic speed

InP DHBTs: 600 nm emitter width, 150 nm thick collector

0

5

10

15

20

25

30

35

109 1010 1011 1012

Gai

ns

(dB

)

Frequency (Hz)

ft = 391 GHz, f

max = 505 GHz

U

H21

Ic = 13.2 mA

Ajbe

= 0.6 x 4.25 um2

Je = 5.17 mA/um2, V

cb= 0.6 V

200

300

400

500

1 2 3 4 5 6

GH

z

Je (mA/um2)

ft

fmax

Vcb

= 0.6 V

10-12

10-10

10-8

10-6

10-4

0.01

0 0.2 0.4 0.6 0.8 1

I b, I

c (A

)

Vbe

(V)

VCB

= 0.3 V

Ic

Ib

nc = 1.17

nb = 1.38

0

1

2

3

4

5

6

7

0.0 0.5 1.0 1.5 2.0 2.5

J e (m

A/

m2 )

Vce

(V)

Ib step

= 85 uA

Peak ft, f

max

391 GHz f , 505 GHz fmax

Zach Griffith

setback

grad

e

base

emitt

er

InP

colle

ctor

Ccb/Ic ~0.5 ps/V

+V +V +V

0V

kz

Microstrip mode Substrate modes

+V

0VCPW mode

0V 0V

CPW has parasitic modes, coupling from poor ground plane integrity

kz

Microstrip has high via inductance, has mode coupling unless substrate is thin.

We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs

-V 0V +V

0VSlot mode

ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductanceground vias suppress microstrip mode, wafer thinning suppresses substrate modes

M. Urteaga, Z. Griffith, S. Krishnan

unitsdata

current steering

data emitter

followers

clock current steering

clock emitter

followerssize m2 0.5 x 3.5 0.5 x 4.5 0.5 x 4.5 0.5 x 5.5

currentdensity

mA/m2 6.9 4.4 4.4 4.4

Ccb/Ic psec / V 0.59 0.99 0.74 0.86

Vcb V 0.6 0 0.6 1.7

f GHz 301 260 301 280

fmax GHz 358 268 358 280

UCSB / RSC / GCS 150 GHz Static Frequency Dividers

-40

-30

-20

-10

0

10

20

0 20 40 60 80 100 120 140 160

Min

imu

m in

put

pow

er (

dBm

)

frequency (GHz)

IC design: Zach Griffith, UCSBHBT design: RSC / UCSB / GCSIC Process / Fabrication: GCSTest: UCSB / RSC / Mayo

-80

-70

-60

-50

-40

-30

74.9975 74.9987 75.0000 75.0012 75.0025

Out

put

Pow

er (

dB

m)

frequency (GHz)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00 19.00 38.00 57.00 76.00

Out

put

Pow

er (

dB

m)

frequency (GHz)

probe station chuck @ 25C

PDC,total = 659.8 mWdivider core without output buffer 594.7 mW

UCSB 142 GHz Master-Slave Latches (Static Frequency Dividers)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 15.0 30.0 45.0 60.0 75.0

Out

put

Pow

er (

dB

m)

frequency (GHz)

Static 2:1 divider:Standard digital benchmark.Master-slave latch with inverting feedback.Performance comparison between digital technologies

UCSB technology 2004:InP mesa HBT technology12-mask process600 nm emitter width142 GHz maximum clock.

Implications:

160 Gb/s fiber ICs

100 + Gb/s serial links

Target is 260 GHz clock rate at 300 nm scaling generation

Z. Griffith, M. Dahlström

25o C

Reducing Divide-by-2 Dissipation

ECL with impedance-matched 50 Ohm bus:25 Ohm load→ switch 12 mA 12 mA x 7 x 4 V = 336 mW/latch

CML with impedance-matched 50 Ohm bus:25 Ohm load→ switch 12 mA 12 mA x 3 x 3 V = 108 mW/latch

Low-Power CML100 Ohm loaded → switch 3 mA 3 mA x 3 x 3 V = 27 mW/latch

What parts of circuit are included in stated dissipation ?

12 mA12 mA 12 mA

50 Ohm bus 50 Ohm 50 Ohm

12 mA

50 Ohm bus 50 Ohm 50 Ohm

50 Ohm bus100 Ohm

3 mA

3 mA 3 mA

padcbwiring CC ,low ,low power low @ speed High

7.5 mW output power

Mesa DHBT Power Amplifiers for 100-200 GHz Communications

7 dB gain measured @ 175 GHz

175 GHz Power Amplifier Demonstrated in a 300 GHz fmax process500 GHz fmax DHBTs available now, 600 GHz should be feasible soon

→ feasibility of power amplifiers to 350 GHz→ Ultra high frequency communications

2 fingers x 0.8 um x 12 um, ~250 GHz f, 300 GHz fmax , Vbr ~ 7V, ~ 3 mA/um2 current density

V. Paidi, Z. Griffith, M. Dahlström

172 GHz Common-Base Power Amplifier

8.3 dBm saturated output power 4.5-dB associated power gain at 172 GHz DC bias: Ic=47 mA, Vcb=2.1V.

-10

-5

0

5

10

140 150 160 170 180 190

S2

1,S1

1,S2

2, dB

Frequency, GHz

S11

S22

S21

RLVin Vout

Input Matching Network Output Loadline Match

-10

-5

0

5

10

15

0

1

2

3

4

5

-15 -10 -5 0 5

Gai

n,

dB

, O

utpu

t P

ower

, dB

m

PA

E (%

)

Input Power, dBm

Gain

Output Power

PAE

V. Paidi, Z. Griffith, M. Dahlström

6 dB gain

176 GHz Two-Stage Amplifier

7-dB gain at 176 GHz8.1 dBm output power, 6.3 dB power gain at 176 GHz9.1 dBm saturated output power at 176 GHz

-10

-5

0

5

10

15

140 150 160 170 180 190 200

S2

1,

S1

1,

S2

2 d

B

Frequency, GHz

S21

S11

S22

0

2

4

6

8

10

0

1

2

3

4

5

-6 -4 -2 0 2 4 6 8 10

Gai

n, d

B, O

utpu

t Pow

er ,

dBm

PA

E (%

)

Input Power, dBm

PAEGain

Output Power

RLVoutVin

50 Ohms 50 Ohms

InputMatchingNetwork

OutputLoadlineMatchingNetwork

InputMatchingNetwork

OutputLoadlineMatchingNetwork

at f0

at f0

Veb,bias

Vcb,bias

V. Paidi, Z. Griffith, M. Dahlström

InP HBT limits to yield: non-planar process

Yield quickly degrades as emitters arescaled to submicron dimensions

base contact

liftoff failure:emitter-baseshort-circuit

S.I. substrate

base

sub collector

base contact

excessiveemitter undercut

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

planarization failure: interconnect breaks

Griffith, Dahlström

Parasitic Reduction for Improved InP HBT Bandwidth

SiO2 SiO2

P base

N+ subcollector

N-thick extrinsic base : low resistancethin intrinsic base: low transit time

wide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)

wide base contacts: low resistancenarrow collector junction: low capacitance

At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics

Much more fully developed in Si…

W

r

LR bulk

bulk

2ln

2

LrR c

contact 2

These are planar approximations toradial contacts:

extrinsic base

extrinsicemitter

N+ subcollector

extrinsic base

bulk

contactbulk

WLR

ln34.12

mintotal,

→ greatly reduced access resistance

UCSB/RSC/GCS TFAST HBT Technology Development

•High performance, low yield technology

•Difficult to scale to WE < 0.4 um

•Processed for epitaxy and circuit validation

Scaled mesa-HBT

S3 Technology

•Improved base-emitter process flow

•Process scalable to WE < 0.25 um

•Process modules that can be added to HBT technology

•Emitter regrowth for high yield, low Re

•Extrinsic base for low Rbb

•Pedestal implant for reduced Ccb

•Allows continued scaling even if base & emitter contact resistivities do not improve.

Regrowth Technology

S.I. InP

N+ Subcollector

N- collector

extrinsic basebase contact

regrown emitteremitter contact

SixNy

collectorcontact

intrinsic base

Low Parasitic, Scalable HBT processes

Collector pedestal implant

N- collector

N+ subcollector

S.I. substrate

collectorpedestal

Extrinsic emitter regrowthEmitter sidewall process

high-yield (10,000 transistor)alternative to emitter-base definition by mesa etch

SiGe-like emitter-base processwide emitter contact → low resistancethick extrinsic base → low resistance

Independent control of base contact & collector junction widths → reduced capacitance

15

20

25

30

35

0 1 2 3 4 5 6 7 8

Ccb

(fF

)

Je (mA/m2)

Aje = 0.5 x 7 m2

Vcb

= 0.3 V2.1 m collector pedestal

1.2 m collector pedestal

1.0 m collector pedestal

0

5

10

15

20

25

30

1 10 100 1000

IC=9.72 mA

VCE

=1.2 V

U,

MS

G/M

AG

, h 21

(dB

), K

Frequency (GHz)

U

h21MAG/MSG

K

fT=280 GHzf

MAX=148GHz

Emitter junction area: 0.3 x 4 m2

-2.00

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

18.00

0.00 0.50 1.00 1.50 2.00 2.50

Vce (V)

Ic (

mA

)

Miguel Urteaga

Dennis Scott, Yun Wei

RSC/GCS/UCSBVitesse similar to earlier Hitachi, NEC, NTT GaAs HBT processes

RSC/GCS/UCSBNorthrup Grumman

RSC/GCS/UCSBHRL Labs

Yingda Dong

Collector Pedestal Implant for InP HBTs

Pedestal can be integrated into: sidewall or mesa emitter processes, emitter regrowth process

0 1 2 3 4 5 6 7 815

20

25

30

35

AE=0.7 x 8 um2

1.0 um pedestal

1.2um pedestal

2.1um pedestal

CC

B (

fF)

JE (mA / um2)

~2:1 reduction in collector base capacitance

Good DC characteristics, high power density,increased breakdown: 5.4 V with a 90 nm thick collector

N++ InP subcollector

Collector contact

N+ pedestalBase contact

Emitter contact

SI substrate

N- collector UID InP

0

2

4

6

8

10

0 1 2 3 4 5 6

J e (

mA

/m

2)

Vce

(V)

Aje = 0.4 x 7 m2

Ib step = 500 A

HBT with pedestalHBT without pedestal

20 mW/m2 device failure

large collector capacitance reductionsignificant increase in breakdown2(1013) V-sec Johnson Figure-of-Merit transistors have low leakage, good DC characteristics

Y. Dong et. al.:ISDRC December 2003,DRC June 2004

What's next ? 250 nm Scaling Generation for >200 GHz clock

sidewall processes for 300 nm at high yield

narrow collector junctions needed low contact resistivity modified sidewall spacer process &/or collector pedestal

power density near reliability limits narrow emitters should improve heatsinking

Decreasing Acollector/Aemitter decreases required Je

eases thermal design

Indium Phosphide HBTs for 100-200 GHz ICsInP HBT: high speed & room left to scale 150 GHz digital clock (static divider) at 500 nm scaling generation 210 GHz clock should soon be feasible at 250 nm scaling. low NRE; low mask cost

Applications feasible soon: 160 Gb fiber ICs, 300 GHz MIMICs for communications & radar GHz mixed-signal ICs for radar & communications

Planar processes address yield limitations emitter-base junction: liftoff-free dielectric sidewall process base-collector junction: planar implanted process

Volume markets are needed to drive down cost GaAs HBT power amplifier processes are cheap Why can't InP HBT be inexpensive ? InP HBT can be scaled at high yieldKey to survival of the technology are emergence of singificant markets progress relative to CMOS & InP