High Speed Data Reception System (HSDRS) Indent · 2015-03-18 · Page 1 of 21 High Speed Data...

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High Speed Data Reception System (HSDRS) Indent

HSDRS is used for reception of high data rate telemetry and for processing of the same for data analysis. HSDRS indent consist of two parts namely PART-A & PART-B.

PART-A gives the detail description of the features required for the HSDRS. The table of

specifications has three columns in which first column is for parameters, second column for specification value and the third one for compliance. The Vendor needs to provide compliance statement for each of the specifications listed in the indent. Compliance should be indicated parameter wise and should not be restricted to just YES or NO. Detailed textual description for compliance should be mentioned with technical leaflets/brochures.

The Acceptance Test Plan, procedures and results must be supplied along with the equipment

delivery. The test cases to be conducted by vendor apart from the standard test procedures (as part of Factory Acceptance test) are provided in PART-B along with the test conditions. These test results should be provided prior to shipment of the product.

The vendor has to quote the price for the product in slabs of 2, 4, 5, 6, 8 and 10.

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PART-A

HIGH SPEED

DATA RECEPTION SYSTEM

(HSDRS)

SPECIFICATIONS

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SL No Table of Contents Page No

1 Introduction 4

2 Top Level Features/Specifications 4

3 Module Level Detailed Specifications 7

3.1 Data Reception 7

3.1.1 IF Receiver and Demodulator 7

3.1.2 Bit Synchronizer ,Frame Synchronizer and Data Processing 8

3.2 Data Simulator and Modulator 11

3.3 Time and Frequency Reference 15

4 General 15

5 Table: External inputs and Outputs 16

ANNEXURE-1 Terms and Conditions 17

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1. INTRODUCTION

High Speed Data Reception System (HSDRS) is meant for ground application and shall be used to

receive remote sensing payload data from the satellite, during ground testing of a satellite.

Feature Compliance HSDRS carries out three basic functions, namely,

1. Demodulation and Bit Synchronization

2. Frame Synchronization and Data Processing

3. Data Simulation and Modulation

The above functions shall be integrated in a single chassis.

It should be able to receive and process two IF chains. Each Receive chain shall consist of a demodulator, bit synchronizer, frame synchronizer and support further processing.

It should have one Transmitter IF chain comprising PCM simulator and a Data modulator.

In each receiving chain, it shall support BPSK, QPSK and 8PSK modulation schemes. For BPSK and QPSK, simultaneous reception on both chains shall be supported with a maximum of four data streams processing. For 8PSK, at least one chain shall support three data streams.

All functions including simulation shall be available simultaneously or independently.

Top level and block level detailed specifications are listed in the following chapters.

2. TOP LEVEL FEATURES / SPECIFICATIONS

Feature Compliance

1. Modules shall comply with CCSDS standards wherever applicable, and provision should exist to exclude/include CCSDS features.

2. HSDRS receives BPSK/QPSK/8PSK signal at 720 MHz Intermediate Frequency

3. Each receiving chain of HSDRS consists of a IF Demodulator, bit synchronizer, Viterbi decoder , Trellis Code Modulation(TCM) decoder, Differential decoder, Serializing I,Q,I+Q data, frame synchronizer, Reed-Solomon decoder, Low-Density-Parity-

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Check(LDPC) Decoder, depacketisation, Derandomiser as per CCSDS Standard (wherever applicable) and transfers the payload data to ground computer on Ethernet LAN.

4. Provision for Clock & data output for BPSK, I, Q, I+Q (Bit synchronizer outputs) for QPSK and three data streams output and clock for 8PSK shall be available.

5. Provision to feed data and clock as inputs to frame synchronizer for all channels.

6. A versatile simulator shall have functions like Data Generator, IF modulator (BPSK/QPSK/8PSK) including noise generator, CCSDS Convolutional encoder , Differential encoder , Frame Sync code addition, Randomizer , RS , LDPC and TCM encoding , CCSDS Packetisation. This simulator is to test the receiving chain of HSDRS and shall be compatible in all respects with the reception modules.

7. Provision to feed base band data I ,Q, C and Clock externally to the BPSK, QPSK and 8PSK modulator

8. Data simulator output (Data, Clock) that is going to modulator shall be available externally.

9. Provision for inclusion/exclusion online shall exist for all encoding/decoding schemes(RS, Convolutional, LDPC, TCM,differential), randomization, Derandomisation and Noise source and packetisation, depacketisation, matched filter and Digital Equalization Automatic Filter(DEAF)

10. Selectable bit rates for all data streams.

11. Provision for single and dual Viterbi decoders shall exist

12. Spectrum analysis: Display on front panel or transfer of spectral data to the computer system through Ethernet LAN. Spectrum monitoring and payload data processing shall be carried out simultaneously.

13. Vector Analysis data (Constellation viewing) display on front panel as well as on TCP/IP to remote clients shall be available

14. User Programmable matched filter and DEAF(Digital Equalization Automatic Filter)

15. HSDRS shall work with its own internal reference

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clock and provision for external 10 MHz reference input to be available.

16. Provision in HSDRS to receive time code generator signal for time stamping purpose.

17. HSDRS shall have local mode operation in addition to remote mode of operation through Ethernet LAN.

18. Ground computer controls HSDRS remotely through TCP/IP Ethernet LAN on one Gbps or more

19. HSDRS front panel display provides complete status information for Payload data processing & simulator modules.

20. Interface Circuitry, signal levels (safe operating range), Impedance and logic compatibility to be made available wherever the HSDRS is receiving external input or giving external output as the case may be.

21. Monitoring and Control in both Local and Remote mode of operation with local operation by keyboard/mouse

22. Product delivery shall describe in detail external input/output interface circuitry and safety issues like grounding & isolation and also driving capabilities

23. External base band Input and Output shall be made available as LVDS

24. The equipment should be industrial & EMC/EMI (IEC/EN 61326 standard or equivalent) proven and Certified, should withstand transport vibrations (to be supplied with appropriate metal/fiber-plastic container with wheels, container can be a third party item customized for the unit and shall be quoted separately) as it shall be transported to other facilities frequently.

25. External Inputs/Outputs shall be available on connectors as mentioned in Table-5

26. Real-Time Data Recording to Internal storage of 1 TB or more on a separate hard disk in addition to system disk

27. Playback of Recorded data ( file size shall be up to internal storage) through Test Modulator in single or loop back mode

28. HSDRS shall be 19 inch rack mountable and realized in a single chassis

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29. Automatic Phase ambiguity resolution

30. Differential encoding/decoding standard equations, user programmable

31. Configuration file management

3 MODULE LEVEL DETAILED SPECIFICATIONS

3.1 Data Reception

3.1.1 IF RECEIVER and DEMODULATOR

Functional Specifications:

Specifications

Parameter Specification Compliance

Input Frequency 720 MHz for two chains

Acquisition range Selectable up to+/- 1 MHz

VSWR <=1.4

Dynamic Range -10 dBm to –50 dBm

Acquisition Time < 300 msec

Demodulation modes BPSK/QPSK/8PSK Selectable Digital Filtering Filter Type FIR, symmetrical up to 60 taps,

programmable

Response Raised cosine, root raised cosine(programmable roll-off factor),Gaussian , User defined characteristics in ASCII file

Sync. Threshold Eb/No better than 3 dB PCM Data Rate Minimum Data Rate 10 Mbps for all

demodulations per chain

Maximum Data Rate as given below :

For BPSK Modulation: 200 Mbps (1X200Mbps) for each chain simultaneously

For QPSK Modulation: 400 Mbps (2X200Mbps) for each chain simultaneously

For 8PSK Modulation: 600 Mbps (3X200Mbps)for at least one chain

External Inputs For 720 MHz IF – 1 & IF-2 Connector : SMA(F) or N-Type-F Input Impedance : 50 Ohms

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Constellation & Spectrum Viewing

To be provided

Monitor (M) & Control (C)

1. Input Frequency(M,C)

2.Acquisition Range(M,C)

3. BPSK/QPSK/8PSK Demodulation Schemes (M,C)

4. Loop BW (M,C) 5 AGC data (M) 6. Input level (M)

7. Demodulator Lock Signal (M)

8. Eb/No (M)

9. IF Level (M)

10.IF input port selection(M,C)

3.1.2 BIT SYNCHRONISER, FRAME SYNCHRONISER AND DATA PROCESSSING

Functional Specifications:

Feature Compliance

1. Provision should exist for hard and soft decision for channel decoding

2. BER Evaluation 3. BER Evaluation for external base band input 4. Frame Locking using dedicated sync word by classical

locking phases of search, Check and Lock

5. Frame Synchronization and further channel decoding on individual data streams and on merged data also ( user selectable)

6. Time stamping at the start of the frame using internal reference

7. Frame Synchronized data should have header containing data quality information

8. Automatic PSK ambiguity resolution 9. CCSDS compliant decoding (Viterbi,RS,LDPC,TCM),

Derandomisation, ASM detection logic

10. Selectable derandomiser (seed word and polynomial programmability up to 16-bits, start offset up to 160 bits from the start of ASM) with enable/disable feature

11. CCSDS compliant CADU , VCDU 12. CCSDS compliant Packet Telemetry Processing 13. Simultaneous Real-Time Recording to internal storage

and real-time streaming on Ethernet for all data streams

�

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� Specifications

Parameter Specification

Compliance

PCM Input Codes NRZ (L, M, S) Selectable PCM bit rate 10 Mbps to 600 Mbps at Viterbi/RS/LDPC decoder

input ( bit synchronizer output) fully programmable with Bit Rate step size 100 bps BPSK(1 X 200) Mbps QPSK(2 X 200) Mbps 8PSK(3 X 200) Mbps

Acquisition Range ± 0.1 % of the symbol rate or better Differential decoder

a) As per equation given below for QPSK

b) Twenty three other possible equations

Sync. Threshold Eb/No better than 3 dB Bit sync Coasting Shall be able to hold lock for data containing 128 bits

(for NRZ type) of continuous zeros or ones.

PSK demod/Bit sync BER performance

<2 dB of theoretical curve

a) Phase ambiguity resolution

Automatic

b) Differential Decoding

Enable / Disable

Frame Sync. Pattern Length (ASM)

Default CCSDS version Up to 128 bits ( programmable)

Bit Slip Window(BSW)

0, +/- 1 bit Programmable

Frame sync Error Tolerance

0 to 15

Frame Sync strategy

Programmable

Check-To-Lock Threshold = 0 to 5 Lock-To-Search Threshold = 0 to 5 Frame length 16 to 1 Mega Bytes Time Stamping Corresponds to first bit of FS code;

Data decoding Derandomiser CCSDS version as default a) CCSDS Polynomial(CCSDS-131-0-B-2 Aug

2011) b) Programmability for seed word, length(7-15) ,

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start offset up to 160 bits Single, Dual Viterbi Decoding (CCSDS-131-0-B-2

Aug 2011)

Reed-Solomon Decoder (223,255) Decoding (CCSDS-131-0-B-2 Aug 2011)

LDPC code, CCSDS 131.1-O-1, September 2007/ CCSDS 131.0-B-2 Aug 2011).

• LDPC 1/2 Decoding (1024,2048) • LDPC 1/2 Decoding (4096,8192) • LDPC 7/8 Decoding (shortened (8160, 7136))

TCM (CCSDS 413.0-G-2) / CCSDS 401.0-B July 2011 Decoding

External Output Bit Sync Outputs: Both clock and Data after Viterbi,

differential decoding :

Data Format: NRZ-L Level : LVDS

Connector : As Specified in Table-5

Impedance: LVDS Standard Clock Polarity : Normal/Inverted Data Polarity: Normal/Inverted (I,Q) Swap : I/Q Data Output Interface

TCP/IP Ethernet LAN - Real-Time streaming

Data Output Format

Data formats shall be provided by the party and obtain clearance

Ethernet Ports Dual Gigabit Ethernet Ports External Input Frame Sync Inputs: Both clock and Data (LVDS)

Clock Polarity : Normal/Inverted selectable Data Polarity: Normal/Inverted (I,Q) selectable BER on PN Sequence

Monitor (M)& Control (C) 1. Bit rates (M,C)

2. PCM input codes (M,C) 3. Bit sync Lock status(M) 4. Loop BW (M,C) 5. Eb/No (M)

6. Frame Synchronizer Input Source (External/Internal)(M,C)

7 Data , Clock Polarity Selection(M,C) 8. Frame Sync Lock Status : (M)

9. Lock Status (Viterbi, RS): (M) 10. Quality byte indicating F.S errors(M) 11. RS Decoding Include/Exclude (M,C)

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12 RS Decoding Error status(M) 13 BER Display for RS,LDPC,TCM,Viterbi Decoder(M)

14.Viterbi decoding include/exclude(M,C) 15 Viterbi decoding Error status(M) 16 Viterbi decoding selection(M,C)

17. Differential Decoding Include/Exclude (M,C) 18 Differential decoding equations (M,C)

19. Derandomisation Include/exclude ( M,C) 20. Derandomisation Polynomial selection ( M,C) 21. Derandomisation Offset selection ( M,C) 22. LDPC decoding include/exclude(M,C) 23 LDPC Code selection(M,C) 24 LDPC Decoding Error status(M) 25 Frame sync length (M,C) 26 Frame sync code (M,C) 27 Frame length (M,C) 28 Bit slip (M,C) 29 Frame Sync Strategy-CTL(M,C) 30 Frame Sync Strategy-LTS(M,C) 31 Frame Sync Code Error Allowance(M,C) 32 Frame Drop Counter in real-time (M) 33. TCM Decoding include/exclude(M,C) 34. TCM Code Selection (M,C)

3.2 DATA SIMULATOR AND MODULATOR Functional Specifications:

The data simulator and modulator module shall provide the necessary features to test all the functions of the HSDRS and shall support the following functions.

Feature Compliance

1. Data generation with bit rate Programmability 2. PCM generation using PRN sequence or stored

data file single or loop back from internal storage ( minimum of 1 TB)

3. Payload Data file (in Binary/ASCII Format with File Size limited to internal storage) upload facility from an external computer for simulation

4. Encoding for LDPC, TCM , Convolution compatible with CCSDS standards

5. Encoding for RS compatible with CCSDS standards

6. Randomizer 7. Differential encoding

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8. BPSK/QPSK/8PSK modulated signal output with level control

9. Shall accept external base band simulation signal (I,Q,C,I+Q,Clk) for BPSK/QPSK/8PSK modulation

10. Internal noise generator with Include /Exclude feature

11. Provision to operate PSK modulator with or without external clock input for the external data input

Specifications

Parameter Specification Compliance Analog signal output level

PCM-BPSK/QPSK/8PSK :

-10 dBm to -50dBm(Carrier) selectable in steps of 1 dB

Output Frequency 720 MHz +/- 10 MHz

Selectable centre frequency in steps of 100 Hz or better

Output stability over a day/temp range.

+/- 0.5 dB. for 10 deg C to 30 deg C

VSWR <1.4

Phase Noise -100 dBc/Hz at 1 KHz

Spurious < - 50 dBc

Bit rate Minimum Data Rate 10 Mbps for all modulations

Maximum Data Rate (Mbps) as given below :

200 Mbps(1X200 ) for BPSK, 400Mbps(2X200) for QPSK, 600Mbps(3X200) for 8PSK

PCM code for Ext data output after Channel coding

NRZ(L,M,S)

PCM sequence type

PRN (7,11, 15, 23 ), 101010…. patterns, or stored frame/file

External Data and Clock input for BER measurement

Modulation Type PCM/BPSK, PCM/QPSK, PCM/8PSK

Modulator Amplitude imbalance

< 0.5 dB

Modulator Phase imbalance

< 3 deg

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Carrier suppression (with modulation)

30 dB minimum

BER Measurement

1) Automatic delay adjustment between transmitting and received signal

2) Bit to bit comparison between transmitted and received signal

BER Measuring range

10-3 to 10 -12 and totalizer

TM Data Programmability (Frames)

Frame Sync Pattern Length: up to 128 bits

Word Length : 8 bits

Frame Size: 16 to 1 Mega bytes

Differential Encoding

Programmable algorithms matching with data reception chain:

a)As per equation given below for QPSK

b)Twenty three other possible equations

Data Encoding Randomizer CCSDS version as default a) CCSDS Polynomial(CCSDS-131-0-B-2

Aug 2011) b) Programmability for seed word, length(7-

15) and start offset up to 160 bits

Single, Dual Viterbi Encoding (CCSDS-131-0-B-2 Aug 2011)

Reed-Solomon Encoder (223,255) Encoding (CCSDS-131-0-B-2 Aug 2011)

LDPC code, CCSDS 131.1-O-1, Sept 2007/ CCSDS 131.0-B-2 Aug 2011).

• LDPC 1/2 Encoding (1024,2048) • LDPC 1/2 Encoding (4096,8192) • LDPC 7/8 Encoding (shortened (8160,

7136))

TCM (CCSDS 413.0-G-2) Encoding/ CCSDS 401.0-B July 2011

External Input

Modulator Inputs: Both clock and Data

Data Format: NRZ-L

Level : LVDS


Impedance: LVDS Standard

External Outputs For 720 MHz IF – 1 & IF-2 Connector : SMA(F) or N-Type(F) Output Impedance : 50 Ohms

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PCM Output: after ASM addition, Coding and randomization ;Both clock and Data

Data Format: NRZ-L

Level : LVDS


Impedance: LVDS Standard

Monitor(M)& Control (C)

1. Modulator Output level (M,C)

2. Modulation ON/OFF (M,C)

3. Carrier ON/OFF (M, C)

4. Bit rate (M,C)

5. PCM code (M,C)

6. PRN sequence (M,C)

7. Noise source Include/exclude (M,C)

8. Noise source level selection ( M,C)

9 External Clock Include/Bypass (M,C)

10 Carrier Frequency Selection (M,C)

11 Modulation Schemes(M,C)

12 Data generator File Input Selection (M,C)

13 Playback File Selection (M,C)

14 Modulator I/P Source (External/Internal)(M,C)

15. RS coding Include/Exclude (M,C)

16 RS Code selection(M,C)

17.Convolution encoding include/exclude(M,C)

18 Convolution encoding selection(M,C)

19. Differential encoding Include/Exclude (M,C)

20 Differential encoding equations (M,C)

21. Randomization Include/exclude ( M,C)

22. Randomization Polynomial selection ( M,C)

23. Randomization Offset selection ( M,C)

24. LDPC encoding include/exclude(M,C)

25 LDPC Code selection(M,C)

26 Frame length (M,C)

27 Frame sync code length (M,C)

27 TCM Coding Include/Exclude (M,C)

28 TCM Code Selection (M,C)

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3.3 TIME AND FREQUENCY REFERENCE

External Time and Frequency Reference Input Specifications

Parameter Specification Compliance Input Frequency 10 MHz

Input Level for Frequency Reference

1V pp to 5 V pp

Physical Interface SMA-F

Impedance 50 ohms

VSWR <1.3

Input Time Code IRIG-B

Time tag capacity Yes

Monitor (M) and Control (C) Time (M)

Time decoder Lock status ( M)

Reference Frequency Lock status (M)

4. GENERAL

Parameter Specification Compliance Power 230 V + /- 10%, 50 Hz +/- 2Hz, single phase

Power Cord Connector

3-Pin Plug as per current Indian standards (BS-546 Standard)

Dimension 19” Standard Rack mountable, Maximum 5 U Size, Maximum Depth 600mm

Operating temperature

10 to 40 deg C, Max. Humidity 80%

Storage temperature -20 to 60 deg c

Associated Deliverables

Operation & Maintenance Manual, Programmer manual, Acceptance Test Procedure, Acceptance Test Results (in English) hard copy and soft copies one set for each equipment

Installation CD/DVD Kit, one set for each equipment

Delivery of front end software for remote monitoring and control and also for remote data acquisition and application protocol interface details for programming remote clients.

All related utility softwares

Accessories to be supplied • Power Cord • Interconnecting cables and adapters

wherever applicable

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5. TABLE: EXTERNAL INPUTS AND OUTPUTS:

SL

NO

Input/

Output

Description Connector Compliance

1 Input IF input to HSDRS ( 720 MHz ) for Chain1 SMA-F or

N-Type(F)

2 Output Bit sync output after viterbi,differential decode—I for Chain1

LVDS

Interface

On SMA-F

or D-Type

connectors

3 Output Bit sync output after viterbi,differential decode—Q for Chain1

4 Output Bit sync output after viterbi,differential decode—I+Q or C for Chain1

5 Output Bit sync output after viterbi,differential decode—I Clock for Chain1

6 Output Bit sync output after viterbi,differential decode—Q Clock for Chain1

7 Output Bit sync output after viterbi,differential decode—I+Q Clock or C Clock

for Chain1

8 Input Data for Frame/RS decoder input --- I for Chain1

LVDS

Interface

On SMA-F

or D-Type

connectors

9 Input Data for Frame/RS decoder input --- Q for Chain1

10 Input Data for Frame/RS decoder input --- I+Q or C for Chain1

11 Input Clock for Frame/RS decoder input --- I Clock for Chain1

12 Input Clock for Frame/RS decoder input --- Q Clock for Chain1

13 Input Clock for Frame/RS decoder input --- I+Q Clock or C Clock for Chain1

14 Input IF input to HSDRS ( 720 MHz ) for Chain2 SMA-F or

N-Type(F)

15 Output Bit sync output after viterbi,differential decode—I for Chain2

LVDS

Interface

On SMA-F

or D-Type

connectors

16 Output Bit sync output after viterbi,differential decode—Q for Chain2

17 Output Bit sync output after viterbi,differential decode—I+Q or C for Chain2

18 Output Bit sync output after viterbi,differential decode—I Clock for Chain2

19 Output Bit sync output after viterbi,differential decode—Q Clock for Chain2

20 Output Bit sync output after viterbi,differential decode—I+Q Clock or C Clock

for Chain2

21 Input Data for Frame/RS decoder input --- I for Chain2 LVDS

Interface

On SMA-F

or D-Type

connectors

22 Input Data for Frame/RS decoder input --- Q for Chain2

23 Input Data for Frame/RS decoder input --- I+Q or C for Chain2

24 Input Clock for Frame/RS decoder input --- I Clock for Chain2

25 Input Clock for Frame/RS decoder input --- Q Clock for Chain2

26 Input Clock for Frame/RS decoder input --- I+Q Clock or C Clock for Chain2

27 Output IF Output from HSDRS ( 720 MHz) SMA-F OR

N-Type(F)

28 Input Data input to PSK Modulator --- I

LVDS

Interface

On SMA-F

or D-Type

connectors

29 Input Data input to PSK Modulator --- Q

30 Input Data input to PSK Modulator --- C or I+Q

31 Input Clock input to PSK Modulator

32 Output Data Simulator Output ---I

LVDS

Interface

On SMA-F

or D-Type

connectors

33 Output Data Simulator Output ---Q

34 Output Data Simulator Output ---C or I+Q

35 Output Data Simulator Clock output

36 Input Frequency reference Input (10 MHz) SMA-F

37 Input Time Reference Input ( IRIG) SMA-F

38 I/O Giga Bit Ethernet TCP/IP LAN Port-1 RJ45

39 I/O Giga Bit Ethernet TCP/IP LAN Port-2 RJ45

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ANNEXURE-1 TERMS AND CONDITIONS

Features Compliance 1. Vendor should mention list of users currently using similar equipment (Indian/International)

2. Only original manufacturer or their authorized agents/Distributors/Dealers should submit quotation. If the quotation is from authorized Agent/Distributors/Dealers, they should submit Letter of Authorization to that effect along with quotation.

3. The Acceptance Test Plan, procedures and results must be supplied along with the equipment delivery

4. Quotations without technical compliance matrix (point-to-point) will not be considered

5. Quotations without detailed data sheets/catalogues will not be considered

6. Compliance should be indicated parameter wise and should not be restricted to just YES or NO. Detailed textual description for compliance should be mentioned with technical leaflets/brochures

7. Vendor should demonstrate the features as part of technical evaluation if required, at ISAC

8. Equipment installation and training to be provided as part of Acceptance tests

9. List of spares to be identified

10. Support, Service and up gradation to be available for up to 10 years in India

11. Three years warranty is required

12. Extended warranty up to 5 years to be quoted

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PART-B

� The vendor is required to carry out the test cases in Annexure 2 .These test results

along with the factory acceptance test results should be provided prior to the

shipment of the product.

� The test results should have the measured values and the plots

(Spectrum/Constellation) wherever applicable.

� All the I/O ports available at the front/ rear panel to be properly labeled.

� The physical inspection report for Hardware configuration to be provided.

� The modulator test results should include the screenshots of the plots captured on

the Spectrum Analyzer inside the HSDR unit and the phase noise plots.

� The Monitor and Control features in the product to be tested remotely and the

Screen shots for the same to be provided.

� The Skew between Bit Synchronizer Output and Frame Synchronizer Input to be

tested and test result to be provided.

� The following parameters of Data simulator and Modulator to be tested for

indented specifications and the results to be included.

� Analog signal output level

� Output Frequency

� Output stability over a day/temp range.

� VSWR

� Phase Noise

� Spurious including Close-in Spurious

� PCM sequence type

� Modulator Amplitude imbalance

� Modulator Phase imbalance

� Carrier suppression

� BER Measuring range

� TM Data Programmability

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Annexure: 2: Test Cases for HSDRS

Case 1: a) Data for Modulator : From External source with clock (with and without merged data)

Data rate : Highest Data Rate Coding : RS (223,255) Digital Filtering : Raised Cosine Hard/Soft Decision : Hard Decision Decoding Differential Encoding : The default equation provided in the specifications Randomization : Include (default CCSDS) Modulation : QPSK Power Level :-50dBm

b) Data for Modulator : From External source without clock (with and without merged data)

Data rate : Highest Data Rate Coding : RS (223,255) Digital Filtering : Programmed coefficients Hard/Soft Decision : Soft Decision Decoding Differential Encoding : The default equation provided in the specifications Randomization : Include (default CCSDS) Modulation : QPSK Power Level :-50dBm

c) Data for Modulator : From External source without clock

Data rate : Lowest Data Rate Coding : RS (223,255) Differential Encoding : The default equation provided in the specifications Randomization : Include (default CCSDS) Modulation : QPSK Power Level :-50dBm

d) Data for Modulator : From External source with clock

Data rate : lowest Data Rate Coding : RS (223,255) Differential Encoding : The default equation provided in the specifications Randomization : Include (default CCSDS) Modulation : QPSK Power Level :-50dBm CCDS Packet Processing : Include

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Case 2: a) Data for Modulator : From External Source with clock

Data rate : Highest Data Rate Coding : RS (255,239) Randomization : Include (default CCSDS) Modulation : 8 PSK Power Level :-50dBm

b) Data for Modulator : From External Source without clock

Data rate : Highest Data Rate Coding : RS (255,239) Randomization : Include (default CCSDS) Modulation : 8 PSK Power Level :-50dBm

Case 3:

a) Data for Modulator : Internal File

Data rate : Highest Data Rate Coding : RS (255,239) +TCM (2) Randomization : With a selected seed word of length 10 and start

offset of 80 bits Modulation : 8 PSK Power Level :-50dBm

b) Data for Modulator : Internal File

Data rate : Highest Data Rate Coding : RS (255,239) +TCM (2.5) Randomization : With a selected seed word of length 10 and start offset

of 80 bits Modulation : 8 PSK Power Level :-50dBm

c) Data for Modulator : Internal File

Data rate : Highest Data Rate Coding : RS (255,239) +TCM (2.75) Randomization : With a selected seed word of length 10 and start

offset of 80 bits Modulation : 8 PSK Power Level :-50dBm

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Case 4:

a) Data for Modulator : From External Source with clock

Data rate : Highest Data Rate Coding : LDPC ½ encoding (1024, 2048) Differential Encoding : Any of the twenty three equations Randomization : Exclude Modulation : QPSK Power Level :-50dBm

b) Data for Modulator : From External Source with clock

Data rate : Highest Data Rate Coding : LDPC ½ encoding (4096, 8192) Differential Encoding : Any of the twenty three equations Randomization : Exclude Modulation : QPSK Power Level :-50dBm

c) Data for Modulator : From External Source with clock

Data rate : Highest Data Rate Coding : LDPC 7/8 encoding (8160, 7136) Differential Encoding : Any of the twenty three equations Randomization : Exclude Modulation : QPSK Power Level :-50dBm

Case 5:

a) Data for Modulator : From External Source with clock

Data rate : Highest Data Rate Coding : LDPC ½ encoding (1024, 2048) Randomization : Exclude Modulation : 8-PSK Power Level :-50dBm

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