HDLC Driver development - functions.pdf

8/11/2019 HDLC Driver development - functions.pdf

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Name Description Status Issue Test

apm_hdlc_init

_ get all HDLC configuration relatedparameters from insmod comand.

_ pass these parameters toapm_hdlc_run function.

apm_hdlc_run

_ call Keelback's low-level intializingfunctions with parameters fromapm_hdlc_init function.

_ allocation memory for hdlc netdevice.

_ request interrupt for hdlc net device.

_ initializing each members ofapm_hdlc struct.

_ register hdlc net device with LinuxKernel.

apm_hdlc_exit _ unregiste hdlc net device

apm_hdlc_ioctl_ issue Keelback's device-specificcommands.

apm_hdlc_xmit_ called by generic HDLC layer to sendframe

apm_hdlc_attach

_ called by generic HDLC layer whenprotocol selected (PPP, frame relay, ..)set endconding and frame checksequence (FCS) options.

apm_hdlc_intr

_ Keelback's HDLC interrupr handler.

_ the function is called eachtime there

is an interrupt on the port, it will check ifit is a Tx or Rx interrup and call therespected interrupt handler.

apm_hdlc_set_carri_ Change Link State.


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Comment Code


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apm_hdlc_open

_ called by generic network driver

_ call hdlc_open to open the HDLCdevice

_ call apm_hdlc_set_carrier to anounce

link state change to Linux Kernel.

_ call netif_start_queue to start HDLCinterface's transmit queue.

apm_hdlc_close

_ reset HDLC channel.

_ disable HDLC related interrupts.

_ call netif_stop_queue to mark the

device as being unable to transmit anymore packets.

_ call hdlc_close to announce HDLCdevice is being closed.

Keelback's low-level initializing functions

TDM Interface

Config

Choosing the order of transmission onthe TDM interface by setting theBitOrder bit in Configuration Register 2.By default, data on the TDM interface

is transmitted least significant bit first.

Time Slot AssignerConfig

setting or clearing the TSEnb bit in theTime Slot Assigner Table for each 128timeslots.

Ready to SendConfig

RTSEnb = 0: the hdlc_rts_n signal isalways assertedRTSEnb = 1: the hdlc_rts_n signal isasserted during the frame transmissionand deassered between frames.

TTdmEdge: indicate which hdlc_txclkclock edge the hdlc_rts_n signal isasserted and deasserted.


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Clear to SendConfig

Clear to Send operation is controlled bythe CTSEnb, and CTSMode bits inConfiguration Register 1.++ When CTSEnb = 0, the HDLC-AHBcore transmit frames regardless of thestate of hdlc_cts_i.

++ When CTSEnb = 1, the valueassigned to hdlc_cts_i depends on thevalue of CTSMode.++ When CTSMode = 0, hdlc_cts_i isset to the signal hdlc_cts_n.++ When CTSMode = 1, hdlc_cts_i isgenerated internally.+ The CTSLMode bit in ConfigurationRegister 1 controls the operation when

hdlc_cts_i is deasserted.++ The HDLC-AHB Core waits forhdlc_cts_i to be asserted to transmit aframe.++ If CTSLMode = 0, the transmissioncontinues even if the hdlc_cts_i isdeasserted.++ If CTSLMode = 1, the transmissonstops when hdlc_cts_i is sampled highand the CTSLost interrupt is asserted.


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HDLC ReceiveSection

_The bit destuffing mode is selected bysetting the CfgRxStuffMode bit to 0

_The byte destuffing mode is selectedby setting the CfgRxStuffMode bit to 1

_ CRC checking is enabled byasserting the CfgRxCRCEnbconfiguration bit. The CRC circuit(CRC16 or CRC32) is selected via theCfgRxCRCLength bit.

HDLC TransmitSection

_ The bit stuffing mode is selected bysetting the CfgTxStuffMode bit to 0.

_ The byte stuffing mode is selected by

setting the CfgTxStuffMode bit to 1._ CRC insertion is enabled byasserting the TxConfig.CRCEnbconfiguration bit. The CRC circuit(CRC16 or CRC32) is seleted via theTxConfig.CRCLength bit. NOTE: whenCRC insertion is disabled (TxConfig.CRCEnb = 0), the CRC is provided withthe packet over the FIFO interface.

AddressComparisonConfig

_ The least significant byte of theHDLC Receive Header Data Registersis programmed with the first byte of theexpected address (i.e., the bytefollowing the opening flag). The mostsignificant byte of the HDLC ReceiveHeader Data Registers is programmedwith the second byte of the expectedaddress.

FrameRetransmissionConfig enable by setting RetransEnb bit


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Transmit FrameOperation

_ Host CPU divides frame intosegments with each segment writteninto a separate buffer in system RAM.

_ The Host CPU then writes adescriptor for each segment into the Tx

Dsc FIFO. The descriptor consists ofthe address of the buffer in systemRAM, the segment length, andindications that the segment is theframe's first or last segment.

Receive FrameOperation

_ Prior to enabling the receiver, thehost CPU must supply free bufferpointers by writing them in the ReceivePointer FIFO


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HDLC Driver development - functions.pdf

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