HBM2.0 PHY and Controller - guc-asic.com · 2018Q1 HBM2.0 PHY and Controller Overview GUC‘s HBM...
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www.guc-asic.com 2018Q1 HBM2.0 PHY and Controller Overview GUC‘s HBM IP is fully compliant with JEDEC JESD235B HBM specification and together with GUC’s 2.5D package design service offer customers total system-in-chip solution. The IP supports 2D / 4D / 8D memory stack height options allowing system architect flexibility to address big data applications such as Networking and Supercomputer. The PHY features auto training / calibration and read/write DQ maximum eye margin, etc. Memory Controller HBM PHY IP (MLB RTL Modual) Miscellaneous Logic Block (MLB) HBM PHY IP Hard Macro Loopback Test Mode I/O PAD PHY Register DLL Training Logic PHY Register Settings HBM DRAM Interface DFI Interface DFT (JTAG) System I2C PHY Internal Interface PLL Memory Controller HBM DRAM
Transcript of HBM2.0 PHY and Controller - guc-asic.com · 2018Q1 HBM2.0 PHY and Controller Overview GUC‘s HBM...
www.guc-asic.com2018Q1
HBM2.0 PHY and Controller
Overview
GUC‘s HBM IP is fully compliant with JEDEC JESD235B HBM specification and together with GUC’s 2.5D package design service
offer customers total system-in-chip solution.
The IP supports 2D / 4D / 8D memory stack height options allowing system architect flexibility to address big data applications
such as Networking and Supercomputer. The PHY features auto training / calibration and read/write DQ maximum eye margin,
etc.
MemoryController
HBM PHY IP(MLB RTL Modual)
Miscellaneous LogicBlock (MLB)
HBM PHY IPHard Macro
Loopback Test Mode
I/OPAD
PHY Register
DLL
Training Logic
PHYRegisterSettings
HBM DRAMInterface
DFI Interface
DFT(JTAG)
System
I2C
PH
Y Internal
Interface
PLL
MemoryController
HBM DRAM
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www.guc-asic.com
2018Q1
HBM2.0 PHY Key Features
Support TSMC 16FFPGL, 16FFC and 7FF
Support 2.4Gbps / pin for 7FF
Complete HBM PHY delivered as a hard macro
component ( includes I / O, PLL, and DLL )
DFI compliant interface
Support multiple output driving capacities ( 1.5mA,
3mA, 4.5mA, 6mA, 9mA, 12mA, 15mA and 18mA )
Automatic READ / WRITE eye training
No READ leveling training needed
HBM lane repair with redundant pin for row / column / data
Support IEEE1500 interface and LFSR / MISR
Internal loopback
Low-power mode
Provide IO pass through mode
Comply with HBM DRAM standard ( JEDEC JESD-235B )
HBM2.0 Controller Key Features
High Bandwidth Memory ( HBM2 ) DRAM controller,
Comply with JESD235B
Support 8 channels or 16 pseudo channels
Support 8H SDRAM stack
Supports one AXI4.0 port
Supports DQ/AC bus parity
Supports DBI, DM, and ECC
Supports single bank refresh
Supports self-refresh
Supports programmable mapping from AXI address
to bank group, bank, row, and column
Supports AXI read interleaving
Supports QoS
Supports BIST
HBM2.0 IP Portfolio
IP NAME FEATURE PROCESS STATUS
HBM2.0 PHY 2.8Gbps CLN7FF 2019 / Q2
HBM2.0 PHY 2.4Gbps CLN7FF 2018 / Q3
HBM2.0 PHY 2.0Gbps CLN16FFC Silicon Proven
HBM2.0 PHY 2.0Gbps CLN16FF+GL Silicon Proven
HBM2.0 CTRL 2.8Gbps Digital 2019 / Q2
HBM2.0 CTRL 2.4Gbps Digital Silicon Proven
