GaN Transistors for Efficient Power Conversion · 2016. 1. 10. · Reference: Texas Instruments,...

www.epc-co.com 1 EPC - The Leader in GaN Technology | September , 2014 |

GaN Transistors for Efficient Power Conversion

Alex Lidow

and David Reusch

Efficient Power Conversion


Agenda

• How GaN works and the state-of-the-art

• Design Basics

• Design Examples

• What is in the future?


How GaN Works and the

State-of-the-Art


Power Switch Wish List

• Lower On-Resistance

• Faster

• Less Capacitance

• Smaller

• Lower Cost


Material Comparison


State of the Art

Theoretical on-resistance vs. blocking voltage capability for silicon, silicon carbide, and gallium nitride.


GaN Switch

AlGaN

GaN

V


GaN Switch

AlGaN

GaN

V

Now we have a switch That has high voltage blocking

capability, low on resistance, and is

very, very fast.

Depletion Mode = Normally On


Device Construction Concept

GaN

Silicon

Protection Dielectric

Drain Source

Gate AlGaN


What about “Normally Off” devices?


Cascode GaN Device

Reference: “The Status of GaN Power Device Development at International Rectifier,” PCIM 2012


Cascode Penalty

Gate

Source

Drain

Cascode devices combine a depletion mode GaN transistor with a low voltage enhancement mode MOSFET

GaN Improves

Si Improves


Enhancement Mode

A positive voltage from Gate-To-Source establishes an electron gas under the gate


A positive voltage from Gate-To-Drain also establishes an electron gas under the gate

Body Diode?


Cross Section of an eGaN® FET


Electrical Characteristics


MOSFET

+ QRR

eGaN FET

+ Zero QRR

eGaN FET Reverse Conduction


On Resistance vs. Temperature

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

-50 -25 0 25 50 75 100 125 150

Nor

mal

ized

On

Res

ista

nce

Junction Temperature (°C)

GaN

MOSFET B

About 20%

Difference At 125 °C

eGaN FET


Threshold vs. Temperature

0.6

0.7

0.8

0.9

1

1.1

1.2

-50 -25 0 25 50 75 100 125 150

Nor

mal

ized

The

rsho

ld V

olta

ge

Junction Temperature (°C)

GaN

MOSFET A

eGaN FET


eGaN FET Transfer Characteristics

EPC2001


MOSFET Transfer Characteristics

Source: www.infineon.com

Negative temperature coefficient region of silicon MOSFET


eGaN FET Safe Operating Area

22

1 ms

10 ms

100 ms

DC


eGaN FET Safe Operating Area

23

1 ms

10 ms

100 ms

DC


eGaN FET Capacitances

GaN

Silicon

CGD

CDS

CGS


Total Gate Charge

EPC2001 = 100 V, 5.6 mΩ typ.

BSC057N08 = 80 V, 4.7 mΩ typ.

BSC057N08NS


VIN=48 V VOUT=1 V IOUT=10 A fsw=300 kHz L=10 µH eGaN FET T/SR: 100 V EPC2001

MOSFET T/SR: 80 V BSZ123N08NS3G

10 V/ div 20 ns/ div

80 V

Si MOSFET

10.3 mΩ 100 V

eGaN FET

5.6 mΩ

Switching Comparison


0

1

2

3

4

5

6

0 20 40 60 80 100 120

RD

S(o

n) (m

Ω)

Drain-to-Source Voltage (V)

GaN Improvements

VGS=5 V

Generation 2

2011

Generation 4

2014

2.3x

2.6x


0

10

20

30

40

50

60

70

80

90

100

0 50 100 150 200 250

FO

M=

QG·R

DS

(on

) (p

C·Ω

)


Gate Charge FOM

1.4x

1.4x

1.4x

Generation 2

2011

Generation 4

2014

28


Gate Charge Figure of Merit

0

100

200

300

400

500

600

0 50 100 150 200 250

FO

M=

QG·R

DS

(on

) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

Vendor C

Vendor D

Vendor E

9.9x

1.3x

4.2x


0

5

10

15

20

25

30

35

40

45

50

0 50 100 150 200 250

FO

MH

S=

(QG

D+

QG

S2)·

RD

S(o

n) (p

C·Ω

)


VDS=0.5·VDSS, IDS=20 A

Hard Switching FOM

1.4x

2.4x

2.4x

Generation 2

2011

Generation 4

2014

30


1

10

100

0 50 100 150 200 250

FO

MH

S=

(QG

D+

QG

S2)·

RD

S(o

n) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

Vendor C

Vendor D

Vendor E

GaN Transistors

2014

GaN Transistors

2011

Si MOSFETs

2014


Hard Switching FOM

5x

4.8x

8x

31


Miller Ratio


0

0.5

1

1.5

2

2.5

0 50 100 150 200 250

Mil

ler

Rati

o=

QG

D/Q

GS

1


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

Vendor C

Vendor D

Vendor E

2.5x

2.5x

2x


Soft-Switching Figure of Merit

VDS=0.5·VDSS

0

500

1000

1500

2000

2500

0 50 100 150 200 250

FO

MS

S=

(QG+

QO

SS)·

RD

S(o

n) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

3.2x

2.5x 2.4x


eGaN FET Loss Mechanisms

Like A MOSFET

• I²R Conduction Loss

• Capacitive Switching Losses

• Gate Drive Losses

• V×I Switching Loss

Not Like A MOSFET

• High Reverse Conduction Loss

• No Body Diode Reverse Recovery Loss

Can be much, much better than comparable silicon MOSFET


Package Wish List

• Low parasitic resistance

• Low parasitic inductance

• Low thermal resistance

• Small size

• Low cost


Flip-Chip LGA Construction

Printed Circuit Board

Copper Trace

eGaN FET Silicon Solder

Bar

Absolute minimum lead resistance and inductance!


Gate

Substrate

Source Contacts

LGA Construction

Drain Contacts Interleaving to reduce layout

inductance


Size Comparison – 200 V

D-PAK

eGaN FET

Drawn To Scale

5.76 mm²

65.3 mm²


Design Basics


Design Basics Agenda

• Requirements for: – Gate Driver – Dead-time – Layout – Paralleling – Thermal – Measurement


Gate Drive


Low VGS(on) Overhead

VGS(Max) = 6 V


VGS eGaN FET

Minimizing Overshoot

80 ns/ div 2 V/ div


eGaN FET Drive Requirements

• Minimize gate loop inductance

• Separate source and sink transistors allowing

for separate drive paths

To avoid overshoot:

GS

SGG

C

LLR

)(4

LS

RG(INT)

CGS

LGR

G(EXT)

RG

= RG(INT)

+ RG(EXT)


VGS eGaN FET VGS eGaN FET

Minimizing Overshoot

20 ns/ div 1 V/ div


eGaN FET Driver IC

• Bootstrap clamp limits (HS) supply

Reference: Texas Instruments, “Gate Drivers for Enhancement Mode GaN Power FETs 100 V Half-Bridge and

Low-Side Drivers Enable Greater Efficiency, Power Density, and Simplicity,” SNVB001

• Optimized drive impedance

• Separate inputs allow accurate, dead-time management


Dead-time Requirements


TDead

Cin

T

SR

Reverse Conduction Period

VGS_T

V VSW

t

VGS_SR

VSW


MOSFET

eGaN FET

eGaN FET Reverse Conduction

+ Zero QRR

+ QRR


TDead

VGS_T

V VSW

t

VGS_SR

Cin

T

SR

VSW

Reverse Conduction Period


0

0.2

0.4

0.6

0.8

1

1.2

1.4

-5 0 5 10 15

Dead

-tim

e L

oss (

W)

Dead-Time (ns)

eGaN FET

Si MOSFET

w/o QRR

Impact of Dead-time

0

0.2

0.4

0.6

0.8

1

1.2

1.4

-5 0 5 10 15

Dead

-tim

e L

oss (

W)

Dead-Time (ns)

eGaN FET

Si MOSFET

w/o QRR

eGaN FET w/Schottky

VIN =12 V, VOUT =1.2 V, IOUT=20 A, and fsw =1 MHz


82

83

84

85

86

87

88

89

90

2 4 6 8 10 12 14 16 18 20 22 24 26 28

Eff

icie

ncy (

%)

Output Current (A)

eGaN FET

TDEAD ≈ 2.5 ns

Si MOSFET

TDEAD ≈ 2.5 ns

w/o Schottky

82

83

84

85

86

87

88

89

90

2 4 6 8 10 12 14 16 18 20 22 24 26 28

Eff

icie

ncy (

%)

Output Current (A)

eGaN FET

TDEAD ≈ 2.5 ns

eGaN FET

TDEAD ≈ 5 ns

Si MOSFET

TDEAD ≈ 2.5 ns

w/o Schottky

82

83

84

85

86

87

88

89

90

2 4 6 8 10 12 14 16 18 20 22 24 26 28

Eff

icie

ncy (

%)

Output Current (A)

eGaN FET

TDEAD ≈ 2.5 ns

eGaN FET

TDEAD ≈ 10 ns

eGaN FET

TDEAD ≈ 5 ns

Si MOSFET

TDEAD ≈ 2.5 ns

w/o Schottky

82

83

84

85

86

87

88

89

90

2 4 6 8 10 12 14 16 18 20 22 24 26 28

Eff

icie

ncy (

%)

Output Current (A)

eGaN FET

TDEAD ≈ 2.5 ns

eGaN FET

TDEAD ≈ 10 ns

eGaN FET

TDEAD ≈ 5 ns

Si MOSFET

TDEAD ≈ 2.5 ns

w/o Schottky

w/ Schottky

VIN =12 V, VOUT =1.2 V, and fsw =1 MHz

Impact of Dead-time


Fixed Dead-time Implementation

G N D

A

B

Y

V D D

U 1

NC7SZ00L6X

R 5

47.0

C 7

1 0 0 p

D 2

SDM03U40

R 4

22.0

C 6

1 0 0 p

D 1

SDM03U40

V C C

2

P 1

Optional

2

P 2

Optional

G N D

A

B

Y

V D D

U 4

NC7SZ08L6X

Used on all EPC90XX boards

Single PWM input

Inverter

Buffer

To LM5113 High side input To LM5113 Low side input

RCD filters delay turn-on, but not turn-off

Dead-time


Layout


tCF ∝ QGS2 tVR ∝ QGD

Ideal Hard Switching

VDS IDS

VGS

VIN

IOFF

𝐏𝐭𝐕𝐑 ≈𝐕𝐈𝐍 ∗ 𝐈𝐎𝐅𝐅 ∗ 𝐐𝐆𝐃

𝟐 ∗ 𝐈𝐆 𝐏𝐭𝐂𝐅 ≈

𝐕𝐈𝐍 ∗ 𝐈𝐎𝐅𝐅 ∗ 𝐐𝐆𝐒𝟐𝟐 ∗ 𝐈𝐆

t

VPL VTH


0

10

20

30

40

50

60

70

80

100 V eGaN®FETGen2

100 V eGaN®FETGen 4

100 V MOSFET 1 100 V MOSFET 2 100 V MOSFET 3

FO

M =

(Q

GD+

QG

S2)*

RD

SO

N (p

C*Ω

)

QGD

QGD

QGD QGD QGD

QGS2

QGS2

QGS2

QGS2 QGS2

100 V Device Comparison

VDS=0.5*VDS, IDS= 10 A

100 V

eGaN FETs

100 V MOSFETs


3

3.25

3.5

3.75

4

4.25

4.5

4.75

5

5.25

5.5

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3P

ow

er

Lo

ss(W

)

Parasitic Inductance (nH)

Power Loss vs Parasitic Inductance

Ls

3

3.25

3.5

3.75

4

4.25

4.5

4.75

5

5.25

5.5

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3P

ow

er

Lo

ss(W

)

Parasitic Inductance (nH)

Power Loss vs Parasitic Inductance

Ls LLoop

Cin

T

SR

LS: Common Source

Inductance VIN=12 V, VOUT=1.2 V,

fsw=1 MHz, IOUT= 20 A LLoop: High Frequency

Power Loop Inductance

Converter Parasitics


LGA

0

0.5

1

1.5

2

2.5

SO-8 LFPAK DirectFET LGA

Po

we

r L

os

s (

W)

Device Loss Breakdown

Package

Die

18%

82%

0

0.5

1

1.5

2

2.5


Po

we

r L

os

s (

W)


Package

Die

18%

82%

27%

73%

0

0.5

1

1.5

2

2.5


Po

we

r L

os

s (

W)


Package

Die

18%

82%

27%

73%

53%

47%

0

0.5

1

1.5

2

2.5


Po

we

r L

os

s (

W)


Package

Die

18%

82%

27%

73%

53%

47%

82%

18%

LGA eGaN FET SO-8 LFPAK DirectFET

65

70

75

80

85

90

0.5 1 1.5 2 2.5 3 3.5

Eff

icie

ncy (

%)

Switching Frequency (MHz)

SO-8

LFPAK

DirectFET

LGA

VIN =12V

VOUT =1.2V

IOUT =20A

fsw =1MHz

Drain

Source

Gate

Package Impact on Efficiency


83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22 24

Eff

icie

ncy (

%)

Output Current (A)

LLoop≈

1.0nH

40 V eGaN FET 40 V MOSFET

LLoop≈

2.2nH

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22 24

Eff

icie

ncy (

%)

Output Current (A)

LLoop≈

1.0nH LLoop≈

1.7nH


LLoop≈

2.2nH

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22 24

Eff

icie

ncy (

%)

Output Current (A)

LLoop≈

1.0nH LLoop≈

1.7nH

LLoop≈

0.4nH


LLoop≈

2.2nH

VIN=12 V, VOUT=1.2 V, fsw=1 MHz, L=300 nH

Measured Efficiency

Layout Impact on Efficiency

Ref: D. Reusch, J. Strydom,

“Understanding the Effect of PCB Layout

on Circuit Performance in a High

Frequency Gallium Nitride Based Point of

Load Converter,” APEC 2013

EPC Optimal Layout


LLoop≈1.0 nH LLoop ≈ 0.4 nH

Layout Impact on Peak Voltage

VIN=12 V VOUT=1.2 V IOUT=20 A

fsw=1 MHz L=150 nH

Switching Node Voltage

70% Overshoot 30% Overshoot


Top View

Conventional Lateral Layout

Side View

Shield Layer


Top View Side View

Conventional Vertical Layout

Bottom View


Side View

Top View

EPC Optimal Layout

Top View

Inner Layer 1


CIN

Q1

Q2

U2

Optimal Layout Implementation

CIN

Q1

Q2

U2


Layout Inductance Comparison

Top View Test Cases Board Thickness (mils)

Inner Layer Distance (mils)

Design 1 31 4 Design 2 31 12 Design 3 62 4 Design 4 62 26


Power Loss Comparison

VIN=12 V VOUT=1.2 V IOUT=20 A fsw=1 MHz L=300 nH

T/SR: EPC2015 Driver LM5113

3

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Po

wer

Lo

ss (

W)

High Frequency Loop Inductance (nH)

Vertical Power

Loop

Lateral Power

Loop

Optimal Power

Loop


Efficiency Comparison

VIN=12 V VOUT=1.2 V fsw=1 MHz L=300 nH

GaN T/SR: EPC2015 Driver LM5113

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22 24 26

Eff

icie

nc

y (

%)

Output Current (A)

40 V MOSFET

Vertical Design 1

Vertical

Design 1

Lateral

Design 1

Optimal

Design 1

40 V

eGaN FET


Voltage Overshoot Comparison



20

30

40

50

60

70

80

90

100

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vo

ltag

e O

vers

ho

ot

(%)


Vertical Power

Loop

Lateral Power

Loop

Optimal Power

Loop


Switching Speed Comparison



0

1

2

3

4

5

6

7

8

9

10

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

eG

aN

FE

T d

V/d

t (V

/ns

)


Vertical Power

Loop

Lateral Power

Loop

Optimal Power

Loop


eGaN FET vs. MOSFET

VIN=12 V VOUT=1.2 V IOUT=20 A fsw=1 MHz L=300 nH eGaN FET

T/SR: EPC2015 MOSFET T:BSZ097N04 SR:BSZ040N04

Si MOSFET

eGaN FET

3 V/ div 20 ns/ div


0

5

10

15

20

25

30

35

40V eGaN®FETGen 2

30V eGaN®FETGen 4

40 V MOSFET 1 40 V MOSFET 2 25V MOSFET 1 25V MOSFET 2

FO

M=

(QG

D+

QG

S2)*

RD

SO

N (p

C*Ω

)

QGD

QGD QGD

QGD QGD

QGS2

QGS2

QGS2

QGS2 QGS2

40 V MOSFETs

25 V MOSFETs 40 V

eGaN FET

QGD

QGS2

30 V

eGaN FET

Lower Voltage Comparison


80

81

82

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22

Eff

icie

ncy (

%)

Output Current (A)

40 V Discrete eGaN FET

40 V Discrete MOSFET

80

81

82

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22

Eff

icie

ncy (

%)

Output Current (A)




80

81

82

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22

Eff

icie

ncy (

%)

Output Current (A)




30 V Module MOSFET

VIN=12 V VOUT=1.2 V fsw=1 MHz L=300 nH

Lower Voltage Comparison


40 V Si MOSFET

30 V Si MOSFET Module


40 V

eGaN FET

3 V/Div 20 ns/ div

Switch Node Voltage

Switching Comparison


EPC9107 Demonstration Board

VIN=12-28 V VOUT=3.3 V

IOUT=15 A fsw=1 MHz

2 x EPC2015

5 V/ div

Switching Node

Voltage VIN=28 V, IOUT=15 A

VIN=28 V ~3V overshoot @ 15 AOUT

20ns

~1.1ns rise time @ 15 A


VIN=12 V VOUT=1.2 V

86

87

88

89

90

91

92

93

94

2 6 10 14 18 22 26 30 34 38 42 46 50

Eff

icie

nc

y (

%)

Output Current (A)

EPC2015 +

EPC2015

EPC2015 +

EPC2023

fsw=0.5 MHz

fsw=1 MHz

30 V

MOSFET

Module

Higher Current Devices


0

1

2

3

4

5

6

7

8

9

10

2 6 10 14 18 22 26 30 34 38 42 46 50

Po

wer

Lo

ss

(W

)

Output Current (A)

EPC2015 +

EPC2015

EPC2015 +

EPC2023

fsw=0.5 MHz

fsw=1 MHz

30 V

MOSFET

Module

VIN=12 V VOUT=1.2 V



Paralleling High-Speed eGaN FETs


Parallel Power Devices

?


QGS2 QGD

VDS

t

VTH

Unbalanced Loop Inductance

VGS1

VGS2

IDS1

IDS2

IDS

VGS

VDS1

VDS2


Loop Inductance Impact

0

5

10

15

20

25

30

35

40

45

0 0.2 0.4 0.6 0.8 1 1.2

Cu

rre

nt

Dif

fere

nc

e (

%)

Loop Inductance Difference (nH)

LS=0.10nH

LS=0.15nH

LS=0.20nH

LS=0.25nH

LS=0.50nH

VIN=48 V IOUT=25 A eGaN FET T/SR: 100 V EPC2001


VIN=48 V VOUT=12 V IOUT=30 A fsw=300 kHz L=3.3 µH GaN FET T/SR: 100 V EPC2001

10 V/ div 5 ns/ div

SR1 SR4

Single Loop Optimal Layout

T1-4 SR1 SR4



10 V/ div 5 ns/ div

SR1

SR4

T1

T2 T4

T3

SR2 SR4

SR3 SR1 SR4

Parallel Loop Optimal Layout


94.5

95

95.5

96

96.5

97

2 6 10 14 18 22 26 30 34 38 42

Eff

icie

ncy (

%)

Output Current (A)

4 ǁ eGaN FETs

Proposed Four Distributed

Power Loops Design

Conventional Single

Power Loop Design

Parallel Layout Performance

VIN=48 V VOUT=12 V fsw=300 kHz L=3.3 µH GaN FET T/SR: 4x100 V EPC2001

4 Layer 2 oz PCB


T1-4 SR1-4

Parallel Layout Implementation

T1

T2 T4

T3

SR1

SR2 SR4

SR3



30

40

50

60

70

80

90

100

110

2 6 10 14 18 22 26 30 34 38

Maxim

um

Tem

pera

ture

(°C

)

Output Current (A)

Proposed Four Distributed

Power Loops Design

Conventional Single

Power Loop Design

Parallel Layout Performance

VIN=48 V VOUT=12 V fsw=300 kHz L=3.3 µH GaN FET T/SR: 100 V EPC2001

Fan Speed 200 LFM 4 Layer 2 oz PCB


10 V/ div 5 ns/ div

2x eGaN FET

4x eGaN FET

1x eGaN FET

Parallel eGaN FET Swithcing

VIN=48 V VOUT=12 V IOUT=30 A/ number of devices fsw=300 kHz GaN FET T/SR: 100 V EPC2001


92

92.5

93

93.5

94

94.5

95

95.5

96

96.5

97

97.5

98

98.5

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

Eff

icie

nc

y (

%)

Output Current (A)

300kHz

EPC2001 4 ǁ EPC2001

245 kHz Si

Isolated IBC

150 kHz Si

Isolated IBC

14 W

Parallel Buck in IBC Applications

VIN=48 V VOUT=12 V Fully Regulated IBC

92

92.5

93

93.5

94

94.5

95

95.5

96

96.5

97

97.5

98

98.5

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

Eff

icie

nc

y (

%)

Output Current (A)

300kHz

EPC2001 4 ǁ EPC2001

300kHz EPC2001 + EPC2021

245 kHz Si

Isolated IBC

150 kHz Si

Isolated IBC

14 W



VIN=48 V VOUT=12 V

92

93

94

95

96

97

98

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

Eff

icie

nc

y (

%)

Output Current (A)

fsw=300 kHz

fsw=500 kHz

80V MOSFET

80 V EPC

Gen 4

100 V EPC

Gen 2



VIN=48 V VOUT=12 V VIN=48 V VOUT=12 V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

Po

wer

Lo

ss

(W

)

Output Current (A)

EPC2001

+

EPC2001

EPC2001

+

EPC2021

fsw=300 kHz

fsw=500 kHz

80V MOSFET


Fan Speed=200 LFM fsw=300 kHz VIN=48 V VOUT=12 V IOUT=30 A

Improved Thermal Performance


Thermal


RƟCA

Thermal Management

Silicon Substrate

Active GaN Device Region RƟJC

RƟBA

RƟJB

TJ


Packaging Advancements

Single Sided

Cooling

RƟJB ↓


Package Comparisons

0

0.5

1

1.5

2

2.5

3

0 5 10 15 20 25 30 35

RƟ

JB

, Th

erm

al

Resis

tan

ce (

°C/W

)

Device Area (mm2)

RθJB_Si RθJB_GaN


Package Comparisons

0

0.5

1

1.5

2

2.5

3

0 5 10 15 20 25 30 35

RƟ

JC

, T

herm

al

Re

sis

tan

ce (

°C/W

)

Device Area (mm2)

RθJC_Si RθJC_GaN


80

81

82

83

84

85

86

87

88

89

90

91

2 4 6 8 10 12 14 16 18 20 22

Eff

icie

ncy (

%)

Output Current (A)

40 V eGaN FET

40 V MOSFET

Performance Comparison



VIN=12 V, VOUT=1.2 V, IOUT=20 A, fsw=1 MHz, L=300 nH

Thermal Comparison

GaN is 38% Smaller 13% Cooler



Thermal Comparison

20

30

40

50

60

70

80

90

100

110

120

130

140

150

2 4 6 8 10 12 14 16 18 20 22 24 26

Ma

xim

um

Te

mp

era

ture

(C

)

Output Current (A)

eGaN FET

MOSFET

0 LFM

20

30

40

50

60

70

80

90

100

110

120

130

140

150

2 4 6 8 10 12 14 16 18 20 22 24 26

Ma

xim

um

Te

mp

era

ture

(C

)

Output Current (A)

eGaN FET

MOSFET

0 LFM 200 LFM


VIN=12 V VOUT=1.2 V

Generation 4 Thermal Performance

20

30

40

50

60

70

80

90

100

110

120

130

140

150

0 4 8 12 16 20 24 28 32 36 40 44

Ma

xim

um

Te

mp

era

ture

(°C

)

Output Current (A)

400 LFM

fsw=1 MHz

200 LFM

Natural

Convection


Measurement


Voltage Measurement

Place probe tip in large via or exposed pad

Minimize loop

Do not use probe ground lead

Do not let probe

tip touch the

low-side die!

Ground probe against TP3 OR use wire ground


Probe Options

Yokogawa Probe Hand-made Probe Adapter

Tektronix PCB Jack

http://www.google.com/url?sa=i&source=images&cd=&cad=rja&docid=GxR4oJqSXMWk4M&tbnid=2KVfX9IRNlJiuM:&ved=0CAgQjRwwAA&url=http://www.cliftonlaboratories.com/july_2007.htm&ei=FknfUYzBBo2ujAKrmoCgAQ&psig=AFQjCNGu7o7kD8KZOEeXg1-zqyB2cmeBzg&ust=1373674134182653http://www.google.com/url?sa=i&source=images&cd=&cad=rja&docid=CkJfEDDyObddFM&tbnid=6OVVWJeJtOef0M:&ved=0CAgQjRwwADixAg&url=http://tmi.yokogawa.com/us/products/oscilloscopes/voltage-probes/pba2500-701913-25-ghz-active-probe/&ei=nknfUZWrMMmsiQLBqIH4Ag&psig=AFQjCNFExzkwIwq3rXy3Ifuk3UTpcvnaxg&ust=1373674270848600


1GHz, 100:1, 1pF / 5k probe

4GHz, 40Gsa/s oscilloscope

500MHz, 10:1, 10pF / 10M probes

1GHz, 4Gsa/s oscilloscope

High Speed Measurement


• eGaN FETs raise the bar for power conversion performance

• Lower resistance per die area

• Better FOM’s

• Better Packaging

• Improved PCB Layout Techniques

• Superior In-Circuit Performance

• Can parallel devices for higher current

• Avoid gate overshoot and long dead-times

Design Basics Summary


Design Examples


Design Example Agenda

• Resonant Bus Converter

• Envelope Tracking

• Wireless Power

• LiDAR

• Class-D Audio


Resonant Bus Converter


Figure of Merit (FOM) History

•In 1989, Baliga derived a switching FOM

•𝐁𝐇𝐅𝐅𝐎𝐌 =𝟏

𝐑𝐎𝐍,𝐒𝐏∙𝐂𝐈𝐍,𝐒𝐏

•In 1995, Kim et al proposed a new FOM

•𝐍𝐇𝐅𝐅𝐎𝐌 =𝟏

𝐑𝐎𝐍,𝐒𝐏∙𝐂𝐎𝐒𝐒,𝐒𝐏

•In 2004, Huang proposed a new FOM

•𝐇𝐃𝐅𝐎𝐌 = 𝐑𝐎𝐍,𝐒𝐏 ∙ 𝐐𝐆𝐃,𝐒𝐏


LM

Resonant Bus Converter

Ref: Y. Ren, M. Xu, J. Sun, and F. C. Lee, “A family of high power density unregulated bus converters,” IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1045–1054, Sep. 2005.

High Frequency DC/DC Transformer

4:1

48V

VIN

+

-

Q1

Q2 Q3

Q4

CO

S2

S1

LK2

LK1

IPRIM

ILK1

VGS(Q2,Q4) VGS(S2)

VGS(Q1,Q3) VGS(S1)

VDS(Q1)

t0 t1

VIN

t2 t3

I Lk1

D

tZVS

ILM

IPRIM


Gate Charge Figure of Merit

0

100

200

300

400

500

600

0 50 100 150 200 250

FO

M=

QG·R

DS

(on

) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

Vendor C

Vendor D

Vendor E

9.9x

1.3x

4.2x


𝑡𝑍𝑉𝑆

I

𝑡

Output Charge

sDRG fVQ =PG

V

𝑡

𝑉𝐷𝑆 𝑡𝑍𝑉𝑆

𝑉𝐺𝑆

QOSS

𝐼𝑆𝑊

tZVS IRMS PCON

𝐷 ∗ 𝑇𝑆


VDS=0.5·VDSS

Output Charge FOM

0

200

400

600

800

1000

1200

1400

1600

0 50 100 150 200 250

FO

M=

QO

SS·R

DS

(on

) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

2.6x

1.9x 1.7x


0

100

200

300

400

500

600

700

800

0 50 100 150 200 250

FO

M=

QG\Q

OS

S·R

DS

(on

) (p

C·Ω

)


Soft-Switching FOM

QOSS

QG

𝐅𝐎𝐌𝐒𝐒 = (𝐐𝐎𝐒𝐒+𝐐𝐆) ∙ 𝐑𝐃𝐒(𝐨𝐧)

8x

3.5x 1.2x


Soft-Switching FOM

𝐅𝐎𝐌𝐒𝐒 = (𝐐𝐎𝐒𝐒+𝐐𝐆) ∙ 𝐑𝐃𝐒(𝐨𝐧)

0

500

1000

1500

2000

2500

0 50 100 150 200 250

FO

MS

S=

(QG+

QO

SS)·

RD

S(o

n) (p

C·Ω

)


EPC Gen 4

EPC Gen 2

Vendor A

Vendor B

3.2x

2.5x 2.4x


Transformer

Secondary

Devices

Primary

Devices

Input

Capacitors

Resonant

Capacitors

MOSFET vs. eGaN®FET

eGaN FET vs. MOSFET


MOSFET VGS MOSFET VDS

eGaN FET VDS

eGaN FET VGS

fsw = 1.2 MHz, VIN = 48 V, and VOUT ≈ 12 V

TZVS = 87 ns

TZVS = 42 ns

ZVS Switching Comparison


MOSFET VGS

MOSFET VDS

DMOSFET = 34% eGaN FET VDS

eGaN FET VGS

DeGaN FET = 42%

Duty Cycle Comparison



90

91

92

93

94

95

96

97

98

0 5 10 15 20 25 30 35 40

Eff

icie

nc

y (

%)

Output Current (A)

1.2 MHz MOSFET

1.2 MHz eGaN FET

10 W 12 W

14 W

2

4

6

8

10

12

14

16

18

20

22

24

0 5 10 15 20 25 30 35 40

Po

wer

Lo

ss

(W

)

Output Current (A)

1.2 MHz eGaN FET

1.2 MHz MOSFET

5 A

Efficiency Comparison



LK2

**

*

VIN-

VIN+ VOUT+

LIN

CIN

LK1

4:1

LOUT

COUTCRES

Q1

Q2 Q4

Q3

VOUT-

Q6,Q7

Q5,Q8

2 SR

2 SR

EPC9105 Demonstration Board 36 - 60 VIN, 12 VOUT, 350 W, 1.2 MHz

EPC9105 Bus Converter


Envelope Tracking


Same average

Reference: Nujira.com website

0

2

4

6

8

10

12

2012 2013 2014 2015 2016 2017

Ex

ab

yte

s p

er

Mo

nth

Source: Cisco VNI Mobile Data Traffic Forecast

66% Compound annual growth

rate (CAGR)

Why Envelope Tracking?


Output Power (dBm)

Average

Power

Output

Probability

Envelope

Tracking

Fixed

supply

Peak Power

PAPR = 0dB

Peak efficiency

up to 65%

Envelope Tracking


Gen 3 FOM

EPC2014

EPC8004

eGaN FET

EPC8000 Series


Hard Switching FOM


HB Layout – Top Layer

To BUS caps

Switch

node

Ground Bottom Gate

Top Gate Ga

te

Drain

Source

Sub

S

Gate

Drain Sub

S

Re

turn

R

etu

rn

Source

Gate

Current

orthogonal

to drain

current

Vias to next layer

Supply

Vias to next layer


Optimum gate

loop return

Optimum gate

loop return

To gate

drive

To gate

drive

Optimum power

loop return

Gate

Drain

Source

Sub

S

Gate

Drain Sub

S

Re

turn

R

etu

rn

Source

HB Layout – Inner Layer 1


Envelope Tracking Prototype Board

EPC8005

Bus caps

SO-8 footprint

EPC8005 LM5113


VIN=42 V VOUT=20 V

65%

70%

75%

80%

85%

90%

95%

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Eff

icie

nc

y

Output Current (A)

5 MHz

10 MHz EPC8005

High Frequency Efficiency


EPC8005

42VIN, 10 MHz Losses

Conduction

Switching

COSS

Unaccounted losses


10 MHz switching, no load, large dead-time

No-Load Switching

Initially slow

rising edge

Actual voltage commutation

slopes are different, even

though currents are the same

10V/div, 100mA/div, 10ns/div

Expected commutation based on

eGaN FET COSS


Le

ve

l S

hift

VDD VDD

IC c

ap

acita

nce

Bo

ots

tra

p d

iod

e

Reverse

recovery

charge

Switch-node

rising edge

LM5113 half-bridge

driver

Parasitic Losses


Bootstrap QRR

10 MHz switching, no load, large dead-time 10V/div, 100mA/div, 10ns/div

Switch-node voltage

Actual commutation based on total

COSS – including IC capacitance

Loss Breakdown


EPC8005

Conduction

Switching

COSS

Unaccounted losses

42VIN, 10 MHz Losses


Calculated efficiency improvement

eGaN FET Limited Efficiency


Wireless Power


Wireless Power

• The global wireless charging market is estimated to grow to $10B by

2018, a CAGR of 42.6%

• eGaN FETs enable higher efficiency and operation at safer

frequencies


Experimental System Setup

eGaN FETs RF connection

Device Board

Source Coil Source Board

Coil Feedback

Device Coil

25m

m

RF connection

50mm


Coil Simplification

Lsrc Ldev

Cdevs

RDCload

Cout

Ldevs

Cdevp Zload

Coil Set

Simplified representation of coil-set for easy comparison between topologies


Single Ended Class-E

VDD

Ideal Waveforms

VDS ID

time

3.56 x VDD

V / I

50%

Q1

+

Csh

Cs Le LRFck

Zload

• Switch voltage rating ≥ 3.56·Supply (VDD).

• COSS “absorbed” into matching network.

• Susceptible to load variation - high FET losses.

• Coil voltage ≈ 0.707·VDD [VRMS].


Class-E Device Comparison

FoMWPT [nC·mΩ]

0

200

400

600

800

1000

1200

1400

1600

EPC

20

12

MO

SFET

SE-CE

SE-CE

GDGDS(on)WPT QQRFOM

100

200

300

400

500

600

700

800

900

1000

0 100 200 300 400 500 600

Devic

e P

ow

er

[mW

]

RDS(on) [mΩ]

MOSFET

eGaN FET

Gate Power

dominant

Conduction Loss

dominant

Lowest Power Dissipation


Class-E Analysis Comparison

2

6

10

14

18

80

85

90

95

100

0 10 20 30 40 50

Ou

tpu

t P

ow

er

[W]

Effi

cie

ncy

[%

]

DC Load Resistance [Ω]

eGaN FET Eff.

MOSFET Eff.

eGaN FET Pout

MOSFET Pout

EPC2012

MOSFET 95.6%

98.5 %

85.2%

94.4%

Peak Power Device losses = 279 mW No Heat-Sink Required


ZVS Class-D

+ VDD

Cs Q2

Q1 Zload

LZVS

CZVS

V / I

VDS ID

time

VDD

50%

Ideal Waveforms ZVS tank

• Switch voltage rating = Supply (VDD).

• COSS voltage is transitioned by the ZVS tank .

• ZVS tank circuit does not carry load current.

• Coil voltage = ½·VDD [VRMS].


Device Comparison

020406080

100120140160180

EP

C8009

EP

C2007

MO

SF

ET

2

MO

SF

ET

3

ZVS-CD

FoM

WP

T [

nC

·mΩ

]

VG

S =

10

V

GDGDS(on)WPT QQRFOM

ZVS-CD


64

68

72

76

80

84

10 15 20 25 30 35 40 45 50

Eff

icie

ncy [

%]


64

68

72

76

80

84

10 15 20 25 30 35 40 45 50

Eff

icie

ncy [

%]


Load Variation Results

η EPC8009 ZVS-CD

η MOSFET 2 ZVS-CD

η MOSFET 3 ZVS-CD η EPC2012 SE-CE

η MOSFET 1 SE-CE

Coil becomes Inductive

Coil becomes Capacitive

Fixed Supply Voltage


LiDAR


LIght Detection And Ranging

• Autonomous vehicles • Video games • Geology • Agriculture

http://www.usgs.gov/blogs/features/usgs_top_story/hurricane-season-is-here/


LiDAR

Courtesy of OmniPulse


Class-D Audio


Why eGaN FETs in Class-D Audio

• Low RDS(on) & Low COSS + High Efficiency

+ High Damping Factor = Low open loop output Impedance = Low T-IMD

• Fast Switching & No Reverse Recovery (Qrr) + High output linearity, Low

Cross-over Distortion

= Low THD


eGaN FET Class-D Audio Amplifier

RCA Inputs

XLR Input

XLR Input

±30 V supply

Speaker Connections

• Bridge-Tied-Load (BTL) • EPC2016 with LM5113

LF1

CF1Q2

Q1 LF2

Q4

Q3

CF2

eGaN FET Power Stage:

250 W into 4 Ω at 440 kHz without a heatsink


A Look Into the Future


Breaking Down the Barriers

• Does it enable significant new capabilities?

• Is it easy to use?

• Is it VERY cost effective to the user?

• Is it reliable?





• Is it reliable?



Faster Transistors

eGaN FETs are Faster

Faster transistors enable the systems to get

smaller, more efficient, and lower cost.


Key Applications

• Wireless Power Transmission

• RF DC-DC “Envelope Tracking”

• LiDAR

• RadHard

• Network and Server Power Supplies

• Point of Load Modules

• Energy Efficient Lighting

• Class D Audio

• Various Medical


Product Revenue Forecast 2018

NRE 1%

Lighting 1%

RadHard 1% MRI 2%

Audio 2%

DC-DC 9% LiDAR 6%

WiPo 18%

Envelope Tracking 22%

AC-DC 38%





• Is it reliable?



It’s just like a MOSFET

Is an eGaN FET Easy to Use?

except

The high frequency capability makes circuits using eGaN FETs sensitive to layout

The lower VG(MAX) of 6 V makes it advisable to have VGS regulation in your gate drive circuitry


Educating


• Virginia Tech • University of California at Santa Barbara • Rensselaer Polytechnic Institute • Hong Kong University of Science and Technology • Cornell University • Katholieke Universiteit Leuven • University of Bristol • University of Glasgow • University of Sheffield • University of Warsaw • University of Sydney • Massachusetts Institute of Technology • Cambridge University • National Central University of Taiwan • National Taiwan University • Chang Gung University • University of Florida • Florida State University • Case Western University

• Yale University • University of Ohio, Toledo • Ohio State University • Kyushu Institute of Technology • National Chiao Tung University • University of Tennessee • Auburn University • University of Texas • Yamaguchi University • Universitat Kassel • National Tsinghua University • Mid Sweden University • New Mexico State University • University of Johannesburg • University of Toronto • Universita di Padova • Delft University of Technology • Missouri University of Science and Technology • University of Maryland • Insitituto Italiano di Technologia

Universities all over the world are graduating well-trained engineers experienced in the use of GaN Transistors

Universities with GaN Transistor Programs


92.5

93

93.5

94

94.5

95

95.5

96

96.5

97

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Eff

icie

nc

y (

%)

Output Current (A)

DrGaNPLUS

300kHz

80V MOSFET

300kHz

92.5

93

93.5

94

94.5

95

95.5

96

96.5

97

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Eff

icie

nc

y (

%)

Output Current (A)

DrGaNPLUS

300kHz

80V MOSFET

300kHz

DrGaNPLUS

500kHz

Simplifying GaN- DrGaNPLUS

VIN=48 V VOUT=12 V fsw=300 kHz L=10 µH eGaN FET T/SR: 100 V EPC2001

MOSFET T/SR: 80 V BSZ123N08NS3G






• Is it reliable?


Silicon vs. eGaN Product Costs

Starting Material

Epi Growth

Wafer Fab

Test

Assembly

OVERALL

2014 2015

lower lower

higher

same

same

lower

lower

same

lower

~same?

lower! higher






• Is it reliable?


High Temp Reverse Bias (HTRB)

Part Number Stress VDS (V) Temperature (oC) Sample Size

Results (# of fails)

Duration (Hrs)

EPC2001 80 150 207 0 500

EPC2001 80 150 144 0 168

EPC2001 80 150 80 0 1000

EPC2001 80 125 96 0 168

EPC2001 100 125 45 0 1000

EPC2016 80 150 239 0 500

EPC2016 100 150 80 0 168

• Over 0.5 million accumulated device hours of reliability testing without

failure across 891 devices.


100 V HTRB Acceleration

90 °C

35 °C

150 °C

FIT Rate vs VDS and Temperature

0.0001%

1%0.01%

20 yrs

10 yrs

Tim

e to

Fai

l


HTGB Acceleration

10 yrs

MTTF vs VGS

1 FIT

FIT Rate vs VGS


High Temp Gate Bias (HTGB)

Part Number Stress VGS (V) Temperature (oC) Sample Size Results (# of fails) Duration (Hrs)

EPC2001 5 150 48 0 168

EPC2001 5 125 167 0 168

EPC2001 5 150 192 0 500

EPC2001 5 150 125 0 1000

EPC2014 5 150 48 0 500

EPC2015 5 125 96 0 168

EPC2015 5 150 50 0 1000

EPC2001 5.5 150 48 0 168

EPC2001 5.5 150 208 0 500

EPC2016 5.5 150 80 0 168

EPC2016 5.5 150 80 0 500

EPC2001 5.75 150 96 0 168

EPC2001 5.75 125 32 0 168

EPC2001 5.75 125 48 0 181

EPC2001 5.75 125 64 0 200

EPC2001 5.75 150 240 0 500

EPC2001 5.75 125 32 0 500

EPC2016 5.75 90 32 0 200

EPC2016 5.75 150 32 0 350

EPC2016 5.75 150 240 0 500

EPC2019 5.75 150 160 0 168

EPC2001 6 125 24 0 181

EPC2001 6 150 32 0 200

EPC2001 6 150 80 0 437

EPC2001 6 150 32 0 500

EPC2001 6 125 32 0 500

EPC2016 6 90 32 0 200

EPC2016 6 150 32 0 350

EPC2001 6.3 150 32 0 200

EPC2016 6.3 150 32 0 200

EPC2016 6.3 90 32 0 200

EPC2016 6.6 150 32 0 200

• 0 fail in over 0.97 million

accumulated device

hours of HTGB reliability

testing greater than 5V.

• 0 fail in over 0.6 million

accumulated device

hours of HTGB reliability

testing greater than

5.5V.


A Look Into the Future


Gen 2

2010-2013

40 V - 200 V

Generation 5

~December 2014

Moore’s Law Revival

Generation 3

Higher Frequency

Launched September 2013

High Voltage

September 2014

Half Bridge ICs

September 2014

Generation 4

2 X Performance Improvement

Launched June 2014


Generation 2/4

Discrete HB

Generation 4

Monolithic 4:1 HB

+

GaN Integration

T

SR

Top Switch (T) Synchronous

Rectifier (SR) 33 % die size reduction


Monolithic Half Bridge

70

72

74

76

78

80

82

84

86

88

90

2 6 10 14 18 22 26 30 34 38 42

Eff

icie

ncy (

%)

Output Current (A)

GaN POL

w/ Gen 4

Discrete Transistors

GaN POL

w/ Gen 4

Monolithic HB 33 % die size reduction

fsw=2 MHz fsw=4 MHz fsw=3 MHz

VIN=12 V VOUT=1.2 V L=100 nH


Summary

• GaN transistors enable exciting new applications such as LiDAR, RF Envelope Tracking and Wireless Power Transmission

• GaN transistors have the potential to replace silicon power MOSFETs and LDMOS in power conversion applications with a low-cost and higher efficiency solution

• GaN technology is keeping Moore’s Law alive!

GaN Transistors for Efficient Power Conversion · 2016. 1. 10. · Reference: Texas Instruments,...

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Transcript of GaN Transistors for Efficient Power Conversion · 2016. 1. 10. · Reference: Texas Instruments,...