GaN Power Switch ALL-Switch Platform Application...

GaN Power Switch &

ALL-SwitchTM Platform

Application Notes AN01V650

Preliminary Application Note: VisIC, Ltd. reserves the right to make design improvement changes at any time.

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APPLICATION NOTES AN01V650

VisIC GaN Transistor Features

Changes from Last Version:

1. Minor formatting changes

2. Addition of chapter 5 – PCB and Thermal design


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Table of Contents

1.Introduction ................................................................................................................. 3

2.VisIC GaN Switch Features .................................................................................. 4

2.1 Safe Normally OFF circuit ...................................................................................... 5

2.2 D-Mode GaN Transistor ......................................................................................... 8

3.Reverse Recovery .................................................................................................. 10

4.Gate Driver Consideration ............................................................................... 11

5.PCB Design ................................................................................................................. 14

5.1 Thermal Design ................................................................................................... 14

5.1.1 Top Cooling ......................................................................................................... 15

5.1.2 Bottom Cooling .................................................................................................. 21

5.2 Thermal Interface Material resistance calculation (TIM): .................... 22


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1. Introduction

The ever-growing market demand of vehicle electrification and energy

harvesting, the global increase in information storage and processing and

increase governmental regulation on energy efficiency put pressure on

designers of power systems to increase the operational performance and

power density of their products.

VisIC Technologies has met these demands with the introduction of its

proprietary High Voltage GaN Power Semiconductor Technology in

combination with the developed ALL-SwitchTM platform (Advanced Low Loss

Switch).

This document describes VisIC GaN power device characteristics in

conjunction with its SMD package, and focus on applying this technology for

high voltage, high power and high frequency applications.


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2. VisIC GaN Switch Features

To achieve the highest performance and reliability of the power transistor,

VisIC has developed the ALL-SwitchTM platform.

The All-SwitchTM is an SMT packaged MCM (multi chip module) featuring:

• Low parasiticsfor high switching frequency

• Low switching losses (see Fig. 1)

• Safe normally OFF operation

• Low thermal resistance.

Fig. 1 V80N65B Switching Energy


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Products are available with top or bottom cooling versions:

The ALL-SwitchTM consists of three key technologies:

- Enable Circuit: Si circuit providing a safe Normally OFF operation.

- D-Mode GaN HEMT (High Electron Mobility Transistor) driven

directly by market available common MOSFET Drivers.

- EMPACK: SMT package with embedded AlN substrate for electrical

isolation and high thermal conduction.

2.1 Safe Normally OFF circuit :

Enable Circuit is incorporated in VisIC All-SwitchTM platform beside the GaN

transistor . Enable Circuit provides the switch with reliable and safe

normally OFF function in case of driver or AUX PSU failure.

Enable circuit performs two functions:

• Normally OFF (NOFF) Circuit.

• Under Voltage Lock Out (UVLO) Circuit.

NOFF Circuit:

This circuit is based on two low voltage P-Channel Si MOSFETS (Q2 and Q3),

one fast Schottky diode D1 and one pull-down resistor (see Fig. 2).

It is responsible for the Normally OFF (NOFF) feature.


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Operation description of NOFF Circuit:

Operation of NOFF Circuit maybe consider in three cases :

1) Only HV bias is applied to Drain Source -> as Q2 is normally OFF,

voltage rises on its Source.This induces negative Gate-Source potential

on the GaN, whose gate is clamped to Drain of Q2 through Diode D1.

When the negative Gate-Source potential reaches the threshold

voltage of GaN, it is turned off.(in a similar fashion to a Cascode

operation).

Fig. 2 V80N65B internal schematic

NOFF Circuit

Q1

Q2

Q3

D1 UVLO

Q4

D2

GaN


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2) HV bias is applied to Drain Source and Gate, VDD and GND pins are

connected to related pins of external driver IC, which is in power-off

state without supplying of VDD. -> Q3 in its OFF state prevents high

current path to the driver, and the scheme operates as in case 1.

3) During normal operation Q2 and Q3 are in ON state -> GaN is driven

directly from driver, and conducts through Q2.

UVLO Circuit:

This circuit consists of a pre biased BJT (Q4) and 9V Zener diode (see Fig. 2).

UVLO Circuit is provided to prevent erroneous operation during driver AUX

PSU startup and shutdown or when VDD is below its specified operating

circuits range.

Operation description of UVLO Circuit:

The Zener senses the driver supply voltage, if the voltage is above 9V the

BJT (Q4) is turned ON, which turns Q2 and Q3 ON – allowing normal

operation.

If AUX power voltage drops below 9V the UVLO circuit, using the NOFF

circuit, turns the GaN switch to normally OFF state.

UVLO and NOFF features in VisIC product portfolio:

*See section 4 for more detailed schematics.

V22N65A V80N65B V150N65B

NOFF Internal Internal Internal

UVLO External* Internal Internal


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2.2 D-Mode GaN Transistor:

Structure:

VisIC D-Mode GaN HEMT is a lateral device (see Fig. 3)

AlGaN/GaN hetero-epitaxy structure creates a channel of 2DEG (2-dimensional electron gas) which provides exceptional charge mobility and density.

Characteristics:

• The GaN transistor is rated for 650V blocking voltage

• D-Mode GaN is normally ON – at 0V Gate Source bias the channel is

fully open and conducts, at -7V Gate Source bias (threshold voltage)

the channel closes and only small leakage current is present (Fig. 4).

Fig. 1 GaN HEMT structure

AlN

AlGaN

GaN 2DEG

Buffer

GaN cap

Passivation Gate

Under-gate dielectric

Buffer layer

Si substrate

Drain

Source

Electron Flow

Fig. 3 GaN HEMT Structure


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Reverse operation:

As seen from the above graph (Fig. 4) during reverse Drain Source bias,

channel conduction depends on the Gate Source voltage (Vgs) applied:

• At Vth < Vgs< 0V the channel exhibits bidirectional conductivity.

Conduction loss equals Pcond=ISD2xRDS(ON),TJ

• At Vgs < Vth (Vgs<-6V) the channel resistance exhibits “diode like”

behavior, depanding on the negative Gate voltage bias. Conduction

loss equals Pcond=ISDxVSD(at operated VGS)

Fig. 4 V80N65B GaN Output I/V Characteristics


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3. Reverse Recovery

The GaN transistor does not have a build-in body diode and in addition there is no reverse recovery charge due to its lateral structure. Despite of the absence of a body diode, the device is naturally capable of reverse conduction. The reverse conduction characteristics is a function of gate to drain bias. Since the GaN is capable of reverse conduction, it can be modelled as having a body diode. This body diode has higher forward voltage drop and no reverse recovery charge relative to Si.

Si MOSFET

Qa=Qrr_diode

Qb=Qoss

Qrr=Qa+Qb

GaN HEMT

Fig. 5 Recovered Charge - Si MOSFET vs. GaN HEMT


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As it can be seen in Fig. 5 MOSFET Qrr > GaN Qoss, therefore the losses on Si MOSFET are higher then on GaN HEMT.

4. Gate Driver Consideration

In the ALL-SwitchTM platform the GaN is driven directly, the following

considerations should be taken into account when designing drive circuits.

• Recommended driver VDD voltage +12V

• ALL-SwitchTM Gate pin is connected directly to driver output via gate

resistor.

V80N65B & V150N65B specifics:

• VisIC ALL-SwitchTM GaN transistor Source ( VDD pin, Kelvin) is

connected to driver VDD (see Fig. 6), as opposite to an N-Channel Si

MOSFET where transistor Source is connected to Driver GND (see Fig.

7). Such connection allows to use standard 12V driver scheme to drive

a D-mode GaN with negative Gate Source bias.

• GND pin is connected to driver GND.

Fig. 6 V80N65B driving scheme

D-Mode GaN

Q1

Driver

V80N65B


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V22N65A specifics:

• As the UVLO circuit is external in this product, the connection scheme

is as follows (Fig. 8):

When the controller outputs an OFF signal, -12V is applied to GaN VGS, but

relative to driver GND the voltage is 0V

When the controller outputs an ON signal, 0V is applied to GaN VGS, but

relative to driver GND the voltage is 12V

Fig. 7 Standard N-Channel MOSFET driving scheme

Driver

Fig. 8 V22N65A driving scheme

GaN

V22N65A


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Driver AUX power supply isolation is required for the Enable circuitry, in

both High and Low side of power applications (Fig. 9)

Fig. 9 Driver AUX power supply connection for high and low side


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5. PCB Design:

The ALL-SwitchTM devices are intended for high speed, high frequency

switching. To achieve the highest performance, a good design of the power

and gate drive circuits is necessary.

The gate drive loop from driver output to GaN and back to driver GND

should be as short as possible to reduce parasitic inductance.

Dri

ver

Gate drive

loop

Figure 10 V80N65B PCB gate loop layout

Figure 11 V22N65A PCB gate loop layout

Gate drive

loop


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5.1 Thermal Design

VisIc Products incorporate an innovative Power packaging technology for

high power applications – EMPACK. VisIC offers both Top and Bottom

cooled components.

5.1.1 Top Cooling

The V22 Package innovative design provides high performance and low

thermal resistance through top cooling & embedded ceramic technology.

This design concept was adapted from the high powered Automotive LED

industry.

AlNi ceramic plate(600 times more thermally conductive then FR4)

facilitates head dissipation from the GaN Power Die (the junction) to the

component case , while keeping the case isolated from High Voltage (up to

2.5KV)

Figure 12 – embedded ceramic design Schematic side cut view

The V22N65A Tall Package design also provides electrical clearance

between the heatsink and the PCB.

The V22N65A is currently the only isolated top cooled SMT GaN device,

which matches all electrical clearance requirements.

Thermal Resistance calculation

The Total thermal resistance from Junction to Ambient is a critical

parameter which dictates the maximum power capacity for the device.


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𝑅𝐽𝐴 = 𝑅𝐽𝐶 + 𝑅𝑇𝐼𝑀 + 𝑅𝐻𝑆

- RJC is the resistance between junction to case and is a fixed value,

which is provided by the device manufacturer, 0.3[°C/W] for

V22N65A GaN switch.

- RTIM is the resistance of the Thermal interface between the case and

the heat sink, this parameter can be roughly estimated using the

following 1D heat conduction equation:

𝑅 =𝑙

𝑘𝐴

Where A is the Area of the component ceramic plate, K is the thermal

conductivity of the TIM and L is the TIM thickness.

When properly applied, RTIM can range from 0.1 to 0.2 [°C/W].

- RHS is highly dependent on heatsink design and airflow can range

widely from as little as 0.5[°C/W] (Liquid Cooling) and up to 20[°C/W]

for a natural convection heatsink.

VisIC recommends optimizing the heatsink to the expected power

disspation from the device.

Maximum allowed power dissipation

The maximum allowed heat power dissipation from a component is

detrmined by expected temperature gradient and total thermal resistance

from junction to ambient.

𝑃𝑑𝑖𝑠𝑠 =∆𝑇𝑚𝑎𝑥

𝑅𝐽𝐴

∆Tmax is the maximum allowed temperature for the device Die. This value

is always specified in the component datasheet. All VisIC GaN products are

rated to 150°C.


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Below is an example for calculating the V22N65A maximum allowed power

under set conditions:

RJC RTIM RHS RTot

0.3 0.1 0.5 0.9

• Maximum Allowed Temperature: 150[°C],

• Ambient Temperature: [25°]C,

𝑃𝑑𝑖𝑠𝑠 =𝑇𝑚𝑎𝑥 − 𝑇𝑎𝑚𝑏

𝑅𝐽𝐴=

150 − 25

0.9= 138[𝑊]

Heatsink Mounting for top cooled components

When mounting a shared heatsink for multiple top cooled SMD devices,

consideration is required to the stacking of tolerances in the assembly.

Namely, the sum of PCB, solder paste, component highet, and heat sink

surface tolerances.

Figure 13 Typical Air gap occurring due to height miss-match between

components under sink


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When The estimated sum of tolerances between components is greater

then 0.2[mm], simple Thermal paste might not provide an effective

thermal contact between case and heat sink.

In this case, one can consider the use of gap filler materials.

Since VisIC products are fully isolated, It is recommended to use a Non-

Insulating Thermal pad.

One Such product with Exceptional Thermal Qualities is the “TGON”

graphite thermal pad (Manufactured by Laird.LTD)

4 Screws Mounting Technique:

• Simple solution for heat sink mounting, accommodates 1 or

more devices.

• PCB Bending Stress is a concern,

• Recommended using 4 M3 screws, clamped with nuts on

opposite side of PCB.

Figure 14 – 4 screws heatsink mounting side view


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Back Plate Support Bending Stress in PCB due to Pre-loading of screws, Will usually create a negative deformation at the center of the screws formation, This effect can be greatly negated by using a back-side supporting plate.

Figure 15 – Backplate support exploded view

Center Screw Mounting Technique:

• The simplest solution for Device mounting.

• Suitable for configurations of two or four devices.

• Less stress on PCB due to bending.

• Forces a minimum distance between devices,

• Reduces Trace width between devices.

• recommended Using M3 plastic screw or metal screw with plastic

isolating bushing and washer.


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Figure 15 Center screw mounted heatsink exploded view

5.1.2 Bottom Cooling

The V80N65B is a bottom cooled SMT component with a very small foot-

print of 10X10mm. This small footprint. Bottom cooled components

dissipate their heat through the PCB and this is normally the dominant

resistance to consider for thermal design.

The 1st challenge to tackle for a good thermal design is the high thermal

resistance of the FR4 medium.

There are two commonly used and recommended ways to facilitate

imporved heat dissipation through the PCB:


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Copper coated Vias array.

Figure 16 thermal via array

Thermal Vias are a well known and widely used design, normally one

could expect reducing the PCB thermal resistance to 2-3[C/W]

• 0.2-0.3mm is the typical recommended mechanical drilling size.

• Small via diameter will ensure no solder wicking occours during

components reflow.

• Via Array area dimensions are limited due to Creepage limits.

• Thermal Design should focus on increasing copper ratio on the

board through via plating and number.

VisIC-tech recommends the following parametrs for Via array design:

Via Plating

Thickness

[mil]

Via

diameter

[mm]

Plating

Material Via Filling

Via Area

[mm2]

Via Pitch

[mm]

3 0.2 Copper Not Filled 0.016 1 - 1.60


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Copper Inlay

Figure 17 -copper coin inlay

Copper Inlay provides the best overall performance but is more novel. VisIC

suggests discussing the design with your PCB manufacturer.

When especialy high performance is required from the component, one can

consider opting to solder the components to the copper inlay using vapor

phase soldering, instead of reflow soldering. The Vapor phase soldering

method ensures no Voids occour beneath the ceramic plate, and thus the

effective area for thermal dissipation is maximized.

Below are the recommended Dimensions for a copper inlay inside a

standard 1.6mm PCB:

Front View Side View

The Inlay’s thickness should be the same as PCB thickness in order to ensure

optimal heatsink attachment to PCB.

Calculating the thermal resistance of the inlay RPCB is fairly simple using the

following equation and the dimensions above( l-Length, A-Area and K-

Thermal Conductivity):


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𝑅𝑃𝐶𝐵 =𝑙

𝐴 ∗ 𝐾=

1.6

26.73 ∗ 0.389= 0.15[

𝐶

𝑊]

5.2 Thermal Interface Material resistance calculation (TIM):

VisIC recommends the use of a thermal paste material. There is no need for

an Isolating TIM since the device thermal pad is isolated.

Recommended Thermal Paste layer thickness: 0.1[mm].

Recommended Thermal Paste: MX-4. (K=8.5[W/MK)

V22 Ceramic plate Area = 100[mm2]

V80 Ceramic Plate Area=27[mm]

Approx. Theoretical Resistance:

V80N65B 𝑅𝑇𝐼𝑀 =0.1

27∗0.0085=0.44[oC/W]

V22N65A 𝑅𝑇𝐼𝑀 =0.1

100∗0.0085=0.12[oC/W]

Please avoid applying a generous layer of Thermal paste, this only adds

additional resistance. Thermal Paste should not be used to bridge

particulary large “air gaps” between board to PCB.

Important Notice – VisIC Technologies reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products, latest issue, and to discontinue any product. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. Unless expressly approved in writing by an authorized representative of VisIC technologies , VisIC technologies components are not designed or tested for use in, and is not intended for use in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, weapons systems, authorized or warranted for use in lifesaving, life sustaining, military, or space applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of performance. VisIC Technologies hereby disclaims any or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights.

All rights reserved.

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