FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014...

FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET

Korea test conference workshop 2014

Jin-Soo Ko

Teradyne Inc.

[email protected]

Korea test workshop Oct. 15 2014 Jin-Soo Ko

• Fast Ramps• Essentially full volume from

product launch for high profile new products

• Must bring up new silicon process at the same time (14nm, FinFET)

• Yield must be good to reduce cost but defect rate must be extremely low

MOBILE DEVICE CHALLENGES

Number of units sold during the first weekend of

product introduction

COT is important but getting to market quickly with the best quality is what really counts!

Silicon Samples Mass Production

Days Weeks “Zero” DPM

ADVANCED SILICON PROCESS AND VDD

• Roadmap for Gate Length and Supply Voltage

ITRS SEMICONDUCTOR ROADMAP

MARKET TRENDS DRIVING IC TEST

5

Test Fast Time To

Market

Less Than 15 Days Si to Samples

Functional Integration

Large Test Lists

Collaborative Development

Quality<100 DPM For Mobility

Devices

Complex FlowsIncreased Device

Configuration and Repair

COT PressuresHigher Multisite,

Concurrent Test, Datalog overhead

Faster Time To Volume

>1M devices within 2 Months

WHAT IS THE MOST IMPORTANT FOR TEST? (FROM ITRS)

• Cost of Test, Time To Market and Test Quality are equally Important

• Why?• Test Costs are a small part of

the overall cost to make an IC. Focusing only on this does not increase profit much

• In the mobile space, being first to market captures more market share which increases profit the most

• Equipment manufacturers will not accept poor IC quality.

• High quality devices have higher value and bring more profit.

• Higher yield also means lower overall cost.


COST OF TEST(COT)

ATE Capital costs are actually decreasing

This also increases Time To Market

“consumable” items like probe cards and sockets are increasing in costs

Cost trends (ITRS)


COST OF TEST(COT)

Very dependent on DFT Technology

Could potentially eliminate System Level Test insertion to lower costs

Cost trends (ITRS)


DESIGN COMPLEXITY AND SCAN DEPTH

• Compression contained ATE memory requirements growth from 2000 to 2010, but is approaching theoretical limits

• Reduced Pin Count Test Will Drive Memory Requirements Higher

• Also puts strain on datalog and post processing features

Current Industry Practice

• As devices get more complex and scan compression can’t keep up, test times will get longer

• Increased ATE efficiency keeps COT flat

• Higher Site count (Multi-site Testing) is the most efficient way to reduce costs

• Similar to memory test

MORE SCAN TESTING = MORE TEST TIME

3X scan test time in 5 years due to higher gate count

PMICRF

Tx/Rx

ABBFM

BT

PMICRF

Tx/Rx

ABBFM

BT

PMICRF

Tx/Rx

ABBFM

BT

Tim

e

Concurrent

PM

ICB B

RF

FM

BT

US B

PM

ICB B

RF

FM

BT

US B

*Shared device functions prevent some concurrency

~17s

~11s (estimated)

COT - MULTI-SITE AND CONCURRENT TEST AND TTR

=> 35% TTR (estimated)Test Throughput improvement•N=16 sites (PTE 0.98)•35% test time reduction by concurrent test,•Multi-site test throughput 0.98xN site•Concurrent test throughput 1/( 1-0.35)

Throughput = 0.98x16/(1-0.35) = 24.12


CONCURRENT TEST PROGRAMMING AND DEBUG TOOL

TestsBlock A

TestsBlock BTests

Block CTestsBlock D

TestsBlock E

Initial

TestsBlock F

TestTime

Full FunctionalTest

Concurrent Test FlowSerial Test Flow

TestsBlock A

TestsBlock B

TestsBlock C

TestsBlock D

TestsBlock E

TestsBlock F

TestTime

Initial

Full FunctionalTest

Development Challenges• Common bus/pins• Shared test resources• Flow manipulation• Multi-site implementation• Adaptive test & Retest• Debug tools

Timeline viewer

13

Multi-site capability is the key strategy to achieve low COT

4-site codec in 2001

8-site CDP/DVDP in 2004

16-site Mobile A/V processor in 2007

32-site Mobile A/V processor in 2009

16 -site Mobile Application Process in 2011

32-siite from 2015 ?

Multi-site Test Roadmap

FLEX

8-site CD, DVD Player Processor SOC test solution

16-site

Mobile A/V Processor SOC test solution

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011

2 or 4-site 16-site 32-site 16-site

UltraFLEXCatalyst/Tiger

4-site Optical Disk Drive SOC test solution

8-site

32-site

Mobile A/V Processor SOC test solution

UltraFLEX-HC

16-32-site >1000 pin count SOC device test HIB design solutionusing new high density (x2 ~ x4)digital, AC, and DC options

UltraFLEX-XD

2012 2014

TIU+DSA

>> 32//2016


COT - MULTI SITE COUNT TEST ROADMAP

14

“High Mix” = many different device types tested in small lots“Low Mix” = only a few device types tested in large lots

Number of Sites

COT - MULTI SITE VS. PARALLEL TEST EFFICIENCY

15


AWG SEQUENCE FOR PATTERN BASED PROGRAMMING

BUCK1

BUCK2BUCK3

BUCK4BUCK5

BUCK6

BUCK7

VIN

MCU

LNR1 LNR2 LDR1 LDR2 LDR3

The entire AWG Plots

The scale reference is different in each plots.


COT - CHIP TO CHIP DATA


COT - PATTERN BASED PROGRAMMING TEST TIME

BUCK ,BUCK_DVS and LDO,LDO_LDR Test time reduction

Items Before[mS] After[mS] TTR[%]

BUCK 954.004 472.975 50.04

BUCK_DVS 512.082 170.643 66.67

LDO_LDR 613.420 245.368 60.0

LDO 231.010 92.404 60.0

Total 2301.516 981.401 57.36

PBP Chip to Chip Data


COT - UPGRADE TEST COMPUTER

• Next generation tester computer • Load & Validate time improvement up to ~ 20%• Average Runtime Improvement of ~ 4% to 20% • Windows 7

• 33% increase in application memory

• Microsoft Office 2010• Interoperability between Excel 2010 and Excel

2003• New Sheet-Grouping and Navigation Features Benchmark Test Summary:

Tera1 Windows7

Market Segment Run Time

PMIC 4.75%MAP+ DBB 4.30%

Connectivity 5%CODEC 11%Cellular 20%

COT – BUY RATE DOWN

EQUIPMENT CAPITAL BUY RATE DOWN

• Test equipment is already very efficient.

• Most new “test” investment focused on Time To Market and Quality to improve IC revenue and market share

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 20122013 thru Feb

Total ATE Buy Rate 3.6% 1.8% 1.5% 2.0% 2.4% 1.8% 2.0% 1.6% 1.1% 0.5% 1.1% 0.9% 1.0% 0.5%

SOC ATE Buy Rate 3.8% 1.6% 1.4% 1.8% 1.9% 1.5% 1.8% 1.2% 1.1% 0.6% 1.2% 0.9% 1.1% 0.6%

Memory ATE Buy Rate 3.3% 2.8% 1.9% 3.0% 3.9% 2.7% 2.5% 2.7% 1.1% 0.4% 0.9% 0.8% 0.6% 0.2%

Total IC Equipment Buy Rate 26.7% 23.4% 16.2% 15.5% 20.1% 16.5% 18.7% 19.0% 13.7% 8.1% 15.5% 17.1% 14.9% 10.1%

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

4.0%

4.5%

To

tal IC

Makin

g E

qu

ipm

en

t Bu

y R

ate

% (C

AP

EX

)

AT

E B

uy R

ate

%

Total ATE Buy Rate SOC ATE Buy Rate Memory ATE Buy Rate Total IC Equipment Buy Rate

Source: WSTS, SEMS (product only)

“Buy Rate” = ATE Cost / IC Revenue

1%

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 20122013 thru Feb

Total ATE Buy Rate 3.6% 1.8% 1.5% 2.0% 2.4% 1.8% 2.0% 1.6% 1.1% 0.5% 1.1% 0.9% 1.0% 0.5%

SOC ATE Buy Rate 3.8% 1.6% 1.4% 1.8% 1.9% 1.5% 1.8% 1.2% 1.1% 0.6% 1.2% 0.9% 1.1% 0.6%

Memory ATE Buy Rate 3.3% 2.8% 1.9% 3.0% 3.9% 2.7% 2.5% 2.7% 1.1% 0.4% 0.9% 0.8% 0.6% 0.2%

Total IC Equipment Buy Rate 26.7% 23.4% 16.2% 15.5% 20.1% 16.5% 18.7% 19.0% 13.7% 8.1% 15.5% 17.1% 14.9% 10.1%

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

4.0%

4.5%

To

tal IC

Makin

g E

qu

ipm

en

t Bu

y R

ate

% (C

AP

EX

)

AT

E B

uy R

ate

%

Total ATE Buy Rate SOC ATE Buy Rate Memory ATE Buy Rate Total IC Equipment Buy Rate

Source: WSTS, SEMS (product only)

2013

• $1.00 of IC revenue = $0.005 of test capital• Lowering Cost of Test 10% only increases profit by 0.05%• Raising Yield from 95% to 96% increases profit by > 1%

(Much better investment!)• Winning new socket increases market share (Best

investment!)

Buy Rate

“Front End” Costs

“Back End” Costs


TIME TO MARKET (TTM)

What is this and why you should care?• Directly impact to market share and profits

• Smart phone market is never wait for the delay of test.


TTM - HOW TO GET FAST TIME TO MARKET ?

• Industry standard test system and SW capability

• Integration with design and bench test

• Advanced ATE SW tools for Time to Market

• EDA Systems

• ATPG Tools

• Adaptive Test

• Real-time Fault Isolation

• Physical Failure Analysis

• “Big Data” Storage

Des

ign

Sim

ula

tion

On-Tester Debug/ Characterization (hours/minutes)

• Timing/Levels• Mixed Signal• Repeatability• Correlation

Pattern & Test

program. Gen.

events

transactions

ATPG

STDF

“off tester” tools

“on tester” tools

Failure Analysis / Yield Enhancement

EDA-based Pattern Viewer

• Simultaneous display of EDA and tester information

• Diagnose Physical Device Faults

Design Test Design Loop


TTM - MULTI-SHEET USE MODEL

• Separate test code & data for each sub program

• Tied together at the Job List Sheet

• Multi-Sheet Model

Sub-Program B

Sub-Program A

•Enabler for independent development•Reduces time to integrate

= no more manual merging of sub programs

TTM - RF TOOLS- LTE-A TX SIGNAL DEBUG TOOL

IG-XL 7.30

• ESA 2.0 3GPP LTE TD-SCDMA 802.11n 4x4 MIMO VSA 10.01• 1 port vector• Power de-embedding• Signal sheet support• Smith charting

IG-XL 7.40

• ESA 2.5 3GPP LTE Update Bluetooth 3.0 VSA 11

IG-XL 8.00.01

• ESA 3.0 LTE 8.9 VSA12

IG-XL 8.10

• ESA 3.5 LTE-A (R10) 802.11ac VSA 14

IG-XL 8.20

• ESA 4.0 LTE-A (100MHz) 802.11ac (160MHz) 802.11ac (80+80) BT 4.0 (LE) VSA 16• 90% reduction in VSA

instance creation times


• Match an independent part of the tester to each interface

• Match the device’s frequency, timing, etc.

• Communicate natively in the “Language” of the port

Integrated Mobile Device

CPU

MemI/F

MemI/F

DRAM Emulation Engine

DRAM Emulation Engine

JTAG Protocol EngineJTAG

I/F

USBI/F

USB Protocol Engine

DSPBB

Proc

Power MgmtFunctions

DC Test Resources

Audio / BBFunctions

AC Test Resources

GPS

4G

WiFi

FM/TV

Modulation Domain RF




Protocol LevelATE

Protocol Synchronization & Communication

TTM - How To Do Protocol Level Test?

“Stored Response” ATEComplex Device Architecture

Tries to Test

Integrated Mobile Device

CPU

DRAMI/F

FlashI/F

JTAGI/F

USBI/F

DSPBB

Proc

Power MgmtFunctions

Audio / BBFunctions GPS

3G RF

WiFi

FM/TV

Write.jtag ( ADDR: 04h, DATA: 55h)Read.jtag (ADDR: 0Ah, DATA read_var)

Protocol Definition Editor For defining and modifying protocols

Protocol StudioFor online debug of protocol transactions

• Transaction results Debug displays Data capture setups

• Module management Port Properties

TTM - PROTOCOL AWARE

DEVICE TRENDS DRIVE NEW TEST NEEDS

Lithography

More scan testing with failure capture and diagnosis capability = More Patterns, especially at the start of the product life

Need to capture high volumes of scan data for offline analysis

Higher speed Data IO

High Speed Characterization capability with phenomenal Timing accuracy.

Ability to use higher performance standard digital to screen devices in production to augment DFT. DFT-Only approach has more risk as data rates increase.

Lower voltage

Device Supplies < 700mV require excellent accuracy. Huge Current steps cannot cause glitches

More complex RF Standards

Precise measurement of complex RF constellations

Larger number of RF measurements

Device Re-configuration

More Complex Test Programs to do different testing per site

New Packaging

Ability to do a complete test at probe

System Level Test capability for stacked die

Mapping Physical and electrical defects

Power Supply Stability Example

Test Flow

Site 1 Site 2

QUALITY OF TEST (QOT) – TECHNICAL CHALLENGES



DC CHALLENGES

• Supply Voltage levels will continue to decrease

• New test requirements for power supplies to be stable and accurate

• Need very critical DIB PI simulation and design process

QOT - ITRS SEMICONDUCTOR ROADMAP FOR GATE LENGTH AND SUPPLY VOLTAGE

• AP requires many supplies• Core supplies

• IO Supplies

• Requirements are very different

• Core: Accuracy, dynamic performance

• IO: Wider voltage range, more connections

TEST QUALITY - DC POWER VDD ACCURACY & DROOP

All device supplies will have some momentary “droop” when scan patterns are started.

Too large a “droop” will cause good parts to fail, reducing yield

Power Supply Stability Example

...

Single Supply Solution

Ganged Solution

Network Processor Example



RF CHALLENGES

• Increase Demand for Higher Data Rate & Connectivity• Overall mobile data traffic is expected to grow at a 61% CAGR to 15.9 Exabytes per

month by 2018

• Migration to LTE-Advanced occurring in all market segment (high and low end)

• New standards require 2x-3x more active RF device ports

• Demand for higher performance and high site count test capability

• Internet-of-things driving rapid growthof MCU + RF segment

• Shrinking Device Size While Increasing Complexity

• Mobile IC’s moving away from conventional package to wafer-level package technologies (Flip-chip, WLCSP, FOWLP)

WIRELESS INDUSTRY TRENDS

LTE TEST CHALLENGES – MODULATION QUALITY

• When Testing an RF Device, we want to measure how much the signal is corrupted by things like:

• Phase Noise• Signal Imbalance• Other noise and distortion

• All of these errors are combined into Error Vector Magnitude. It is a clear way to measure RF signal quality

• To do production testing, the EVM of the tester must be much better than the Device Under Test

Ideal Signal

Measured Signal

Test Limit

LTE Base Station = 13.5%LTE User Equip 12.5%

802.11ac = 11.22%LTE Base Station = 9.0%

802.11ac = 3.98% 802.11ac = 2.51%

16-QAM802.11a/g, LTE

64-QAM802.11a/g/n; LTE-A

256-QAM802.11 ac

- Device Spec Limit

0 50 100

150

200

250

300

350

400

450

500

0

1

2

3

4

5

6

7I and Q Timing Skew effects on EVM

802.11ac 160M 256QAM

LTE-Adv 100M 64 QAM

802.11ac 80M 256QAM

802.11ac 80M QPSK

802.11ac 40M 256QAM

LTE 20M 64QAM

% E

VM

802.11ac 160MEVM Limit = 2.51%

• The plot below shows the effects of IQ skew Imbalances (modulation signals being out of phase)

• If testing an actual device, the skew, gain and other distortion would contribute to the EVM error.

EXAMPLE OF HOW TESTER ERRORS BECOME MORE CRITICAL FOR NEW RF STANDARDS

LTE 20M

LTE-A 100M

Skew

Tester with 1-2% EVM Test Capability

802.11ac 160M

Tester with 0.5% EVM Test Capability

Can’t Test!X

Good Test

Margin



HIGH SPEED INTERFACE CHALLENGES

JEDEC DATA

• Extremely difficult timing Accuracy Requirements

• DDR3 Used DFT functions to validate

• DDR4 may be too difficult for DFT

• Might require production test with ATE to guarantee spec

LPDDR3 AND DDR4 SPECS

LP-DDR3 (After leveling)

LP-DDR4

DDR TEST STRATEGIES

Test Strategy ATE Solution

Pros Cons DUT DFT Required

Low

CostAt-speed

Test

System Level Test

Does Timing Tests

Complex DIB

Site-to-site Correlation problems

Drive / Compare Predictable data

Loopback on byte to another

Don’t Change Frequency

Keep Clock Running

Extend Latency

Loopback

DC Levels/ static Logic Low Cost DC Option

DRAM on DIB DRAM(s) on DIB

Internal Loopback NA ?

External Loopback

Loopback to 1100Mbps

Unclocked loopback to 2200Mbps on subset of pins

DIB Board Switching

Protocol Aware DDR Protocol Aware

Stored Patterns

Digital pattern test with source synchronous capability

High Speed Digital Option

Very Little

DFT Needed

• High Speed Serial Challenges• Maintain signal integrity from

Instrument to DUT

• Support rapid increases in serial data rates

• 2013: 16Gbps• 2014: 28+Gbps• 2015: 45Gbps / MultiLevel

• Minimize tester capital investment

• Maximize tester capital useful life

• Test Strategy• Support high pin count interfaces with standard

tester instrument

• Develop Re-useable IP than can be implemented on DIBs or DIB modules

• Deliver solutions as • Turnkey applications• Vendor-designed and manufactured hardware only

• Custom hardware made by ATE vendor, 3rd Party or HiSilicon (under license)

HIGH SPEED SERIAL TEST

Advantages

• No need to buy new Tester Options – much lower cost

• Minimizes signal path to DUT for best signal quality and device yield

• Simplifies DIB by eliminating matching circuitry

• Can be customized easily

ITRS Data Rate Forecast

• New PAM (Pulse Amplitude Modulation) Standard is coming

• Targeted for 2015• PAM4 @ 16Gsym/s

• PAM8 @ 16Gsym/s

• Similar technology used on Hard Disk Drive and LAN devices

• Module-Based Solution will allow a solution quickly and inexpensively

FUTURE STANDARDS

40

Prober

TOWERLESS PROBE FOR TSV AND BUMPED DIE

ProberProbe Card

PIB

Probe tower

Standard Prober Docking Towerless Prober Docking

Tester

Probe Card

Standard Prober Docking

Instrument PIBProbe Tower

Probe Card

Probe Head

pogos pogos Solder pads Probe Needlesinterposer

InstrumentProbe Card

Probe Head

Solder pads Probe Needles

Towerless Prober Docking

interposer

Probe Head

Probe Head

Advantages:-Higher signal fidelity-Lower tooling costs-Better planarity with chuck

Tester

CONCLUSION

• Cost of TestATE Capital Program developmentMultisite and Concurrent testPattern Oriented TestDFT dependent test solutions

• Time To MarketSW and debugging toolsAdaptive testingProtocol Aware

• Test Quality DC accuracy and powerRF AC speed and skewHigh speed IODirect Wafer Probing


Q&A

Jin-Soo Ko

Highbrand building 10’th floor,YangJa, SeoCho, Seoul Korea

[email protected]

FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014...

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Transcript of FUTURE IC TEST CHALLENGES QUALITY, COST AND TIME TO MARKET Korea test conference workshop 2014...