CSE 422 page 1

FPGA: Field Programmable Gate FPGA: Field Programmable Gate ArrayArray

Yann-Hang Lee

CSE 422 page 2

The Next Step of PALThe Next Step of PAL

So far, have only talked about PALs (see 22V10 figure next page).

What is the next step in the evolution of PLDs?More gates!

How do we get more gates? We could put several PALs on one chip and put an interconnection matrix between them!!This is called a Complex PLD (CPLD).

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Example: 22V10 PLDExample: 22V10 PLD

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Cypress CPLD

Each logic block is similar to a 22V10.

Programmable interconnect matrix.

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Any other approaches?Any other approaches?

Another approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them:

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Field Programmable Gate ArraysField Programmable Gate Arrays

The FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them.

What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”. A primitive gate like a NAND gate A 2/1 mux (this happens to be a complete logic family) A Lookup table (I.e, 16x1 lookup table can implement any 4

input logic function). Often combine one of the above with a D-FF to form the primitive

logic element.

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Altera Flex 10K FPGA Family

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Dedicated memory

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What is FPGAWhat is FPGA

Field Programmable Gate Arrays Array of logic cells connected via routing channels Special I/O cells logic cells are mainly LUT with associated registers interconnection on SRAM basis or antifuse elements Architecting a FPGA

Performance Density and capacity Ease of use In-system programmability and in-circuit reprogrammability

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Technology and Architecture Technology and Architecture TradeoffsTradeoffs

Antifuse elements high density non volatile not reprogrammable

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Technology and Architecture TradeoffsTechnology and Architecture Tradeoffs

SRAM cells uses more space reconfigurable volatile, requires PROM

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Other FPGA featuresOther FPGA features

Besides primitive logic elements and programmable routing, some FPGA families add other features

Embedded memoryMany hardware applications need memory for data

storage. Many FPGAs include blocks of RAM for this purpose

Dedicated logic for carry generation, or other arithmetic functions

Phase locked loops for clock synchronization, division, multiplication.

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Programmable Logic Device FamiliesProgrammable Logic Device Families

Source: DataquestLogic

StandardLogic

ASIC

ProgrammableLogic Devices(PLDs)

GateArrays

Cell-BasedICs

Full CustomICs

CPLDsSPLDs(PALs) FPGAs

AcronymsSPLD = Simple Prog. Logic Device PAL = Prog. Array of LogicCPLD = Complex PLDFPGA = Field Prog. Gate Array

Common ResourcesConfigurable Logic Blocks

(CLB) Memory Look-Up

Table AND-OR planes Simple gates

Input / Output Blocks (IOB) Bidirectional,

latches, inverters, pullup/pulldowns

Interconnect or Routing Local, internal

feedback, and global

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CPLDs and FPGAsCPLDs and FPGAs

Architecture PAL/22V10-like Gate array-likeMore Combinational More Registers + RAM

Density Low-to-medium Medium-to-high 0.5-10K logic gates 1K to 500K system gates

Performance Predictable timing Application dependent Up to 200 MHz today Up to 135MHz today

Interconnect “Crossbar” Incremental Not shown: Simple PLD (SPLD) Architecture

Complex Programmable Logic Device Field-Programmable Gate Array

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XC9500 CPLDsXC9500 CPLDs

• 5 volt in-system programmable (ISP) CPLDs

• 5 ns pin-to-pin• 36 to 288 macrocells

(6400 gates)• Industry’s best pin-

locking architecture• 10,000

program/erase cycles• Complete IEEE

1149.1 JTAG capability

Function

Block 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock 4

3

Global Tri-

States 2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECT

Switch Matrix

JTAG Port

3

I/O

I/O

Global Set/Res

et

Global Clocks

I/OBlocks

1

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XC4000 Architecture

CLB

CLB

CLB

CLB

SwitchMatrix

ProgrammableInterconnect I/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

OutputBuffer

InputBuffer

Q D

Pad

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

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• Nov. 1997- shipping world’s largest FPGA, XC40125XV (10,982 logic cells, 250K System Gates)

• 1 Logic cell = 4-input LUT + FF• 175,000 Logic cells = 2.0 M logic gates in 2001

Year

Logic Cells Logic Gates

1,000

10,000

100,000

1,000,000

1994 1996 1998 2000 2002

12M

1.2M

120K

12K

2 Million logic gates2 Million logic gates

D Q

FFLUT

Exponential Growth in DensityExponential Growth in Density

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XC4000E/X Configurable Logic BlocksXC4000E/X Configurable Logic Blocks

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'G'

H'

DIN

F'G'

H'

DIN

F'

G'H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

2 Four-input function generators (Look Up Tables)- 16x1 RAM or Logic function

2 Registers- Each can be configured as Flip Flop or Latch- Independent clock polarity- Synchronous and asynchronous Set/Reset

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Look Up TablesLook Up Tables

Capacity is limited by number of inputs, not complexity

Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB

Example:

A B C D Z

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up TableCombinatorial Logic

AB

CD

Z

4-bit address

GFunc.Gen.

G4G3G2G1

WE

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XC4000X I/O Block DiagramXC4000X I/O Block Diagram

Shaded areas are not included in XC4000E family.

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Xilinx FPGA RoutingXilinx FPGA Routing

1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix

3) Long Lines Segmented across chip Global clocks, lowest skew 2 Tri-states per CLB for

busses Other routing types in CPLDs

and XC6200

CLBCLB

CLBCLB

CLBCLB

CLBCLB

SwitchMatrix

SwitchMatrix

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Other FPGA ResourcesOther FPGA Resources

Tri-state buffers for busses (BUFT’s) Global clock & high speed buffers

(BUFG’s) Wide Decoders (DECODEx) Internal Oscillator (OSC4) Global Reset to all Flip-Flops, Latches

(STARTUP) CLB special resources

Fast Carry logic built into CLBsSynchronous Dual Port RAMBoundary Scan

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What’s Really In that Chip?What’s Really In that Chip?

CLB(Red)

Switch Matrix

Long Lines(Purple)

Direct Interconnect (Green)

Routed Wires (Blue)

Programmable Interconnect Points, PIPs (White)

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XC4000XC4000XC4000

3

Design Entry in schematic, ABEL, VHDL, and/or Verilog. Vendors include Synopsys, Aldec (Xilinx Foundation), Mentor, Cadence, Viewlogic, and 35 others.

Implementation includes Placement & Routing and bitstream generation using Xilinx’s M1 Technology. Also, analyze timing, view layout, and more.

Download directly to the Xilinxhardware device(s) with

unlimited reconfigurations* !!

1

2

*XC9500 has 10,000 write/erase cycles

M1 Technology

Design FlowDesign Flow

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Foundation Series Foundation Series Delivers Value & Ease of UseDelivers Value & Ease of Use Complete, ready-to-use software

solution Simple, easy-to-use design

environment Easy-to-learn schematic, state-

diagram, ABEL, VHDL, & Verilog design

Synopsys FPGA Express Integration*

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Xilinx Spartan/XL Series FPGAsXilinx Spartan/XL Series FPGAs

Similar to 4000’s, except --- Synchronous RAM only

No RAM16X1, RAM32X1 (asynchronous) Only RAM16(32)X1S, RAM16X1D

No Edge Decoders (wide AND of I/Os) No DECODEx

BUFTs for Muxes only No WANDx or WOR2AND

Serial configuration modes only No master parallel or peripheral

Mode pins for configuration only Not usable as I/O No MD0, MD1, MD2

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Spartan/XL Family BenefitsSpartan/XL Family Benefits

Standard 5V and 3V supplies3V Spartan-XL devices are 5V tolerant

Lowest power Xilinx FPGA familySpartan-XL K factor is 11Spartan-XL family adds power down pin

50 uA typical

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ChipCombines 3.3 V operation with 0.25 benefits

Spartan-XL Family Spartan-XL Family Advanced 0.35m ProcessAdvanced 0.35m Process

Transistor gates 0.35 Allows 3.3 V supply

All other features 0.25Small sizeLow capacitancePerformanceLow power

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Any 5 V

device

Spartan-XL FPGAAdvanced 0.35

3.3V Core3.3V I/O

5V3.3V

5V

3.3VMeets TTL

Levels

Spartan-XL Family Voltage CompatibilitySpartan-XL Family Voltage Compatibility

Spartan-XL inputs accept 5V signals Spartan-XL outputs drive standard TTL 100% compatible in 5 volt environment

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Spartan/XL Top-Level ArchitectureSpartan/XL Top-Level Architecture

• Based on XC4000 Architecture

• Logic is implemented in CLBs

• IOBs provide the interface between internal signals and package pins

• Routing channels provide paths to interconnect the inputs and outputs of CLBs and IOBs

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Spartan CLBSpartan CLB

Two 4-input LUTs and one

3-input LUT Two edge-

triggered FFs

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Spartan IOBSpartan IOB

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Single-Port RAMSingle-Port RAM

Synchronous write, asynchronous read 16 x 2 or 32 x 1 max per CLB

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Dual-Port RAMDual-Port RAM

One common synchronous write port

Two asynchronous read ports

16 x 1 max per CLB

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New Features in Spartan-XL New Features in Spartan-XL FamilyFamily Higher speed (-4/-5) 8 flexible global low-skew buffers (BUFGLS) CLB latches Input Fast Capture Latch Output multiplexer or lookup table 3.3V supply for low power with 5V tolerance

Programmable 3V input clamp for 3V PCIProgrammable 24 mA output drive for 5V PCI

Power-down pin Improved boundary scan Express parallel configuration mode

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Xilinx FPGA Family SummariesXilinx FPGA Family Summaries

Virtex Family SRAM Based Largest device has 1M gates Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2

DFFs Four onboard Delay Locked Loops (DLLs) for clock

synchronization Dedicated RAM blocks (LUTs can also function as RAM). Fast Carry Logic

XC4000 and Spartan Families Previous version of Virtex No DLLs, No dedicated RAM blocks

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Issues in FPGA TechnologiesIssues in FPGA Technologies

Complexity of Logic ElementHow many inputs/outputs for the logic element?Does the basic logic element contain a FF? What type?

InterconnectHow fast is it? Does it offer ‘high speed’ paths that cross

the chip? How many of these?Can I have on-chip tri-state busses?How routable is the design? If 95% of the logic elements

are used, can I route the design?More routing means more routability, but less room

for logic elements

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Issues in FPGA Technologies Issues in FPGA Technologies (cont)(cont) Macro elements

Are there SRAM blocks? Is the SRAM dual ported? Is there fast adder support (i.e. fast carry chains?) Is there fast logic support (i.e. cascade chains)What other types of macro blocks are available (fast

decoders? register files? ) Clock support

How many global clocks can I have?Are there any on-chip Phase Logic Loops (PLLs) or

Delay Locked Loops (DLLs) for clock synchronization, clock multiplication?

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Issues in FPGA Technologies Issues in FPGA Technologies (cont)(cont) What type of IO support do I have?

TTL, CMOS are a given Support for mixed 5V, 3.3v IOs?

3.3 v internal, but 5V tolerant inputs? Support for new low voltage signaling standards?

GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II HSTL - High Speed Transceiver Logic SSTL - Stub Series-Terminate Logic USB - IO used for Universal Serial Bus (differential signaling) AGP - IO used for Advanced Graphics Port

Maximum number of IO? Package types? Ball Grid Array (BGA) for high density IO