FE Electronics - Overview

ASDTDC

L0 BufferL1 Buffer

bias L0 BX L150 fC

DAQ

counting room

~100m

FE Electronics on the detector

GOL

Electronics Service Box

LVHV TFC ECS Cooling

U.Uwer EDR, June 11, 2003

TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)TQ-distribox

TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)

Fibers to L1 Buffer

Fibers to L1 BufferFibers to L1 Buffer

Fibers to L1 Buffer

TrackerQuadrant

TQ-distribox TQ-distribox

TQ-distribox

ASDBLR

OTIS

GOL

ASDBLR

OTIS

HV boards

ASDBLR ASDBLR

LV Reg

L1

TFC ECS LVHV

Module End:

128 channels

16 ASDBLR chips

4 OTIS TDC chips

1 optical link: 1.28 Gbit/s

Outer Tracker: ST1…3

56000 channels

432 optical links

tot. dose < 10krad

X 1

X 2

X 4X 8

Front-end cards:• have to fit inside a closed

metal shielding box: 25 x 30 x 4 cm

• excellent ground connection to straw-tubes and module reference ground

• power dissipation of cards is about 22 W / box → water cooling

• easy access should be maintained

GOL/Aux Board

TDC boards

HV boardsASD boards

Front-end electronics box: How it fits together

module support

bar

Feed-through board

cooling barcooling plates and blocks

plates of shielding box

Mock-up of Electronics Box

GOL Auxiliary Board

ALU

Gas

Carbon / epoxy skin

Kapton foil for gas tightness

Alu coating shield

GLUE (isolating)

Alu coating shield

Conductive Kapton

Conductive Kapton

Module Interface: Feed-Through Board

Connector:To HV board

R=560kΩ

C=330pF

HV Boards

32 channels per board

Capacitors embedded in PCB:

Capacitors:

JOHANSON 302R29W331KV4E

Max. Volt.: 4kV

Size: 4.6 x 2 x 1.5 mm3

eventual. used as fuse

Z=300ΩZ=300Ω1)

1) Z=150Ω at high frequencies + 150Ω in series

Board Currents Temperature and Humidity

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97

Series1

Series2

Series3

Series4

Series5

Series6

Series7

Series8

Series9

Series10

Series11

Series12

Series13

Series14

Series15

Series16

Series17

Series18

Series19

Series20

Series21

Series22

Long term tests:

19 boards = 608 channels

1. HV = +2.5 KV, t = 14 days

→ I (32 cha) < 50 nA

→ 1 failing cap

I (mA)

14 days

Humidity: 45%

T=21oC

2. Temperature cycling:

every hour 25-65oC

HV = +2.5 KV, t = 14 days

→ 1 failing cap

More studies needed

ASDBLRASDBLR

88

88

ASDBLRASDBLR

88

32

1616

88

84 2 4

OTIS

data

data data

datadata

I2C addr power

power power

powerpower

clk/trig/rst

termterm filter 3.3 2.5 +3

+3+3

+3 +3

-3

-3-3

-3 -3

refref refref

ref ref

refref

tpls

tpls tpls

tplstpls

testpulsetestpulse

min.42 pinsconnector

min.38 pinsconnector

ASD board:

ASDBLR Chip

ATLAS DMILL version 02

TDC board:• radiation hard OTIS TDC chip

• provides bias voltage for ASD

• power rooting for ASDBLR card

• test pulses for ASDBLR

joining ATLAS chip order

building first BGA prototype

Components:• 32 maskable channels • DLL, HitRegister, PrePipeline: 6 bit drift time encoding: 1 bit ↔ 0.39 ns (req. resolut. < 1ns)

playback data feed-in (testing)• Pipeline, Derandomizing Buffer:

buffer length: 160 evts ↔ 4.0 μs• Control Algorithm:

Memory and trigger management,2 read-out modes: 1, 2, 3 BX/evt

• I2C Slow Control Interface:Programming, ASD bias setting

• DAC: ASD-Chip bias

OTIS TDC Chip

0.25 μm CMOS technology

PowerUp Reset as expected

Power Consumption 550mW

DLL: Lock Time 1µs

Lock Lost not observed

DAC as expected

Slow Control as expected

Fast Control: Memory, Data

Output, Debug Features no errors found

Memory Selftest timing problems

Drift Time Encoding timing problems

DLL Lock Range 25-60 MHz @ 300K

10-90°C @ 40 MHz

DLL Lock Time 1µs

DLL DNL 0,54 ns

OTIS1.0 Status

understood

Chip Review 05/06/03

Outer Tracker Electronics: Time Schedule

2004 20052003

07/03 Validation of OTIS baseline

01/04 Delivery of OTIS1.1

06/04 Pre-series finished: start mounting

01/05 Delivery of OTIS1.2

03/05 Start Mass Prod

03/04 Start pre-series production