FE Electronics - Overview

U.Uwer Electronics Review, April 22, 2004

ASDTDC

L0 BufferL1 Buffer

bias L0 BX L1200 fC

DAQ

counting room

~100m

FE Electronics on the detector

GOL

Electronics Service Box

LVHV TFC ECS Cooling

TT

T1 T2 T3

ITOT

6 m

5 m

LHCb Outer Tracker

Straw Tube Drift Chamber

• 5mm diameter straw tubes, single straw tube length ~2.5m

• ArCO2 / ArCO2CF4

• max. drift times ~44ns

• max. occupancy ~ 7% (MC study)

• 56k channels

264 Module

L0 Requirements:

• Max. L0 trigger rate is 1.1 MHz

• Max. readout time /event is 900 ns

• L0 buffer with 160 events (4.0 s)

Straw Module

Cathode

64 Straws

5mm

64 Straws

Grounding tongues

X 2

Module Interface to FE Electronics:

ALU

Gas

Carbon / epoxy skin

Kapton foil for gas tightness

Alu coating shieldGLUE (isolating)

Alu coating shieldConductive Kapton Conductive Kapton

Connector:To HV board

Feed-through boarddefines ground ref.

ASDBLR

OTIS

GOL

ASDBLR

OTIS

HV boards

ASDBLR ASDBLR

LV Reg

L1

TFC ECS LVHV

Outer Tracker: ST1…3

56000 channels

432 optical links

tot. dose < 10krad TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)

TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)

Fibers to L1 Buffer

Fibers to L1 BufferFibers to L1 Buffer

Fibers to L1 Buffer

Module End:

128 channels

16 ASDBLR chips

4 OTIS TDC chips

1 optical link: 1.6 Gbit/s

FE Electronics

FE Box

Front-end cards:• have to fit inside the closed

shielded FE box: 25 x 30 x 4 cm

• excellent ground connection to straw-tubes and module reference ground

• power dissipation of cards is about 25 W / box → water cooling

• easy access should be maintained

GOL/Aux Board

TDC boards

HV boards

ASD boards

X 1

X 4

X 2

X 8

HV Board:

Capacitors:

JOHANSON 302R29W331KV4E

Max. Volt.: 4kV

Size: 4.6 x 2 x 1.5 mm3

R=1 MΩ

C=330pF

Z=316Ω

• 32 channels / board

• Compact capacitors

• Operation in air

casting/embedding of caps

ASDBLRASDBLR

88

88

ASDBLRASDBLR

88

32

1616

88

84 2 4

OTIS

data

data data

datadata

I2C addr power

power power

powerpower

clk/trig/rst

termterm filter 3.3 2.5 +3

+3+3

+3 +3

-3

-3-3

-3 -3

refref refref

ref ref

refref

tpls

tpls tpls

tplstpls

testpulsetestpulse

min.42 pinsconnector

min.38 pinsconnector

ASD board:

ASDBLR Chip

ATLAS DMILL version

TDC board:• radiation hard OTIS TDC chip

• provides bias voltage for ASD

• power rooting for ASDBLR card

• test pulses for ASDBLR

joined ATLAS chip order

28 wafers à1042 chips

Components:• 32 maskable channels • DLL, HitRegister, PrePipeline: 6 bit drift time encoding:

playback data feed-in (testing)• Pipeline, Derandomizing Buffer:

buffer length: 160 evts ↔ 4.0 μs• Control Algorithm:

2 read-out modes: 1, 2, 3 BX/evt• I2C Slow Control Interface:

Programming, ASD bias setting• DAC: ASD-Chip bias

OTIS TDC Chip

Status:• OTIS 1.0 in 2002 • Chip Review in June 2003• OTIS 1.1 received in Feb 2004• Submission of OTIS 1.2 in May

(final chip)

GOL Auxiliary Board

Connected to 4 OTIS boards

Deserialization of OTIS data using CERN GOL serializer chip

Electrical / optical connections to front-end electronics

• Optical data link

• Low voltage connections

• Slow-Control connections

• Fast-control (TFC) connection

Voltage (power) regulation

Testing optical data transmission, development of readout test system

FE Electronics BoxMounting against water cooled plate

FE Electronics Box

Detector curtain

SlaveService Box

SlaveService Box

MasterService Box

HV, LV = copper

TFC, Data, SPECS = fiber

Overlap

Slack-space for TFC cables

TFCMonitor

HVDistribution Box

FiberDistribution Box

LVDistribution Box

I2C

Ground plane

Off-DetectorFiber Patch Panel

TFC

ECS

DATA

For one Detector curtain:4 x 12 fiber ribbon1 x single TTC fiber1 x double ECS fiber6 x single LV cable 95mm23 x 48 conductor shielded HV cable

For the total detector:54 ribbon fibers (12)72 LV cables 95mm2

36 multiwire HV cables

Cavern Counting Room

Services and Distribution Boxes

Low

/ H

igh

Vol

tage

sup

plie

s,

L1 B

uffe

r

Need Component Status

432 Front-End Box Tested.

1728 HV Board Prototype series in production

3465 ASDBLR Board Testing; new version in preparation

1728 OTIS Board Testing; new version in preparation

432 GOL/Aux Board Tested; new version in preparation

6912 ASDBLR Chip Produced, awaiting delivery

1728 OTIS Chip Submitting OTIS 1.2 (final version)

Summary and Status of FEE Components

Currently preparing ¼ station system test foreseen for Oct 2004:

Equip 9 modules with electronics: ~2300 channels (18 FE boxes)

Outer Tracker Electronics: Time Schedule

2005 20062004

05/04 Submission of OTIS 1.2

09/04 Delivery of OTIS 1.2

10/04 Pre-series finished, start system test

12/05 Submission of OTIS engineering run

03/05 Start mass production of front-end boards

06/04 Order pre-series of full electronics for system test

01/06 Start electr. assembly

06/05 OTIS chips from engineering run