Fabrication and Characterization of Thin-Film Transistor Materials and Devices

AN ABSTRACT OF THE DISSERTATION OF

David Hong for the degree of Doctor of Philosophy in

Electrical and Computer Engineering presented on November 5, 2008.

Title: Fabrication and Characterization of Thin-film Transistor Materials and Devices.

Abstract approved:

John F. Wager

A class of inorganic thin-film transistor (TFT) semiconductor materials has emerged in-

volving oxides composed of post-transitional cations with (n-1)d10ns0 (n≥4) electronic

configurations. This thesis is devoted to the pursuit of topics involving the development

of these materials for TFT applications: Deposition of zinc oxide and zinc tin oxide semi-

conductor layers via reactive sputtering from a metal target, and the characterization of

indium gallium zinc oxide (IGZO)-based TFTs utilizing various insulator materials as the

gate dielectric.

The first topic involves the deposition of oxide semiconductor layers via reactive

sputtering from a metal target. Two oxide semiconductors are utilized for fabricating

TFTs via reactive sputtering from a metal target: zinc oxide and zinc tin oxide. With

optimized processing parameters, zinc oxide and zinc tin oxide via this deposition method

exhibit similar characteristics to TFTs fabricated via sputtering from a ceramic target.

Additionally the effects of gate capacitance density and gate dielectric material are

explored utilizing TFTs with IGZO as the semiconductor layers. IGZO-based TFTs ex-

hibit ideal behavior with improved TFT performance such as higher current drive at a

given overvoltage, a decrease in the subthreshold swing, and a decrease in the magni-

tude of the turn-on voltage. Additionally it is shown that silicon dioxide is the preferred

dielectric material, with silicon nitride a poor choice for oxide-based TFTs.

Finally a simple method to characterize the band tail state distribution near the con-

duction band minimum of a semiconductor by analyzing two-terminal current-voltage

characteristics of a TFT with a floating gate is presented. The characteristics trap en-

ergy (ET ) as a function of post-deposition annealing temperature is shown to correlate

very well with IGZO TFT performance, with a lower value of ET , corresponding to a

more abrupt distribution of band tail states, correlating with improved TFT mobility. It is

shown that as the post-deposition anneal temperature increases, the total number of band

tail states does not change significantly, however the energy distribution of these states

approaches that of a crystalline material.

c©Copyright by David Hong

November 5, 2008

All Rights Reserved

Fabrication and Characterization of Thin-film Transistor Materials and Devices

by

David Hong

A DISSERTATION

submitted to

Oregon State University

in partial fulfillment ofthe requirements for the

degree of

Doctor of Philosophy

Presented November 5, 2008Commencement June 2009

Doctor of Philosophy dissertation of David Hong presented on November 5, 2008

APPROVED:

Major Professor, representing Electrical and Computer Engineering

Director of the School of Electrical Engineering and Computer Science

Dean of the Graduate School

I understand that my dissertation will become part of the permanent collection of OregonState University libraries. My signature below authorizes release of my dissertation toany reader upon request.

David Hong, Author

ACKNOWLEDGMENTS

I would like to thank my family for their support and encouragement throughout

my education and life. They have instilled in me a work ethic and ambition that has led

me this far.

I would also like to thank all of my friends and coworkers who have contributed

greatly during my graduate program. Several key people are Dr. Hai Chiang and Dr.

Jeff Bender, who have been great resources for encouragement and cromulent insight

into many topics as well as a great sounding board for my bizarre ideas. Professor John

”The Bossman” Wager has provided great direction and discussion as well as an endless

supply of enthusiasm and energy. Chris Tasker provided a work ethic to follow, as well

as great direction and support in and outside of the cleanroom. Additionally, Manfred

Dittrich has provided exceptional fabrication work and mechanical knowledge as well as

great discussions ranging from politics and religion to football and the proper usage of

threading taps.

A number of industry people deserve acknowledgements. Two specific people I

would like to mention are Randy Hoffman, inventor of the inorganic transparent thin-film

transistor, and Greg Herman, both of whom have been great resources. In addition to

providing many of the substrates used for this dissertation, they have provided a high

level of discussion and I am grateful for their time and energy.

This work was supported by the Hewlett-Packard Company, the Defense Advanced

Research Projects Agency (MEMS/NEMS: Science and Technology Fundamentals), the

United States Display Consortium, and the NSF (IGERT grant no. 0549503).

To the optimist the glass is half full.

To the pessimist the glass is half empty.

To the engineer, the glass is twice as big as it needs to be.

-unknown

TABLE OF CONTENTS

Page

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. OXIDE SEMICONDUCTORS AND THIN-FILM TRANSISTORS . . . . . . . . . 4

2.1 Oxide semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.1 Transparent conducting oxides overview . . . . . . . . . . . . . . . . . . . . . . . 42.1.2 Zinc oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.3 Amorphous oxide semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.4 Zinc tin oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.5 Indium gallium zinc oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Oxide semiconductor devices: Thin-film transistors . . . . . . . . . . . . . . . . . . . 14

2.2.1 Thin-film transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2 Oxide semiconductor-based thin-film transistors . . . . . . . . . . . . . . . . 16

2.2.2.1 TFTs with simple oxide layers: ZnO . . . . . . . . . . . . . . . . . . . 162.2.2.2 TFTs with simple oxide layers: In2O3, SnO2, Ga2O3 . . . 202.2.2.3 TFTs with multicomponent oxide layers: ZTO . . . . . . . . . 212.2.2.4 TFTs with multicomponent oxide layers: ZIO . . . . . . . . . . 232.2.2.5 TFTs with multicomponent oxide layers: IGO . . . . . . . . . 252.2.2.6 TFTs with multicomponent oxide layers: IGZO . . . . . . . . 26

2.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3. TFT FABRICATION AND CHARACTERIZATION . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Thin-film deposition and processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.1 Evaporation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.1.2 Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.1.3 Plasma-enhanced chemical vapor deposition (PECVD) . . . . . . . . . 343.1.4 Atomic layer deposition (ALD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.1.5 Post-deposition thermal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2 Hall measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3 Thin-film transistor fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TABLE OF CONTENTS (Continued)

Page

3.3.1 Fully-transparent TTFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.3.2 Non-transparent TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4 Transistor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 Thin-film transistor device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5.1 DC current-voltage measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.5.2 Threshold voltage and turn-on voltage . . . . . . . . . . . . . . . . . . . . . . . . . 483.5.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.5.4 Drain current swing and drain current on-to-off ratio . . . . . . . . . . . . 57

3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4. REACTIVE SPUTTERING OF OXIDE SEMICONDUCTORS . . . . . . . . . . . . 60

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.2 Reactive Zinc Oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.3 Reactive Zinc Tin Oxide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5. THIN-FILM TRANSISTOR DIELECTRIC PERFORMANCE . . . . . . . . . . . . . 76

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.2 Experimental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3 Chemical Vapor Deposited (CVD) Silicon Dioxide . . . . . . . . . . . . . . . . . . . 79

5.4 Silicon Dioxide, Aluminum Oxide, and Silicon Nitride . . . . . . . . . . . . . . . 88

5.5 Silane and Tetraethyl Orthosilicate (TEOS)-based CVD . . . . . . . . . . . . . . . 98

TABLE OF CONTENTS (Continued)

Page

5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6. OXIDE SEMICONDUCTOR THIN-FILM TRANSISTOR TWO-TERMINALASSESSMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.2 Experimental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3 Transistor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.4 Metal-Semiconductor-Metal Current-Voltage Characteristics . . . . . . . . . . 104

6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7. CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK . . . . 1147.0.1 Recommendations for future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LIST OF FIGURES

Figure Page

3.1 TFT structures used for the research discussed in this thesis, including(a) fully-transparent thin-film transistor and (b) non-transparent thin-film transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2 (a)The basic structure of a TFT and corresponding energy band dia-grams as viewed through the gate for several biasing conditions: (b)equilibrium, (c) VGS <0 V, and (d) VGS >0 V . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3 Four general thin-film transistor configurations, including: (a) stag-gered bottom-gate, (b) coplanar bottom-gate, (c) staggered top-gate,and (d) coplanar top-gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.4 Simplified timing diagram illustrating the applied voltage to the tran-sistor as a function of time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.5 Output conductance-gate-to-source voltage (gD-VGS) characteristic il-lustrating threshold voltage estimation via extrapolation of the linearportion of this curve to the VGS-axis intercept for an indium galliumzinc oxide semiconductor layer TFT with a width-to-length ratio of10:1. gD is assessed at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.6 Log(ID-VGS) transfer characteristics showing the turn-on voltage, VON ,and the threshold voltage, VT for the same device as shown in Fig. 3.5.The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.7 Extracted average mobility (middle-black,) saturation mobility (top-dark gray,) and saturation-average mobility (bottom-light gray) char-acteristics for a single IGZO-based thin-film transistor. . . . . . . . . . . . . . . . . 56

3.8 Log(ID-VGS) transfer characteristics showing the drain current swing,S, and the drain current on-to-off ratio, ION−OFF

D for the same deviceas shown in Fig. 3.5. The TFT is measured at VDS = 30 V. . . . . . . . . . . . . . 58

4.1 Cross sectional and plan view of a typical bottom-gate TFT. . . . . . . . . . . . . 62

4.2 Drain current-drain voltage (ID-VDS) characteristics of a zinc oxideTFT which is fabricated near room temperature, i.e., without inten-tional substrate heating. VGS is decreased from 40 V (top curve, show-ing maximum current) to 0 V in 10 V steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.3 Incremental mobility-gate voltage characteristics of a zinc oxide TFTwhich is fabricated near room temperature, i.e., without intentionalsubstrate heating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

LIST OF FIGURES (Continued)

Figure Page

4.4 Log(ID)−VGS characteristics obtained at VDS = 40 V for two zinc tinoxide TFTs fabricated via reactive rf sputtering which are subjected toa 300 C and 500 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.5 Incremental mobility as a function of oxygen partial pressure for zinctin oxide TFTs which are subjected to a 300 C and 500 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.6 Log(ID)−VGS characteristics obtained at VDS = 40 V for two zinc tinoxide TFTs fabricated via reactive dc sputtering which are subjected toa 300 C and 500 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.7 DC bias on the target as a function of oxygen partial pressure at a con-stant sputtering pressure of 30 mTorr and constant power of 50 W. Aforward sweep (increasing oxygen partial pressure), backward sweep(decreasing oxygen partial pressure), and the region of optimal zinc tinoxide deposition are shown.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.1 Simplified cross-sectional view of the device structure used for thischapter. SiO2 is deposited via PECVD from a silane source, the gateelectrode stack and IGZO are deposited via magnetron sputtering, andaluminum pads are deposited via thermal evaporation. . . . . . . . . . . . . . . . . . 78

5.2 Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizingthermally grown silicon dioxide and CVD grown silicon dioxide asthe gate insulator. The IGZO semiconductor layer is post-depositionannealed in air at 500 C. (inset) ID-VGS transfer characteristics for thesame devices, plotted on a linear scale. The TFTs are measured at VDS= 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3 Extracted incremental mobility characteristics for IGZO-based TFTsutilizing thermally grown silicon dioxide and PECVD grown silicondioxide as the gate insulator. The IGZO semiconductor layer is post-deposition annealed in air at 500 C. at 500 , as shown in Fig. 5.2. . . . . 81

5.4 Log(ID-VGS−VON) transfer characteristics for IGZO-based TFTs uti-lizing various thicknesses of silicon dioxide as the gate insulator. AllTFTs are measured at VDS = 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.5 Extracted incremental mobility µINC as a function of gate-to-sourcevoltage for IGZO-based TFTs utilizing various thicknesses of CVDsilicon dioxide as the gate insulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84


Figure Page

5.6 Extracted turn-on-voltage VON as a function of CVD silicon dioxidethickness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.7 Subthreshold swing as a function of CVD silicon dioxide thicknesssfor IGZO-based TFTs annealed at 300 C and 500 C The interfacestate density for each annealing temperature is also indicated.. . . . . . . . . . 87

5.8 Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizingthermally grown silicon dioxide as the gate insulator. The TFT is mea-sured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.9 Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizingCVD silicon dioxide as the gate insulator. The TFT is measured atVDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.10 Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizingALD deposited aluminum oxide:titanium oxide as the gate insulator.The TFT is measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.11 Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizingALD deposited aluminum oxide:titanium oxide as the gate insulator.For this TFT, the aluminum oxide:titanium oxide is annealed to 500 Cprior to the semiconductor deposition, and the TFT stack is annealedat 300 C after the semiconductor deposition. The TFT is measured atVDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.12 Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizingCVD deposited silicon nitride as the gate insulator. The TFT is mea-sured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.13 Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizingthermal silicon dioxide, CVD deposited silicon dioxide from a silane(SiH4) precursor and CVD via a TEOS (SiC8H20O4) precursor. TheTFTs are measured at VDS = 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.1 Cross sectional view of the test structure used for this chapter. Thesilicon and silicon dioxide constitute the gate electrode and gate di-electric, respectively. The aluminum pads are the source/drain contactsand indium gallium zinc oxide (IGZO) constitutes the semiconductorlayer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102


Figure Page

6.2 Log(ID)-VGS transfer characteristics obtained at VDS = 30 V for anIGZO TFT post-deposition annealed at 300 C. (inset) Drain current-drain voltage (ID-VDS) output characteristics for the same device. VGSis decreased from 30 V (top curve, showing maximum current) to 0 Vin 10 V steps. Note that the VGS = 10 V and 0 V curves overlap withthe x-axis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3 Current-voltage characteristics for an IGZO TFT operated as a two-terminal M-S-M (Al-IGZO-Al) device. Voltage is applied to the drainwith the source grounded for two situations: with the gate electrodefloating and with VGS = 0 V. The IGZO TFT employed is subjected toa 300 C post-deposition anneal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.4 Current-voltage characteristics of four IGZO TFTs operated as two-terminal M-S-M (Al-IGZO-Al). Voltage is applied to the drain with thesource grounded and the gate electrode floating. Four different post-deposition anneal temperatures (300(diamond), 400(square), 500(tri-angle), 600(X) C) are shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.5 Estimated band tail state density distribution (Nt(E)) near the conduc-tion band minimum for IGZO annealed at 300, 400, 500, 600 C. . . . . . . . 110

6.6 Estimated band tail state density distribution (Nt(E)) near the conduc-tion band minimum for IGZO annealed at 300, 400, 500, 600 C as-suming a constant value of N0 for all annealing temperatures. . . . . . . . . . . 112

LIST OF TABLES

Table Page

2.1 Typical properties of various n-type transparent conducting oxide semi-conductors. Eopt

g represents the optical band gap, χ represents the elec-tron affinity, T represents the percentage transmitted in the visible por-tion of the electromagnetic spectrum, m∗/me represents the density ofstates effective mass, µH represents the Hall mobility, n represents thecarrier concentration, and ρ represents the resistivity. . . . . . . . . . . . . . . . . . . . 7

6.1 A summary of IGZO TFT properties for various post-deposition annealtemperatures. Incremental mobility µINC and turn-on voltage (VON)are obtained from three-terminal TFT assessment while space-charge-limited parameters, i.e., characteristic trap energy and temperature, ETand Tt , total trap density, Nt , trap concentration per unit energy eval-uated at the conduction band minimum, N0, are obtained from two-terminal measurements between the source and drain with the gatefloating. The following values are used in the estimation of Nt andN0: NC = 5.0 × 1018 cm−3, µ = 20 cm2V−1s−1, and εS = 1.0 × 10−10

Fcm−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

FABRICATION AND CHARACTERIZATION OF THIN-FILM TRANSISTORMATERIALS AND DEVICES

1. INTRODUCTION

Oxide semiconductors composed of post-transition cations with (n-1)d10ns0 (n≥4)

electronic configurations, such as zinc tin oxide, constitute an interesting class of materi-

als since they are often transparent in the visible portion of the electromagnetic spectrum

as a result of their large band gaps (> 3.0 eV), yet also possess relatively high electron

mobilities in spite of their amorphous character. [1, 2, 3] When employed as a semicon-

ductor layer in TFT applications, such materials, namely zinc oxide, zinc tin oxide, zinc

indium oxide, and indium gallium zinc oxide, have yielded high-performance thin-film

transistors (TFTs). [4, 5, 6, 7, 8]

Research within this area of oxide electronics has ballooned in recent years, specif-

ically with regard towards the commercialization of oxide-based electronics for use in

display technology. [9, 10, 11, 12] These reports primarily focus on the process opti-

mization of the oxide semiconductor for use in TFTs, showing that oxygen content in

the ambient during deposition and processing temperature are the key factors affecting

TFT performance. [9, 13, 14, 15] Additionally several reports have included demon-

stration vehicles utilizing oxide-based electronics for use in OLED and E-ink displays.

Recently at the 2008 Society of Information Display conference, a 12.1 inch OLED dis-

play was demonstrated by Samsung SDI that used IGZO-based TFTs as the active matrix

2

backplane. Functional devices have also been fabricated on plastic substrates for flexi-

ble electronic applications. [16, 12] Furthermore, issues such as TFT bias stress stability

[17, 18, 19, 20] short channel effects [21], light sensitivity [22] and contact resistance

[12, 18] have been explored.

In addition to display control elements, several other applications have been hy-

pothesized. Depending on deposition conditions, these oxide semiconductors can show

sensitivity to humidity or specific gases which make them applicable as sensors. [23, 24,

25, 26] Additionally due to their high performance and ability to be built upon each other

in a vertical arrangement, oxide-based TFTs are possible sense and control elements for

high density memory applications. [21]

Three primary goals are pursued in this thesis, all related to the development of

oxide based TFTs or TTFTs: processing parameter effects on reactive sputtering of zinc

oxide and zinc tin oxide are explored, TFT characteristics as a function of gate capac-

itance density are evaluated, and the material choice for use as the gate dielectric are

explored.

The structure of this thesis is as follows. Chapter 2 contains a review of the per-

tinent literature and provides the technical background necessary to establish a context

within which experimental results can be discussed. Chapter 3 provides a description of

important fabrication tools and techniques employed, followed by a discussion of TFT

operation and relevant electrical TFT characterization methodology and figure-of-merits.

Chapter 4 is devoted to evaluation of processing parameter effects on reactively sputtered

zinc oxide and zinc tin oxide. Chapter 5 presents a study evaluating TFT performance

3

utilizing indium gallium zinc oxide as the semiconductor layer with varying thicknesses

of silicon dioxide and various materials as the gate dielectric. Chapter 6 presents an anal-

ysis of band tail state distribution in IGZO semiconductor after post-deposition anneals at

various temperatures. Finally, Chapter 7 contains conclusions and recommendations for

future work.

4

2. OXIDE SEMICONDUCTORS AND THIN-FILM TRANSISTORS

This chapter first provides an overview of oxide semiconductors. Then, the mor-

phology and properties of several oxide semiconductors (zinc oxide, zinc tin oxide (ZTO)

and indium gallium zinc oxide (IGZO) are discussed in more detail, as they are used

extensively in this work. Finally, the electrical properties of several oxide semiconductor-

based TFTs are reviewed.

2.1 Oxide semiconductors

This section first summarizes the properties of well-known degenerate oxide semi-

conductors or transparent conducting oxides (TCOs). Then, several oxide semiconductors

(zinc oxide, ZTO, and IGZO) are discussed in more detail, as they are used extensively in

this work.

2.1.1 Transparent conducting oxides overview

Transparent conducting oxides (TCOs) constitutes a class of materials which ex-

hibit a large band gap (typically Eg ≥ 3.1 eV, due to the large electronegativity of oxygen

in n-TCOs [27]), rendering them highly transparent (80-90%) in the optical portion of the

electromagnetic spectrum, as well as high conductivity.

In these materials, n-type conduction is derived from two sources: the creation of

point defects (such as oxygen vacancies and/or metal interstitials) or extrinsic substitu-

tional doping (typically on the cation site). The prototypical TCO is zinc oxide, in which

5

case the point defect is due to either oxygen vacancies or zinc interstitials. In the case

of an oxygen vacancy, two valence band sites are not present, therefore the two electrons

that would have occupied those sites now occupy conduction band sites and the lattice

point corresponding to the oxygen vacancy is left with a localized 2+ charge. In the al-

ternative case of a zinc interstitial, a zinc neutral residing on an interstitial site is reduced

to a more thermodynamically stable 2+ state in the process donating two electrons to the

conduction band. Zinc oxide can also be extrinsically doped, typically with an aluminum

ion on a zinc site. In this case, a 3+ aluminum sits on a 2+ site, resulting in one additional

electron in the conduction band and a localized 1+ site.

Typically point defect concentrations can be modified during the deposition pro-

cess by appropriate selection of processing parameters or by subjecting the sample to an

oxidizing or reducing post-deposition anneal. The drawbacks of using intrinsic defects as

the primary source of conduction are the possibility of film re-oxidation and (typically)

lower conductivity compared to extrinsically doped films.

The minimum theoretical resistivity limit for n-type TCOs has been predicted by

Bellingham et al. as 4 × 10−5 Ω·cm. [28] This limit is a consequence of transport that is

constrained by ionized impurity scattering (µ < 90 cm2V−1s−1) and carrier concentration

limitations due to increasing optical reflection with increasing carrier concentration (n <

2 × 1021 cm−3 for >90% optical transmission). Experimental results for single crystal

In2O3:Sn have approached this theoretical resistivity limit, yielding a minimum resistivity

of ∼7.7×10−5 Ω·cm (µ = 42 cm2V−1s−1, n = 1.9 × 1021 cm−3). [29]

6

TCOs are currently utilized in a number of passive applications, including thin-film

solar cells and flat-panel displays. SnO2 is commonly employed in applications where

patterning is not required (as SnO2 is difficult to chemically wet etch) and when high lev-

els of conductivity are not required. Of the commercially available TCOs, In2O3:Sn is the

most conductive. In2O3:Sn is also easier to etch than SnO2 and can be deposited at lower

temperatures. Unfortunately, the availability of indium is limited, as it is a byproduct of

mining ores for other metals (such as zinc and lead). [30] Moreover, indium is not as

abundant as other metals; there is ∼ 1000 times more zinc (132 ppm) than indium (0.1

ppm) in the earth’s crust. [31, 32] Thus, efforts are being made to find a suitable replace-

ment for In2O3:Sn. Among the materials being explored is ZnO:Al, which is attractive

for its ease of etchability, stability in a hydrogen plasma, and low process temperature

requirement. [33, 34]

Table 2.1 summarizes optical and physical properties of various n-type TCOs. The

tabulated electron affinity, χ, is the difference between the vacuum level and conduction

band minimum and is assumed to be approximately equal to the work function (the differ-

ence between the vacuum level and the Fermi level) for these degenerate semiconductors.

Also note that two TCOs, CuInO2 and ZnO, exhibit bipolar conductivity. A summary of

p-type TCOs can be found elsewhere. [35]

7

Tabl

e2.

1:Ty

pica

lpro

pert

ies

ofva

riou

sn-

type

tran

spar

entc

ondu

ctin

gox

ide

sem

icon

duct

ors.

Eop

tg

repr

esen

tsth

eop

tical

band

gap,

χre

pres

ents

the

elec

tron

affin

ity,T

repr

esen

tsth

epe

rcen

tage

tran

smitt

edin

the

visi

ble

port

ion

ofth

eel

ectr

omag

netic

spec

trum

,m∗ /

me

repr

esen

tsth

ede

nsity

ofst

ates

effe

ctiv

em

ass,

µ Hre

pres

ents

the

Hal

lmob

ility

,nre

pres

ents

the

carr

ierc

once

ntra

tion,

and

ρre

pres

ents

the

resi

stiv

ity.

Mat

eria

lE

opt

gχ

Tm∗ /

me

µ Hn

ρR

efer

ence

s(e

V)

(eV

)(%

)(c

m2 V

−1se

c−1 )

(cm

3 )(Ω·c

m)

CdO

2.2-

2.6

750.

18-0

.25

220

1019

-1021

2x10−3

[31,

36]

CuA

lO3.

494.

2660

-70

101x

1018

1[3

7]C

d 2Sn

O4

2.9-

3.1

900.

29-0

.42

35-6

01-

7x10

201.

4-12

x10−

4[3

1,38

,39,

40]

In2O

33.

73.

780

-90

0.35

10-4

0≤

1021

≥10−4

[32,

40,4

1]In

GaO

33.

35.

490

1010

202.

5x10−3

[42,

43]

InG

aZnO

43.

580

-90

0.2

24∼

1020

2x10−3

[44,

45,4

6]Sn

O2

3.6

4.5

80-9

00.

23l ,0

.30t

5-30

≤10

20≥

10−3

[32,

40,4

7]Z

nO†

3.2-

3.3

4.5-

580

-90

0.27

5-50

≤10

21≥

10−4

[32,

40,4

3]Ti

1−X

Nb X

O2

3.2

950.

410

2-40

x1020

2x10−4

[48]

Zn 2

In2O

52.

94.

980

12-2

02.

4-5x

1020

1-4x

10−3

[39,

43,4

9]Z

nSnO

33.

55.

380

7-12

1020

4-5x

10−3

[43,

50,5

1]Z

n 2Sn

O4

3.3-

3.9

900.

16-0

.26

12-2

66-

30x1

0181-

5x10−2

[39,

52,5

3]

†Bip

olar

cond

uctiv

em

ater

ial[

54,5

5,56

]l

Lon

gitu

dina

leff

ectiv

em

ass

tTr

ansv

erse

effe

ctiv

em

ass

8

2.1.2 Zinc oxide

Zinc oxide is one of the most widely used oxide semiconductors. In addition to

its utilization as a TCO material, zinc oxide is used in many health care products due to

its absorption of the UV portion of the electromagnetic spectrum, light-emitting devices,

as well as ceramic-based varistors. The optical band gap for zinc oxide is reported to be

between 3.1 and 3.3 eV. Zinc oxide is typically polycrystalline, with a wurtzite structure

and preferential grain growth in the c-axis direction (normal to the substrate), even on

amorphous substrates.

ZnO thin films have been deposited using a number of methods, including reactive

sputtering (DC [57], RF [58], ion beam [19]), activated reactive evaporation (ARE) [59],

spray pyrolysis [60], metalorganic chemical vapor deposition (MOCVD) [61], and elec-

trochemical reaction [62]. More recently zinc oxide thin films have been fabricated from

solution-based precursors. [63, 64, 65] In these films a solution is spin-coated onto the

substrate and annealed to drive off the solvent.

Zinc oxide is typically an n-type semiconductor, due to an inherent nature of form-

ing an oxygen deficient film. However, recent reports have claimed that p-type doping of

the material can be achieved. A high degree of n-type conductivity (> 5000 Ω−1cm−1)

is attainable in zinc oxide, due to intrinsic defects, intentional donor doping (Al, In, Ga,

B, F) or a combination thereof. Reported thin-film Hall electron mobilities are typically

>20 to 30 cm2V−1s−1; the maximum mobility obtainable in ZnO single crystals is >200

cm2V−1s−1. There is not a consensus in the literature as to which intrinsic defect (O

vacancy or Zn interstitial) is responsible for intrinsic n-type conductivity. P-type conduc-

9

tivity has not been convincingly or reproducibly demonstrated, although compensation of

n-type doping through the introduction of acceptor impurities is possible. This difficulty

in obtaining p-type ZnO is attributed to the phenomenon of self-compensation. [35]

2.1.3 Amorphous oxide semiconductors

Amorphous oxides composed of post-transition metal cations with (n-1)d10ns0,

where n≥4, electronic configurations constitute an interesting subcategory of transparent

conductors, since they possess relatively high electron mobilities despite their amorphous

character. [66, 67, 68] Examples of such materials include indium oxide doped with tin

(ITO) [69] and zinc tin oxide [70] for which amorphous-state mobilities as large as 40 and

30 cm2V−1s−1, respectively, have been reported. Such high mobilities in an amorphous

material are likely a consequence of a conduction band primarily derived from spherically

symmetric, post-transition metal cation ns orbitals. Such orbitals have large radii, leading

to a high degree of overlap between adjacent orbitals and considerable band dispersion.

Moreover, the spherical symmetry of an s orbital makes delocalized electronic transport

less sensitive to local and extended structural order as compared with band formation

from anisotropic p or d orbitals. Furthermore, compared to binary oxide semiconductors,

multicomponent oxide semiconductors increase the likelihood that the structure will re-

main amorphous over a wide range of processing conditions. Zinc tin oxide and indium

gallium zinc oxide are discussed below, as these materials are used extensively in this

work.

10

2.1.4 Zinc tin oxide

Zinc tin oxide (ZTO), which is sometimes referred to as zinc stannate, has recently

received attention as an alternative TCO. Zinc tin oxide is most generally described as,

(ZnO)x(SnO2)1−x, where 0 < x < 1. There are two crystalline forms of ZTO, trigonal il-

menite (ZnSnO3, x = 0.5) [71] and spinel (Zn2SnO4, x = 0.66) [52]. As shown by Shen et

al., powder mixtures with stoichiometry close to trigonal ilmenite ZTO (ZnSnO3) decom-

pose to spinel ZTO (dizinc tin oxide, i.e. Zn2SnO4) and SnO2 at calcination temperatures

above 700C. [72] Several aspects that make ZTO attractive are its low-cost nature (as

zinc and tin are readily available materials), its chemical and electrical stability in highly

concentrated (> 35%) HCl solutions and its physical robustness, [50, 53] i.e., no damage

to the thin film is visually apparent after scratching with the corner of a razor blade.

The zinc tin oxide phase space has been examined by Moriga et al. using dc co-

sputtering from a ZnO and SnO2:Sb (Sb2O5) target. [73] For temperatures up to 350 C,

films with 0.33≤ x≤ 0.66 were found to be amorphous. These amorphous films exhibit a

constant Hall mobility of ∼ 10 cm2V−1s−1. The carrier concentration decreases linearly

as the Zn concentration is increased from x = 0.33 (ZnSn2O5) to 0.66 (Zn2SnO4). The

minimum resistivity is 4 × 10−2 Ωcm and occurs at x = 0.33.

Other authors have shown that crystalline spinel ZTO (Zn2SnO4) thin films are

attainable through the use of a variety of deposition techniques, including electron beam

evaporation, [74] rf magnetron sputtering, [39, 52, 53, 75, 76] chemical vapor deposition,

[53, 77] and spray pyrolysis [23]. In actuality, rf magnetron sputtered Zn2SnO4 has been

11

found to have an inverse spinel structure, in which half of the Zn cations exchange sites

with Sn cations. [53, 75]

Optical and electrical properties of crystalline ZTO are tabulated in Table 2.1.

Spinel ZTO is a direct band gap material with a fundamental band gap of 3.35 eV. Spinel

ZTO exhibits a pronounced Burstein-Moss shift. Concomitant with the Burstein-Moss

shift is a small relative electron effective mass (0.16me). Thus, one would expect the

mobility to be quite large since mobility is inversely proportional to the effective mass,

i.e.,

µ =qτm∗ , (2.1)

where τ is the relaxation time and m∗ the effective mass. However, the maximum mea-

sured Hall mobility for a rf magnetron sputtered thin-film is only 26 cm2V−1sec−1. Thin

films fabricated to date have been limited by intra-grain defects due to atomic disorder,

which may not be alleviated even in single crystal growth. [52, 53, 75]

Applications of ZTO have been somewhat limited due to its low conductivity, but

ZTO has been employed in thin-film solar cell applications [78] and humidity and gas

sensors [23, 24, 25, 26].

2.1.5 Indium gallium zinc oxide

Indium gallium zinc oxide (IGZO) is a wide band gap (∼3.5 eV), n-type semi-

conductors; its stoichiometry can be generally described as In2xGa2−2x(ZnO)k, where

0 < x < 1 and k is an integer that is greater than 0. [46, 44, 45, 79, 80, 81, 82, 83] Single

crystal indium gallium zinc oxide is composed of alternating layers of InO−2 and GaZnO+

4 ;

12

the In3+ ion has octahedral coordination, the Ga3+ ion has pentagonal coordination, and

the Zn2+ has tetragonal coordination. [45, 79, 80] Several groups have synthesized bulk

samples with varying stoichiometry (both x and k) to appraise the solubility limits of the

structure. [79, 80] The intriguing result is that, regardless of k, when x = 0.5 (equal pro-

portions of In and Ga) the structure is preserved. In other words, x = 0.5 constitutes the

base compound where all the In3+ ions are in the InO−2 and all the Ga3+ ions are in the

GaZnO+4 layer.

For k ≤ 3, the conductivity decreases as k is increased. This trend is observed in

both bulk samples [80] and thin films [81], indicating that the conductivity of indium

gallium zinc oxide is primarily associated with the In 5s states. However, for k ≥ 4, the

fraction of Zn becomes increasingly large and Zn begins to contribute to conduction. [81]

Considering orbital overlap interaction and comparing the ionic radii of cations in the

IGZO system is useful for understanding the shift in the conduction path. The ionic radii

of Ga, In, and Zn are 1.27, 1.49, and 1.54 A, respectively. As the ionic radii of In and Zn

are quite similar, it is not surprising that Zn contributes to conduction as the fraction of

Zn becomes increasingly large. [81]

The structure of single crystal and amorphous InGaZnO4 thin films (∼250 nm) are

examined using extended x-ray absorption fine structure (EXAFS), which is commonly

employed to appraise short range order. [46, 84, 85] The nearest-neighbor distances for

In-O, Ga-O, and Zn-O in the amorphous film are 0.211, 0.200, and 0.195 nm, respec-

tively. This short range ordering is similar to that of the single crystal structure (0.218,

0.193, and 0.193, respectively). However, it appears that medium range ordering (second

13

nearest-neighbor distances) near the Ga and Zn ions is lost in the amorphous films. Ab

initio calculations were performed and are in good agreement with the EXAFS results.

Additional calculations show that the In-In second nearest-neighbor coordination number

in the amorphous state varies with distance (i.e., ∼ 1 to ∼ 4 for distances of 0.32 to ∼ 0.4

nm) and is significantly lower than in the crystalline structure, which has a coordination

number of ∼ 6. This indicates that the selective (medium range) coordination of In-In is

lost in the amorphous structure. From the experimental and calculated results, the coor-

dination numbers of In-O, Ga-O, and Zn-O are deduced to be 5, 5, and 4, respectively.

Finally, pseudoband calculations show that the conduction band minimum is composed

of In 5s (consistent with the experimental results discussed in the previous paragraph) and

that that amorphous IGZO has an isotropic effective mass of ∼ 0.2me.

Amorphous IGZO has been employed in a light-emitting pn heterojunction. [86]

The IGZO layer is deposited by pulsed laser deposition (PLD) at room temperature. The

carrier concentration and mobility of this layer is 1 × 1019 cm−3 and 5 cm2V−1s−1. In-

dium gallium zinc oxide is chosen here for its reasonable conductivity at low processing

temperatures and its large band gap (∼3.5 eV). Blue emission (∼ 430 nm peak) is ob-

served from this pn heterojunction and is due to intrinsic exciton recombination in the

single crystal p-LaCuOSe layer (which has a band gap, carrier concentration, and mobil-

ity of ∼2.8 eV, 1 × 1019 cm−3, and 8 cm2V−1s−1, respectively).

14

2.2 Oxide semiconductor devices: Thin-film transistors

As the primary goal of this work is to explore oxide semiconductor-based TFTs

a summary of oxide semiconductor-based TFTs is given. A discussion of TFT opera-

tion and figure-of-merits is included in Chapter 3. As the work in this field is rapidly

increasing, only the most noteworthy works are reviewed here.

2.2.1 Thin-film transistors

Invention of the first field-effect device is often credited to J. E. Lilienfeld, who

patented the concept in 1934. [87] However, development of the first thin-film transistor

(TFT), as it is known today, is credited to P. K. Weimer (1962). [88] These initial n-

type TFTs fabricated by Weimer used a top-gate staggered structure with microcrystalline

CdS deposited via evaporation as the channel layer. Thermally evaporated SiO (silicon

monoxide) was used as the gate dielectric and gold for the gate electrode and source and

drain contacts. All patterning was done via shadow masks, channel lengths of 5 to 50

microns were achieved. These early devices exhibited field-effect mobilities on the order

of 1.1 cm2V−1s−1 and drain current on-to-off ratios of 101.

Since Weimer’s initial work, TFTs based on a wide variety of channel materials,

including CdS, CdSe, amorphous and polycrystalline silicon, have been developed. Cur-

rently, the most dominant TFT technology is based on hydrogenated amorphous silicon

(a-Si:H), which are commonly employed as control circuitry in active-matrix liquid crys-

tal displays (AMLCDs). High performance a-Si:H TFTs typically have field-effect mobil-

15

ities of approximately 1.5 to 2.0 cm2V−1sec−1 with a maximum processing temperature

of 300C. [89]

A route towards silicon-based TFTs utilizing single crystal silicon has been demon-

strated by Menard et al. [90] Beginning with a silicon-on-insulator wafer, micro and

nano-scale patterns are etched within the silicon and released from the insulator layer.

These micro and nano-sized silicon particles are suspended in an organic solution and

subsequently transferred and cured onto a plastic substrate. TFTs fabricated utilizing this

process are n-channel and exhibit mobilities as large as 120 cm2V−1s−1 and VON of -5

V. Multiple circuits have been implemented utilizing this technology: inverters exhibit a

gain of 2.6 at a supply voltage of 3 V, 5 stage ring oscillator exhibit a frequency of ∼8

MHz at a supply voltage of 4 V, and a differential amplifier consisting of a differential

pair, current source and current mirror. [91]

In addition to silicon TFTs, another class of TFTs consists of those which employ

organic materials as the channel layer. [92] These materials exhibit mobilities of 10−3-1

cm2V−1s−1. However, the low mobility of these organic TFTs is offset by the low cost

of deposition, such as spin coating or printing. In addition, the processing temperature

of these devices is below 300C, allowing for deposition onto plastic substrates. Most

of these organic channel materials are p-type. However, an n-type organic TFT has been

demonstrated using an organic channel layer. [93] This n-type organic TFT demonstrated

mobilities of up to 0.1 cm2V−1s−1.

Augmenting organic TFTs, combinations of organics and inorganics, referred to as

hybrid materials, have also been explored for TFT applications. [94] Hybrid materials

16

use a mixture of organic and inorganic chemicals to attain desired physical and chemical

properties. TFTs made from a tin(II) iodide perovskite, (C6H5C2H4NH3)2SnI4, have been

fabricated with incremental mobilities of ∼ 0.61 cm2V−1s−1.

2.2.2 Oxide semiconductor-based thin-film transistors

Since the introduction of oxide semiconductor-based thin-film transistors in 2003,

a wide variety of n-type oxide materials have been employed for the semiconductor

layer. These materials include several simple oxides (ZnO, SnO2, and In2O3) and sev-

eral amorphous multicomponent oxides (ZTO, zinc indium oxide(ZIO), indium gallium

oxide (IGO), and IGZO). The scope of this research includes discrete TFT performance,

circuit integration (ring oscillators), and integration with other technologies (e-ink, liq-

uid crystals, and organic light-emitting diodes). The following subsection does not detail

each work. Instead, the general properties associated with each oxide semiconductor and

the most noteworthy work is highlighted. References are provided for those interested in

obtaining additional information.

2.2.2.1 TFTs with simple oxide layers: ZnO

ZnO was the first and most widely employed oxide semiconductor for TFTs, with

over 10 institutions publishing reports on its use. [95, 15, 96, 97, 4, 98, 99, 100, 101,

102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 63] These reports employ a vari-

ety of deposition techniques for fabrication, including rf sputtering, ion beam sputtering,

solution-based deposition, and pulsed laser deposition (PLD).

17

The initial reports of ZnO-based TFTs by Masuda et al. and Hoffman et al. in 2003

ignited the research of transparent TFTs. These devices were fabricated with different

deposition methods (PLD and ion beam sputtering) and utilized fairly high temperature

processing (450 - 700 C). These devices utilized either atomic layer deposited aluminum

oxide:titanium oxide or plasma enhanced chemical vapor deposited silicon nitride. The

resultant devices exhibited drain current on-to-off ratios (Ion−o f fD ) up to 107 and channel

mobilities in the range of 0.01 to 2.5 cm2V−1s−1. Additionally, ambient light had little

effect on device performance.

More recently, several authors have explored ZnO-based TFTs with rf sputtering

that do not require intentional post-deposition annealing treatments. [98, 102] It is inter-

esting to note that these authors successfully implement drastically different deposition

parameters for forming their ZnO layers (high pressure/low power and low pressure/high

power for Carcia et al. and Fortunato et al., respectively). In these cases, e-beam evap-

orated aluminum oxide and atomic layer deposited aluminum oxide:titanium oxide are

used as the gate dielectrics. The electrical properties of ZnO-based TFTs are shown to be

strongly influenced by the O2 partial pressure in the deposition ambient; TFTs with mo-

bilities approaching 25 cm2V−1s−1 were demonstrated. Additionally, ZnO-based TFTs

on flexible polyimide substrates were also demonstrated. [98]

Solution-based deposition techniques, including spin coating and chemical bath de-

position have been employed to fabricate ZnO-based TFTs. [63, 64, 65] The reports using

spin-coating employ a high temperature post-deposition anneal to attain adequate crystal-

lization and device performance. Norris et al. spin a zinc nitrate precursor solution (zinc

18

nitrate hexahydrate and glycine) and anneal at 700 C. The channel mobility and Ion−o f fD

of these devices is ∼0.2 cm2V−1s−1 and 107, respectively. [63] Lee et al. incorporate

zirconium isopropoxide in their sol-gel precursor to suppress the free carrier density of

their films. Spin-coated Zn0.97Zr0.03O TFTs annealed at 500 C exhibited channel mobil-

ities, VT , and Ion−o f fD of ∼0.3 cm2V−1s−1, 4.7 V, and 106, respectively. [64] Cheng et al.

utilize a chemical bath containing zinc nitrate and dimethylamineborane at 60 C to grow

ZnO films. TFTs fabricated with these films exhibited channel mobilities and Ion−o f fD of

∼0.25 cm2V−1s−1 and 105, respectively. [65]

Contributions enhancing the understanding of oxide-based TFT operation have been

made by Hossain et al. and Hoffman. [97, 4] Hossain et al. analyze grain boundary ef-

fects (modeled as a two-sided Schottky barrier) for polycrystalline ZnO TFTs. These

simulations show a decrease in grain boundary barrier height with increasing free carrier

concentration and a decrease in channel mobility as the number of grain boundaries in

the channel increases. Hoffman explains the intricacies of mobility extraction and dis-

cusses mobility characteristics of ZnO-based TFTs. Understanding mobility extraction is

essential to this work and is discussed in detail in Sec.3.4.3.

Cross et al. report the bias-stress stability of zinc oxide based TFTs. [20] Bias-

stress instabilities are caused by two different mechanisms. Low field instabilities are a

result of charge trapping at or near the dielectric-semiconductor interface concurrent with

negligible change in subthreshold swing characteristics. At higher fields, instabilities are

the result of trap-state creation concurrent with degraded subthreshold swing characteris-

tics. The demarkation between low-field stress and high-field stress is found to be ∼30

19

V for devices with 150 nm thick silicon dioxide as the gate dielectric, corresponding to

an applied electric field of 2 MVcm−1. The threshold voltage shifted in the direction of

the applied voltage, with a positive bias-stress inducing a positive shift and a negative

bias-stress inducing a negative shift.

Cross et al. report also on the bias-stress stability of zinc oxide based TFTs utilizing

either a silicon dioxide or a silicon nitride gate dielectric. In these cases the gate dielec-

tric is deposited via a high temperature process (>1000 C), with the semiconductor and

source and drain deposited at room temperature. In these devices, the bias stability exhib-

ited different characteristics, however silicon nitride appeared to exhibit better bias-stress

stability.

Levy et al. report on the fabrication of the gate dielectric and semiconductor layer

via atomic layer deposition. [113] Zinc oxide TFTs are fabricated with temperatures

below 200 C, exhibiting mobilities as high as 20 cm2V−1s−1 and no visible hystere-

sis. Additionally ring oscillators are demonstrated exhibiting 31 nS propagation delays

through each stage.

Hirao et al. and Park et al. have utilized ZnO-based TFTs in active-matrix dis-

plays. [103, 104] Hirao et al. have fabricated AMLCDs with staggered top-gate ZnO

TFTs which utilize a SiNx gate insulator. These TFTs exhibit a channel mobility of ∼50

cm2V−1s−1. Park et al. have fabricated a transparent AMOLED display with coplanar

bottom-gate ZnO TFTs which utilize an Al2O3 gate insulator. Additionally, the ZnO

deposition process utilized by Park et al. is compatible with plastic substrates. These dis-

20

play prototypes show that ZnO TFTs can be integrated into useful applications and that

multiple ZnO TFTs can operate simultaneously.

Yamauchi et al. report on fabrication of an integrated zinc oxide TFT-OLED device.

[114] Zinc oxide is deposited via sputtering. The OLED is deposited directly on the TFT

drain material (aluminum doped zinc oxide), such that the aluminum doped zinc oxide

constitutes both the drain for the TFT and electron injection material. When ITO is used

as the drain material/OLED contact, no luminance is detected indicating that zinc oxide

is necessary for electron injection.

2.2.2.2 TFTs with simple oxide layers: In2O3, SnO2, Ga2O3

SnO2 and In2O3 are not commonly employed as the TFT semiconductor layer due

to difficulty in suppressing/controlling the carrier concentration, which leads to highly

negative threshold voltages. To compensate for this, Presley et al. utilize extremely thin

semiconductor layers (10-20 nm) to control VT of SnO2-based TFTs. [115] Wang et al.

address this issue through the use of ion-assisted deposition, in which the carrier con-

centration of the layer is controlled (1017 to 1020 cm−3 in In2O3 films) by adjusting the

O2 partial pressure and ion beam power. Using this technique, In2O3-based TFTs with

organic self-assembled dielectrics were fabricated. [116]

Additionally, Ga2O3 is not commonly employed as a TFT semiconductor layer due

to low mobility values. Matsuzaki et al. report on polycrystalline Ga2O3-based TFTs

with field-effect mobilities of 0.05 cm2V−1s−1 at a processing temperature of 550 C.

21

[117, 118] At higher processing temperatures, the Ga2O3-based TFTs exhibited no field-

effect induced conduction, indicative of a high trap concentration.

2.2.2.3 TFTs with multicomponent oxide layers: ZTO

Zinc tin oxide (ZTO)-based TFTs have been fabricated using a wide variety of

methods, including rf sputtering, reactive dc sputtering, and plasma-assisted PLD. [13,

119, 17, 120, 12, 121] The initial ZTO-based TFTs (ZnSnO3) exhibited a channel mobil-

ity which approached 30 cm2V−1s−1 when subjected to a 600 C post-deposition anneal.

[13] Since this initial report, researchers have explored the effects of varying ZTO stoi-

chiometry [17, 120], integrated ZTO-based TFTs with transparent OLEDs, and demon-

strated flexible TFTs using ZTO.

The effects of stoichiometry and annealing on electrical characteristics of ZTO-

based TFTs were explored by Hoffman. [120] Sputter targets of varying stoichiometry

(Zn/(Zn + Sn) = 0.0, 0.33, 0.5, 0.67, and 1.0) were used for fabrication. The interme-

diate stoichiometries (Zn/(Zn + Sn) = 0.33, 0.5, and 0.67) and post-deposition anneal

temperatures (400-600 C) produced devices with broad peak mobilities (approaching

30 cm2V−1s−1). The turn-on voltage decreases with increasing anneal temperature and

decreasing ratios of Zn:Sn (with the inability to deplete any of the SnO2 devices).

Gorrn et al. explore the effect of stoichiometry (0.33 ≤ Zn/(Zn + Sn) ≤ 0.65) on

bias stress stability of ZTO-based TFTs. These devices were fabricated at 250−400 C

with plasma-assisted PLD. All transistors fabricated in this study exhibited minimal hys-

teresis and channel mobilities in the range of 5−14 cm2V−1s−1. A constant voltage bias

22

stress of 10 V is applied for 60 ks; the test is interrupted every 100 s to measure trans-

fer (ID−VGS) characteristics for threshold voltage and mobility extraction. Positive and

negative VT shifts with respect to bias stress time were observed. Positive shifts in VT

were accompanied by rigid shifts in the transfer characteristic, while negative shifts were

accompanied by non-rigid shifts in the transfer characteristic and degradation in the sub-

threshold slope. The relative change in channel mobility during testing for all devices is

less than 10% and does not correlate to the behavior of VT shifts. Zn/(Zn + Sn) = 0.36 re-

sulted in optimal performance; a threshold voltage shift of ∼ 30 mV and minimal change

in channel mobility is observed for this stoichiometry.

Gorrn et al. have studied the effects of illumination on the TFT performance of

ZTO-based TFTs. [22] Zinc tin oxide TFTs exhibit persistent photoconductivity in the

form of a negative threshold voltage shift, increased off current, and decreased mobility

when under illumination of 425 nm light at an intensity of 250 µWcm−2 which mimics

the effect of a blue LED. The effect of the illumination reached a steady state at ∼10

hours, while recovery back to initial device characteristics required ∼20 hours.

Gorrn et al. have integrated transparent ZTO-based TFTs with transparent OLEDs

as a first step towards a transparent display. [119] For this demonstration, the OLED is

fabricated atop the drain (which also serves as the cathode for the OLED) of the staggered

bottom-gate ZTO and SU-8 photoresist is used for pixel definition. The ZTO semiconduc-

tor layer is deposited by plasma-assisted PLD, with a maximum processing temperature of

150 C. The channel mobility and threshold voltage range of these TFTs is 11 cm2V−1s−1

and -1 to 1 V, respectively.

23

Jackson et al. fabricated staggered bottom-gate ZTO-based TFTs on flexible poly-

imide substrates. [12] These TFTs utilize a 375 nm thick SiON gate insulator. The ZTO

semiconductor is subjected to a 250 C post-deposition anneal for 10 minutes. The chan-

nel mobility and threshold voltage are 14 cm2V−1s−1 and -8 V, respectively. The authors

identify the threshold voltage and subthreshold slope as the characteristics which require

greatest improvement for their devices. The threshold voltage can be shifted towards 0

V by increasing the nitrogen content in the SiON layer or reducing oxygen deficiency

in the ZTO layer. The subthreshold slope is degraded by excess carriers (as indicated

from capacitance-voltage characteristics) and thus, can be improved by reducing oxygen

deficiency in the ZTO layer.

Sol-gel methods for deposition of zinc tin oxide was studied by Jeong et al. . [122]

These sol-gel deposited devices required a 500 C anneal to fabricate working TFTs. At

processing temperatures below 500 C, no field modulation is observed in the devices.

Optimal devices were fabricated with 30 molar percent of tin, exhibiting mobilities of ∼1

cm2V−1s−1 and turn-on voltage of ∼-2 V.

2.2.2.4 TFTs with multicomponent oxide layers: ZIO

Several researchers have explored various stoichiometries of zinc indium oxide

(ZIO) by rf sputtering for TFTs. [14, 123, 124, 125] ZIO TFTs typically exhibit high

channel mobilities (up to 40 cm2V−1s−1), but suffer from the same issue as In2O3 and

SnO2, namely difficulty in suppressing the carrier concentration. As a result, many of the

reported ZIO TFTs are “normally on” devices (ID > 0 at VGS = 0 V), i.e., depletion-mode

24

devices. It is important to note that VT is commonly reported and is thus used here for

comparison, but in many cases, significant current still flows below VT . An alternative

figure-of-merit, the turn-on voltage, is discussed in Sec. 3.4.2.

The initial report of ZIO-based (Zn2In2O5) TFTs employed a staggered bottom-

gate structure with an ALD Al2O3-TiO2 superlattice as the gate insulator. [14] Two types

of TFTs were reported, those which were subjected to a post-deposition anneal (300 and

600 C) and “room temperature” TFTs. TFTs subjected to a 300 C (600 C) exhibit a

channel mobility and VT in the ranges of 10−30 cm2V−1s−1 (45−55 cm2V−1s−1) and

0−10 V (-20 to -10 V), respectively. The authors contend that the positive values of VT

observed in devices annealed at 300 C are a consequence of deep traps present in the

channel and/or at the interface (which must be filled by application of a positive gate

voltage). TFTs not subjected to a post-deposition anneal exhibit a channel mobility of∼8

cm2V−1s−1.

Barquinha et al. and Yaglioglu et al. utilize room temperature In2O3 − 10 wt %ZnO

(sometimes referred to as IZO) as the semiconductor layer in staggered bottom-gate TFTs.

[124, 125] Barquinha et al. obtain channel mobilities approaching 40 cm2V−1s−1 while

exploring the effect of semiconductor thickness (15 to 65 nm) on device performance. VT

decreases with increasing semiconductor thickness (from 10 to 3 V); this effect is ascribed

to reduced sheet resistance for thicker films and a reduced effect from the back surface

(opposite to insulator-semiconductor interface), where carrier trapping may be possible.

Additionally, the channel mobility decreases with increasing semiconductor thickness (38

to 25 cm2V−1s−1); this is attributed to the longer source-drain path as the semiconductor

25

thickness is increased (recall that a staggered structure is employed). Yaglioglu et al.

observe a channel mobility and VT of ∼20 cm2V−1s−1 and -3.2 V, respectively, for their

TFTs which employ thermally grown SiO2 as the gate gate insulator. The carrier density

is estimated to be 2.1 × 1017 cm−3 using a standard van der Pauw setup.

Nakanotani et al have utilized ZIO in conjunction with p-type organics to fabricate

ambipolar TFTs. [126] These ambipolar devices exhibit field effect when applying both

positive and negative gate bias. Additionally, electroluminescence was observed in TFTs

utilizing ZIO and tetracene, with the intensity of the luminance controlled by the gate-to-

source voltage.

A route towards solution deposition of ZIO has been explored by Lee et al. [127]

Lee et al demonstrated that ZIO via inket printing is a viable option to realize the semi-

conductor layer for TFTs. These ZIO-based TFTs exhibit turn-on voltages of -25 V and

mobility of 7.4 cm2V−1s−1 after processing at 600 C.

2.2.2.5 TFTs with multicomponent oxide layers: IGO

Indium gallium oxide (IGO)-based TFTs were employed in transparent integrated

circuits (inverters and ring oscillators). [128] These TFTs used a 100 nm SiOx gate insu-

lator deposited by plasma-enhanced chemical vapor deposition (PECVD) and were pat-

terned using standard photolithography techniques. Post-deposition annealing at 500 C

resulted in TFTs with a channel mobility and turn-on voltage (discussed in Sec.3.4.2) of

∼7 cm2V−1s−1 and 2 V, respectively. The maximum oscillation frequency of the ring

oscillator circuit is ∼9.5 kHz (with 80 V supply voltage). The rather low oscillation

26

frequency is due to loading from large parasitic capacitances associated with each TFT

(∼142 nF/cm, 200 µm source/gate and drain/gate overlap). .

2.2.2.6 TFTs with multicomponent oxide layers: IGZO

Indium gallium zinc oxide (IGZO)-based TFTs have been fabricated by PLD and

rf sputtering. [129, 10, 16, 130, 131] The initial IGZO-based (InGaO3(ZnO)5) TFTs em-

ployed single crystalline IGZO layers, with indium oxide layers alternating with gallium

zinc oxide layer, which were obtained through the use of a high temperature anneal and

yttria-stabilized zirconia substrates. [129] These TFTs employ a coplanar top-gate struc-

ture with a 80 nm thick HfO2 gate insulator. The channel mobility, VT , and Ion−o f fD are

80 cm2V−1s−1, 3 V, and 106, respectively.

Yabuta et al. explored amorphous IGZO-based (InGaZnO4) TFTs with a staggered

top-gate structure. [130] rf sputtering is used for deposition of the semiconductor and

insulator (Y2O3) layers. While no intentional substrate heating is used, the maximum

processing temperature is 140 C due to heating from the sputtering process during insu-

lator deposition. The channel mobility, VT , and Ion−o f fD are ∼ 12 cm2V−1s−1, 1 V, and

108, respectively.

Iwasaki et al. explored the IGZO phase space for TFTs (which utilize a staggered

bottom-gate structure) using a combinatorial approach with rf co-sputtering from three

cathodes. With this experimental setup, the range of compositional variation is 10−70%

for each material. [131] Iwasaki et al. indicate that the optimal O2 partial pressure em-

ployed during deposition changes for different stoichiometries. A lower O2 partial pres-

27

sure is required to produce functioning TFTs (i.e., TFTs that switch from well-defined on

to off regions) when the Ga content of films increases. In contrast, a higher O2 partial

pressure is required to produce functioning TFTs when the In content of films increases.

In:Ga:Zn ratios of 37:13:50 resulted in the best performance, where the channel mobility,

VT , and Ion−o f fD are ∼ 12 cm2V−1s−1, 3 V, and 107, respectively.

Park et al. have formed TFTs via a self-aligned process. [132] In this process a top-

gate device is realized with 100 nm of CVD grown silicon dioxide as the gate insulator.

After patterning of the gate electrode and gate dielectric, the device is exposed to an argon

plasma, which dopes the exposed semiconductor region with oxygen vacancies, rendering

them conductive. These conductive semiconductor regions constitute the source and drain

regions. All processing is accomplished below 200 C.

Park et al. have also studied the affects of water on IGZO-based TFTs. [133] Two

competing effects are analyzed, for film thicker than 100 nm, water appears to act as an

electron donor, manifesting as a large negative threshold voltage shift. For films thinner

than 70 nm, water appears to act as an acceptor-like trap, manifesting as a large increase in

subthreshold swing characteristics. The mechanism for both electron donor and acceptor-

like trap appears to both be reversible.

Song et al. examine the short-channel effects of IGZO based TFTs. [21] IGZO-

based TFTs with source-to-drain separation of 50 nm are fabricated utilizing e-beam

lithography. IGZO-based TFTs for this study were built on silicon nitride and the TFT

stack is annealed in a nitrogen ambient at 300 C. These devices showed µINC of 8.2

cm2V−1s−1 and VON of -2 V. Varying the source-to-drain separation from 50 nm to 500

28

nm had minimal effects on the subthreshold swing and turn-on voltage. The drain current

however did not scale linearly with source-to-drain separation, and is attributed to the

effect of contact resistance.

Kim et al. have demonstrated a passivated IGZO TFT, utilizing a CVD silicon

dioxide as the passivation layer. The TFT stack prior to source and drain deposition

but including the passivation layer is annealed at 350 C. Devices with the passivation

layer exhibited a µINC of 36 cm2V−1s−1 and a VON of 0 V, however devices without the

passivation layer showed reduced performance due to damage during the source and drain

patterning.

Flexible IGZO-based TFTs (InGaZnO4) on 200 µm thick polyethylene terephtha-

late using a coplanar top-gate structure have been demonstrated by Nomura et al. [16] All

layers were deposited by PLD at room temperature, including the Y2O3 gate insulator.

The channel mobility, VT , and Ion−o f fD are ∼ 8 cm2V−1s−1, 1.6 V, and 103, respectively.

TFT characteristics were not significantly altered by bending. Additionally, the TFT is

stable up to 120 C.

IGZO-based integrated circuits (inverters and ring oscillators) were demonstrated

by Ofugi et al. [10] The gate length of these TFTs was 10 µm. Additionally, these TFTs

used a 100 nm SiOx gate insulator deposited by rf sputtering and were patterned using

standard photolithography techniques. Discrete TFTs fabricated alongside the integrated

circuits exhibited a channel mobility and threshold voltage of ∼3 cm2V−1s−1 and 7 V,

respectively. The maximum oscillation frequency of the ring oscillator circuit is ∼21.5

kHz (with 18 V supply voltage).

29

IGZO-based TFTs have also been utilized in an electronic paper demonstration.

[134] Ito et al. report on the fabrication IGZO-based TFT array on glass with an elec-

trophoretic display. The 4 in panel has a resolution of 200 pixels per inch and a pixel

count of 640 × 480. Discrete TFTs exhibited a µINC of 2.8 cm2V−1s−1 and VON of 2 V.

2.3 Conclusions

This chapter provides a summary of electrical and optical properties for several n-

type TCO semiconductors. The properties of ZTO, IGO, and IGZO are reviewed in more

detail, as these materials are of primary interest for this research. Finally, a summary

of oxide semiconductor-based TFTs is given, including discrete device performance and

examples of integration.

30

3. TFT FABRICATION AND CHARACTERIZATION

This chapter presents information regarding the fabrication and characterization of

TFTs and TTFTs. First, deposition techniques used in TFT and TTFT fabrication are

discussed. Second, electrical characterization of TFTs is discussed.

3.1 Thin-film deposition and processing

This section covers deposition and processing techniques that are used for this re-

search. Many other processing techniques are available, as explained in detail elsewhere.

[135]

3.1.1 Evaporation

Evaporation is a deposition technique whereby the material to be deposited begins

as a solid, goes into a vapor phase, and then recondenses back to a solid thin film. [135]

The transition from solid to vapor can either be direct, referred to as sublimation, or

indirect via a transition from a solid to a liquid phase, i.e., melting, and subsequently from

a liquid to a vapor phase, i.e., vaporization. Whether the material sublimes or melts and

vaporizes depends on the heating source, and the material to be deposited. Additionally

the temperature at which the source material sublimes or vaporizes depends strongly on

the composition of the source material. Note that the stoichiometry of the growing film

may be different from the source material, such as oxides which tend to be reduced during

evaporation.

31

Evaporation at the OSU solid state processing lab is accomplished using a small

desktop evaporator manufactured by Polaron. For the research described in this thesis,

the Polaron is used for deposition of aluminum. The main chamber for this system is

comprised of a glass bell jar assembly. High-vacuum of ∼5 x 10−7 Torr is achieved

with a diffusion pump. The heating element is a resistive element, a tungsten basket. The

aluminum material is placed in the tungsten basket. A current of∼30 A is passed through

the tungsten basket, at which point the aluminum melts and subsequently vaporizes.

In addition to thermal evaporation, an alternative method is electron beam evapo-

ration which utilizes a high energy (5-30 keV) electron beam to heat a source material.

One of the drawbacks of electron beam evaporation is possible damage to the deposited

thin-film from x-rays generated by the electron beam. Electron beam evaporation at the

OSU solid state processing lab is accomplished using a custom built system. The elec-

tron beam evaporation system utilizes a stainless steel chamber which includes a thermal

source for deposition of a second material concurrent with the electron beam evaporation.

3.1.2 Sputtering

Sputtering is a common thin film deposition technique whereby a plume of the

source material is created by energetic ions, generally argon ions. Sputtering is the pri-

mary deposition method utilized in this work, and is thus given more attention than other

methods discussed in this thesis.

In the most simple configuration, the DC diode sputtering system, an anode, which

is usually grounded, and a cathode are placed within a vacuum chamber. The chamber

32

is evacuated to high vacuum to remove any impurities. The chamber is backfilled with

an inert gas and a DC field on the order of 100 V/cm is applied between the electrodes.

Any free electrons within the chamber are accelerated by the field, reaching energies

high enough to ionize more gas atoms upon collision. The cascading process repeats,

leading to gas breakdown and the establishment of a glow discharge in the chamber. The

negative electrons are swept by the field to the positive anode while the positive ionized

gas species are attracted towards the negative cathode. As the ions strike the cathode,

secondary electrons are emitted from the surface; these secondary electrons allow the

discharge to be sustained.

Because the mass of the electrons is much smaller than that of the ions, they are

quickly accelerated away from the negative cathode, leaving a positively charged region

in front of the cathode. This high-field region is known as the Crooke’s dark space and

accounts for most of the voltage dropped between the anode and cathode. This region

accelerates positively charged ions toward the cathode leading to atoms and clusters of

atoms being ejected from the cathode.

In sputtering, the cathode is a pellet of the source material (the ”target”) while the

substrate is placed on the anode. The atoms ejected from the cathode recondense onto the

anode surface.

In practice, strong magnets are employed behind the cathode. The magnetic config-

uration is designed such that the magnetic field causes electrons to gyrate in loops parallel

to and confined near the cathode surface, greatly increasing the chance of ionization. This

allows operation at lower pressures than with non-magnetron configurations. The disad-

33

vantage of a magnetron configuration is preferential erosion in certain areas, leading to

material waste and non-uniform deposition.

Additionally, DC configurations are only possible when the target is made of a

conducting material, such as a metal, which can source secondary electrons continuously

to sustain the glow discharge. For non-conductors, an AC field is used, typically created

by an rf generator at 13.56 MHz. The applied AC excitation creates a self-biased DC

voltage localized in front of the cathode, leading to sputtering as in a DC configuration.

During the short positive portion of the excitation, electrons are attracted towards the

target to replenish lost secondary electrons.

Reactive sputtering can be employed by flowing a reactive gas in combination with

an inert gas during the sputter deposition process. For example, when sputtering an oxide

from a metal or ceramic target, oxygen is introduced into the chamber in a controlled

manner to adjust film properties.

At the OSU solid state processing lab, sputtering is performed using a custom

built sputtering system denoted the Tasker/Chiang (Tang) sputtering system. [136, 137]

The Tang is a cylindrical, stainless-steel, load-locked chamber. [136] High-vacuum is

achieved using a turbomolecular pump. The Tang has three side-mounted 2” sputtering

gun and two side-mounted 3” sputtering gun. Gas flow is controlled via four mass flow

controllers which can introduce up to four different gas compositions. Currently the sys-

tem is configured with argon (with a maximum flow of 100 standard cubic centimeters per

second (sccm)), nitrogen (with a maximum flow of 50 sccm,) oxygen (with a maximum

34

flow of 50 sccm,) and a gas mixture of 9 parts argon to 1 part oxygen (with a maximum

flow of 10 sccm.)

Thin films deposited across a 15 cm wafer using this system is shown to be good.

IGZO-based thin-film transistors were fabricated on a 15 cm wafer in conjunction with

Sharp Labs. Across the 15 cm wafer, 96 TFTs were tested, exhibiting a mean µAV G of 11.1

cm2V−1s−1, with a range and standard deviation of 1.6 and 0.4 cm2V−1s−1, respectively.

Measured VON values exhibited a mean of -2.2 V, a range of 2V, and a standard deviation

of 0.23 V.

For this thesis, semiconductor layers and ITO contacts are deposited via sputtering.

3.1.3 Plasma-enhanced chemical vapor deposition (PECVD)

Chemical vapor deposition (CVD) techniques employ gas-phase sources (rather

than solid sources as employed in PVD) to form a thin film. [138] After the gas-phase

precursors are introduced into the chamber, they are transported (by diffusion) to the

substrate, where a reaction that results in thin film formation occurs. This reaction can

be driven in a variety of ways, including (but not limited to) thermally, by photons, or

by glow discharge. Plasma-enhanced chemical vapor deposition (PECVD) utilizes both a

glow discharge and heat to drive the thin film-forming reaction. Use of a glow discharge

allows for reduced processing temperatures compared to conventional CVD.

In this work, PECVD is utilized to deposit SiO2 for use as a gate insulator. Two dif-

ferent gas sources are utilized: silane (SiH4) and TEOS(SiO4C8H20). Silane is a gaseous

species consisting of hydrogrenated silicon, analogous to methane. Typically silane is

35

converted to silicon dioxide in the presence of nitrous oxide (N2O) via

SiH4 + 4N2O−→ SiO2 + 4N2 + 2H2O. (3.1)

TEOS is an organometallic liquid consisting of a tetrahedral coordinated silicon with an

ethyl ester (-O-CH2-CH3) attached at each of the tetrahedral sites. TEOS is typically in-

troduced into a deposition chamber via a carrier gas (N2) that is introduced into a bubbler

containing TEOS. TEOS conversion to silicon dioxide consists of

SiO4C8H20 +12O2 −→ SiO2 + 8CO2 +10H2O. (3.2)

3.1.4 Atomic layer deposition (ALD)

Atomic layer deposition (ALD) is a powerful deposition technique that produces

films with excellent step coverage and few pin-hole defects. [139] The main difference

between previously discussed thin film deposition techniques (i.e. evaporation and sput-

tering) and ALD is the growth mechanism. In the previously discussed techniques, thin

film growth is dominated by nucleation, thus forming microcrystals, whereas ALD is a

self-controlled process, resulting in the sequential growth of monolayers or submonolay-

ers.

Execution of the ALD process involves anionic and cationic precursor gases which

are separately introduced into the deposition chamber. [140] The cationic species is first

introduced so that several monolayers are adsorbed onto the substrate surface. An inert

gas then purges the surface, causing desorption of weakly bound adatoms and, ideally,

36

retention of a single saturated monolayer of film growth. Next, an anionic species is

introduced and reacts with the adsorbed cationic precursor at the substrate surface. A

subsequent anion purge completes the sequence. This alternating cycle is repeated until

the appropriate film thickness is achieved. Note that saturated monolayer growth does not

always occur. Additionally, the alternating ALD cycle can be appropriately modified to

accomplish doping or alternate atomic engineering of the deposited layer.

3.1.5 Post-deposition thermal processing

After deposition, many films require a thermal anneal. Annealing is accomplished

by controlling the ambient pressure, ambient composition and the temperature of the

substrate. During thermal annealing, thin films can react with the processing ambient,

which can consist of, for example, oxidizing or reducing gases. Thin films can also

undergo crystallization, diffusion, and a change in film stress due to thermal annealing.

For the research discussed in this thesis, Thermolyne 62700 and 47900 box furnaces

are used for thermal annealing. The thermolyne box furnaces utilizes resistive coils as the

heating element, a thermocouple as the temperature sensor, and room air as the annealing

ambient. No vacuum pump or gases are connected to this system. Samples are placed on

alumina discs during annealing to prevent contamination.

In addition a Neytech Qex system is used for thermal annealing. The Neytech

system is a cylindrical chamber and utilizes resistive coils and a thermocouple as the

heating element and heat sensor, respectively.

37

3.2 Hall measurement

The Hall effect, discovered in 1879, can be used to determine the resistivity, carrier

type and concentration, and mobility of a sample. [141, 142] The Hall effect is based on

the Lorentz force,

−→F = q(−→v x

−→B ), (3.3)

where q denotes the charge of the particle, −→v the velocity vector, and−→B the magnetic

field vector. The Lorentz force deflects carriers (the direction of deflection is determined

by charge of the particle and the cross product of −→v and−→B ) towards the top or bottom

of the sample, creating a potential known as the Hall voltage, VH . The Hall voltage is

defined as,

VH =BIqtn

, (3.4)

where I is the current, t is the thickness of the sample and n is the carrier concentration.

In addition, one can define the Hall coefficient, RH ,

RH =tVH

BI. (3.5)

Note that the sign of the Hall coefficient indicates dominant carrier type; a negative Hall

coefficient indicates that electrons are the dominant carriers. [141, 142]

After determining the Hall coefficient, the carrier concentration, n, is given by,

n =− 1qRH

. (3.6)

38

To determine the Hall mobility, the film resistivity is first assessed using,

ρ =πt

ln(2)R12,34 +R23,41

2. (3.7)

The two resistances in Eq. 3.7 can be generalized as Rab,cd and are measured by forcing

a current from contact a to b, then measuring the voltage between terminals d and c.

Finally, the Hall mobility, µH , is obtained using,

µH =RH

ρ. (3.8)

Note that the Hall mobility is related to the conductivity mobility for electrons (or holes)

via

µH = rµn(p), (3.9)

where r, the scattering factor, and is defined as,

r =〈τ2〉〈τ〉2 . (3.10)

τ is the mean time between scattering events. r is typically between 1 and 2. Specifically,

r is 1.18 for lattice scattering and 1.93 for impurity scattering. [141]

For measurements conducted at OSU, a symmetric lamella-type van der Pauw

structure is used. [141] When using this structure, terminals to the sample should be

small and close to the sample edges. Sample and contact symmetry is not required, but

39

in practice is preferred. If these conditions are not met, appropriate corrections must be

made.

3.3 Thin-film transistor fabrication

Figure 3.1 shows two TFT structures fabricated for this thesis: a fully-transparent

TTFT and a non-transparent TFT built on a silicon substrate. Both TFTs are bottom-gate

staggererd TFTs, as shown in Fig. 3.3.

3.3.1 Fully-transparent TTFT

Figure 3.1a-b shows a cross section of a fully-transparent TFT. A fully-transparent

TTFT is prepared on Nippon Electric Company glass substrates (NEG OA2) coated with

a 100 nm sputtered indium tin oxide (ITO) gate electrode film and a 220 nm atomic layer

deposited superlattice of AlOx and TiOx (ATO). The ATO has a dielectric constant of

∼15. The ITO and ATO layers constitute the gate contact and insulator, respectively, of a

bottom-gate TTFT. An ∼40 nm semiconductor layer is then deposited via RF magnetron

sputtering through a shadow mask for semiconductor definition using 2” diameter sputter

targets, a target-to-substrate distance of∼7.5 cm, a power of 50 W, a pressure of 5 mTorr,

and an Ar:O2 ratio of 9:1. Next, an ∼200 nm layer of ITO is deposited by RF sputtering

through a shadow mask for source and drain patterning using a 3” target in pure Ar at

a pressure of 30 mTorr. Aluminum deposited via thermal evaporation is used as an al-

ternative source and drain contact material. There is no measureable difference between

aluminum source/drain TTFTs and ITO source/drain TTFTs. The TFT length and width

40

(a)ITO ITOITO ITO

Semiconductor

ATOATO

ITO

GlassGlass

(b)Al Al

Silicon dioxide

Semiconductor

Silicon

Gold

Figure 3.1: TFT structures used for the research discussed in this thesis, including (a)fully-transparent thin-film transistor and (b) non-transparent thin-film transistor.

41

are 1520 µm and 7170 µm, respectively. The entire thin film stack is then furnace an-

nealed in air using a one hour ramp and a 10 minute hold at the processing temperature

for 10 minutes; the sample is then allowed to cool inside the furnace for 5 hours to reach

room temperature. Annealing occurs prior to aluminum source/drain deposition when it

is utilized.

3.3.2 Non-transparent TFT

Figure 3.1a shows a cross section of a non-transparent TFT. A non-transparent TFT

is prepared on heavily-doped p-type silicon substrates with 100 nm of thermal silicon

dioxide and a gold back contact. Note that the heavily-doped silicon acts as both the

substrate and the gate electrode. An ∼40 nm semiconductor layer is then deposited via

RF magnetron sputtering through a shadow mask for semiconductor definition using a

2” diameter sputter target, a target-to-substrate distance of ∼7.5 cm, a power of 50 W, a

pressure of 5 mTorr, and an Ar:O2 ratio of 9:1. Next, an ∼200 nm layer of aluminum

is deposited via thermal evaporation to form the source and drain electrodes. Both the

semiconductor layer and source/drain electrodes (ITO) are patterned through the use of

shadow masks; the TFT length and width are 100 µm and 1000 µm, respectively. The thin

film stack is then furnace annealed similar to the fully-transparent TTFT.

3.4 Transistor overview

Figure 3.2 shows the basic structure of a TFT and several energy band diagrams

as viewed through the gate of an n-semiconductor, accumulation-mode TFT. [143] The

42

energy band diagram of Fig. 3.2b shows the device at equilibrium, with 0 V applied to

the source, drain, and gate. Figure 3.2c shows an energy band diagram with the gate neg-

atively biased. The applied negative bias repels mobile electrons from the semiconductor,

leaving a depletion region near the insulator-semiconductor interface. When compared to

Fig. 3.2b, this biasing condition has a reduced conductance due to the reduced number of

mobile electrons in the semiconductor. Figure 3.2d shows an energy band diagram with

the gate positively biased. The applied positive bias attracts mobile electrons, forming

an accumulation region near the insulator-semiconductor interface. These excess mobile

electrons lead to an increase in the conductance.

Beginning with the case where the gate is biased positively and accumulation is

established, i.e., Fig. 3.2d, consider the effect of an applied drain-source voltage, VDS.

Initially the semiconductor is modeled as a resistor, i.e. linearly increasing current with

VDS. As VDS increases, accumulation near the drain decreases. As VDS is increased

further, the region near the drain eventually begins to deplete. The voltage at which the

semiconductor region near the drain is fully depleted of carriers is denoted the pinch-

off voltage. Therefore, application of VDS greater than the pinch-off voltage results in a

saturated drain current characteristic.

TFT device structures can differ from that shown in Fig. 3.2a. Four possible TFT

device structures are shown in Fig. 3.3. [144] As evident from Fig. 3.3, devices can be

either staggered or coplanar. In a coplanar configuration, as shown in Figs. 3.3b and 3.3d,

the source and drain contacts and the insulator are on the same side of the semiconductor.

In such an arrangement, the source-drain contacts are in direct contact with the induced

43

DrainSource

Conductor

(a)

Conductor

Semiconductor

Dielect ric

Gate

VGS = 0 V VGS > 0 VVGS < 0 V

(d)

or In

su

lato

r

Meta

l

su

lato

r

al

(b)

Sem

ico

nd

ucto M

Insu

lato

r

Meta

l

nd

ucto

r

(c)

Ins

Meta

co

nd

ucto

r

S

Sem

ico

n

Sem

ic

Figure 3.2: (a)The basic structure of a TFT and corresponding energy band diagrams asviewed through the gate for several biasing conditions: (b) equilibrium, (c) VGS <0 V,and (d) VGS >0 V

44

GateSource Drain

Source Drain

Gate

Conductor

Semiconductor

Dielectric

(a)

(b)

(c)

(d)

Source Drain

GateSource Drain

Gate

Figure 3.3: Four general thin-film transistor configurations, including: (a) staggeredbottom-gate, (b) coplanar bottom-gate, (c) staggered top-gate, and (d) coplanar top-gate.

45

channel. In a staggered configuration, as shown in Figs. 3.3a and 3.3c, the source and

drain contacts are on the opposite side of the semiconductor from the insulator; thus, there

is no direct connection to the induced channel. However, the contact area is very large

when a staggered structure is used.

In addition to coplanar and staggered configurations, TFTs can be classified as ei-

ther bottom-gate or top-gate devices. A bottom-gate TFT, which is sometimes referred to

as an inverted TFT, has the gate insulator and gate electrode located beneath the semicon-

ductor, as shown in Figs. 3.3a and 3.3b. The top surface of a bottom-gate TFT is exposed

to air or is passivated by coating the top surface with a protective layer. A top-gate TFT,

as shown in Figs. 3.3c and 3.3d, has the gate and insulator located on top of the semicon-

ductor. In a top-gate device, the semiconductor is covered by a gate insulator so that the

top surface is inherently passivated.

Process integration-related issues can also motivate the use of different structures.

In the co-planar top-gate structure, the semiconductor is deposited first. Therefore, the

maximum semiconductor processing temperature is limited only by the semiconductor

and the substrate. Notice that in both bottom-gate structures, the insulator is deposited

first. If the insulator is deposited using a glow discharge process, such as rf sputtering

or plasma-enhanced chemical vapor deposition, the plasma-induced damage to the semi-

conductor layer can possibly be reduced using this structure (since insulator deposition

typically requires the use of a higher power as compared to deposition of other layers).

The co-planar structure is difficult to realize in some technologies, such as a-Si:H. a-

Si:H TFTs utilize ion implantation to form an ohmic contact to the semiconductor. Since

46

the maximum processing temperature of a-Si:H transistors is ∼ 350C, damage from

implantation cannot be remedied. This implies that the semiconductor must be protected

during implantation. If the insulator is used as an implant-block, there is no source/drain-

to-gate overlap. Without this overlap, the series resistance increases and retards carrier

injection. [145]

3.5 Thin-film transistor device characteristics

This section discusses several important TFT figures-of-merit, threshold voltage

and mobility, and their estimation from experimental data.

3.5.1 DC current-voltage measurements

DC current-voltage characteristics presented in this thesis are obtained using an

Agilent 4156B Semiconductor Parameter Analyzer. Measurements are executed in the

dark, with a hold time of 500 ms, a delay time of 200 ms, and medium integration time.

Devices are contacted using a Micromanipulator 6000 series probe station.

Figure 3.4 shows an abbreviated version of the output voltage as a function of time

for a typical transfer current-voltage measurement . For this measurement, VS and VD

are constant values of 0 V and 1 V, respectively. VG is varied from 0 V to 4 V. At t

= 0 s, the measurement begins by application of all initial voltages. VS is grounded,

VD = 1 V, and VG = 0 V. These voltages are applied for 500 ms, equating to the hold

time, and an additional 200 ms, equating to the first delay time, for a total of 700 ms.

At t = 700 ms the drain current, source current and gate current are measured. After

47

2

2.5

3

3.5

4

4.5V

olt

ag

e (

V)

VD

VS

VG

HoldTime

Tim

e

-0.5

0

0.5

1

1.5

2

Ap

plied

V

Time (s)

Dela

yT

Figure 3.4: Simplified timing diagram illustrating the applied voltage to the transistor asa function of time.

the measurements, the second set of voltages is applied (VS = 0 V, VD = 1 V, and VG

= 1 V), held for 200 ms (equating to the second delay time) and the measurements are

taken. The process of incrementing the voltage, waiting for the delay time, and taking the

measurement repeats until a maximum voltage of VG = 4 V is achieved. At the maximum

voltage point the voltage is applied for 200 ms, the measurement is taken, another delay

period occurs and another measurement is taken prior to the gate voltage decreasing down

to 3 V . The process of decrementing the voltage, waiting for the delay time, and taking

the measurements continues until VG reaches 0 V.

48

3.5.2 Threshold voltage and turn-on voltage

Threshold voltage, VT , is an important TFT parameter indicative of the onset of

drain current. [146] Unfortunately, it is not possible to uniquely define VT , which some-

times leads to ambiguous or even misleading conclusions. Thus, an alternative figure-of-

merit for the onset of drain current, the turn-on voltage, is introduced at the end of this

section and is extensively employed in this thesis.

VT may be estimated graphically by plotting the TFT output conductance, gD, as

a function of the gate-source voltage, VGS. [146] Using the square-law model of a TFT,

[147] ID is given by

ID = µCIWL

(VDS (VGS−VT )− V 2

DS2

), (3.11)

where W is the width of the semiconductor, L is the length from source to drain, µ is

the mobility in the semiconductor, CI is the gate insulator capacitance density, VDS is the

drain-source voltage, and VGS is the gate-source voltage. Evaluating gD as the derivative

of ID with respect to VDS leads to

gD =∂ID

∂VDS

VGS=constant

= µCIWL

(VGS−VT −VDS) . (3.12)

Notice that gD is directly proportional to VGS, and thus, is linear with respect to VGS.

Also note that gD approaches zero as VGS approaches VT + VDS. Thus, a gD-VGS plot

should be linear and an extrapolation of the linear portion of this curve to the VGS-axis is

equal to VT + VDS.

49

100

150

200

250

S)

-50

0

50

100

-10.0 0.0 10.0 20.0 30.0 40.0

gD

(

VGS (V)

VT + VDS

Figure 3.5: Output conductance-gate-to-source voltage (gD-VGS) characteristic illustrat-ing threshold voltage estimation via extrapolation of the linear portion of this curve tothe VGS-axis intercept for an indium gallium zinc oxide semiconductor layer TFT with awidth-to-length ratio of 10:1. gD is assessed at VDS = 1 V.

50

Figure 3.5 shows a gD-VGS curve for a TFT with an indium gallium zinc oxide

semiconductor layer. For VGS > 25 V, the curve is linear. Using linear extrapolation of

this curve to the VGS-axis intercept yields a value of 13 V. Since this plot is taken at VDS

= 1 V, VT is estimated to be 12 V for this device.

An alternative procedure for assessing the initiation of current flow in a TFT is

to employ a log(ID)-VGS curve and to define a turn-on voltage, VON , as the voltage at

which ID begins to increase with increasing VGS. [148] This definition of turn-on voltage

corresponds to the applied gate bias at which an appreciable density of mobile carriers

are present within the semiconductor.

Figure 3.6 shows a log(ID)-VGS plot for the same TFT as shown in Fig. 3.5. VON

for this device is 2 V. It is evident from Fig. 3.6 that VON is a more accurate indicator

of the onset of current than VT . Thus, for the research reported in this thesis, VON is

preferred to VT as a TFT parameter.

3.5.3 Mobility

Along with threshold voltage, mobility is the other key figure-of-merit for TFTs.

Mobility is a measure of the mobile carrier transport in the semiconductor and thus re-

lates information about the current drive of the TFT. A higher mobility corresponds to a

higher current drive. Four types of mobility are considered in this thesis: average mobil-

ity (µAV G), incremental mobility (µINC), saturation mobility (µSAT ), and saturation-average

mobility(µSAT−AV G. [148, 146]

51

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

D(A

)

VT

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E 06

-10.0 0.0 10.0 20.0 30.0 40.0

I D

VGS (V)

VON

Figure 3.6: Log(ID-VGS) transfer characteristics showing the turn-on voltage, VON , andthe threshold voltage, VT for the same device as shown in Fig. 3.5. The TFT is measuredat VDS = 1 V.

52

Average mobility (µAV G) is an estimate of the mobility of all carriers induced into

the semiconductor by an applied gate bias, VGS. [148] Average mobility is calculated

using

µAV G(VGS) =GLIN

D (VGS)WL CI(VGS−VON)

, (3.13)

where W and L are the width and length of the TFT, and CI is the gate insulator capaci-

tance, and GLIND is the output conductance as a function of applied gate bias calculated in

the linear regime, as indicated by the notation LIN , such that the TFT can be modeled as a

resistor. The output conductance is also evaluated at small values of VDS and is calculated

as [148]

GLIND (VGS) =

ID(VGS)VDS

VDS→0

. (3.14)

Incremental mobility is the mobility of charges incrementally added to the semi-

conductor by a corresponding incremental change in VGS. [148] Incremental mobility is

calculated as [148]

µINC(VGS) =GLIN′

D (VGS)WL CI

VDS→0

, (3.15)

where GLIN′D (VGS)is the change in output conductance due to a corresponding change to

VGS. This is evaluated as as

GLIN′D (VGS) =

∂GLIND

∂VGS

VDS→0

. (3.16)

Comparing these two mobility estimates, average mobility is of greater practical

significance, as it estimates the mobility of all carriers in the semiconductor and is more

53

useful for quantifying device performance. On the other hand, incremental mobility is of

greater physical significance, as it estimates the mobility of incrementally induced carri-

ers with changing gate voltage and is more useful for analyzing trapping and interfacial

scattering physics of carriers transiting along the semiconductor.

A third mobility, saturation mobility, is extracted from a ID-VGS curve, measured

with the device held in saturation. [146] Saturation mobility is calculated as

µSAT =2m2

WL CI

VDS>>VGS−VON

(3.17)

where m is the slope of a plot of√

ID,SAT against (VGS - VT .) This slope is evaluated as

m =∂√

ID,SAT

∂VGS(3.18)

This µSAT equation is based on the assumption that the TFT characteristics follow

the ideal square-law model. This is not the case, however, for many situations. The pro-

cedure that is used for deriving µSAT is not exact, but actually involves an approximation

in its derivation. This can be confirmed using the conductance integral equation to derive

IDSAT . Substituting in the conductance equation using the charge sheet model,

GLIND (VGS) =

WL

CI µ(VGS) (VGS−VON), (3.19)

54

into the saturation regime form of the conductance integral equation,

IDSAT (VGS) =∫ VGS

VON

GLIND (VGS)dVGS, (3.20)

leads to

IDSAT (VGS) =WL

CI

∫ VGS

VON

µ(VGS) (VGS−VON)dVGS. (3.21)

Evaluating the integral in equation 3.21 via integration-by-parts results in

IDSAT (VGS) = W2LCI µ(VGS) (VGS−VON)2

−WL CI

∫ VGS

VON

(VGS−VON)2 ∂µ(VGS)∂VGS

dVGS, (3.22)

This is a more precise specification of IDSAT . Deriving the mobility expression for µSAT

from the square-law equation requires assuming that the mobility in saturation is a con-

stant, independent of VGS, so that the integral term in equation 3.22 may be neglected.

A new type of mobility, denoted as the satuation-average mobility, µSAT−AV G, is

introduced. It’s derivation is as follows. Beginning with the conductance integral equation

[149],

ID =∫ VGS

VGD

GLIND (VGS)dVGS, (3.23)

where ID is the drain current, VGS is the gate-to-source voltage, VGD is the gate-to-drain

voltage, and GLIND (VGS) is the output conductance when the device is operated in the

linear regime (i.e., VD ≈ VS ≈ 0 V) as a function of applied gate voltage (VGS). GLIND is

55

evaluated as

GLIND (VGS) =

ID(VGS)VDS

VDS→0

. (3.24)

First note that when the device is in saturation, VGD is replaced by VON and the

conductance integral equation is written as

IDSAT (VGS) =∫ VGS

VON

GLIND (VGS)dVGS. (3.25)

Differentiating both sides with respect to VGS yields

∂IDSAT

∂VGS= GLIN

D (VGS). (3.26)

From the charge sheet model [148], GLIND is given as

GLIND (VGS) =

WL

CIµ(VGS−VON). (3.27)

Replacing GLIND in Eq. 3.26 with 3.27, noting that

gSATm (VGS) =

∂IDSAT

∂VGS, (3.28)

where gSATm is the transconductance of the TFT in saturation, and solving for µ yields

µSAT−AV G =gSAT

mWL CI(VGS−VON)

. (3.29)

56

8

10

12

14

16

18

20

m2V

-1s

-1)

0

2

4

6

8

0.0 10.0 20.0 30.0

(cm

VGS (V)

Figure 3.7: Extracted average mobility (middle-black,) saturation mobility (top-darkgray,) and saturation-average mobility (bottom-light gray) characteristics for a singleIGZO-based thin-film transistor.

57

Figure 3.7 shows three types of calculated mobility values for a single IGZO-based

TFT. The black curve (middle curve) is an average mobility calculated from data taken

with VDS = 1 V. The dark gray curve (top curve) is a saturation mobility calculated using

Eq. 3.7 from data taken with VDS = 30 V. The light gray curve (bottom curve) is the

saturation-average mobility calculated using Eq. 3.15 from the same data as the satura-

tion mobility. At VGS = 30 V, the saturation mobility (∼17 cm2V−1s−1) overestimates

the mobility by ∼20%, when compared to the average mobility (∼13 cm2V−1s−1). The

saturation-average mobility (∼12.7 cm2V−1s−1) is clearly a more accurate estimate of

mobility, underestimating the mobility by only 3% when compared to the average mobil-

ity.

3.5.4 Drain current swing and drain current on-to-off ratio

The subthreshold swing (S) and the drain current on-to-off ratio (ION−OFFD ) are

estimated using a semi-log plot of the transfer characteristics taken at high VDS (i.e. VDS

> VDSAT = VGS - VON ,) as shown in Fig. 3.8, S is the inverse of the maximum slope in

the transfer characteristic,

S =(

∂log10(ID)∂VGS

)−1

max. (3.30)

S is a useful quantification of how efficiently the device turns on and is typically less than

1 V/decade. For the device shown in Fig 3.8, S∼500 mV/decade.

Drain current on-to-off ratio (ION−OFFD ) is a parameter for switching application

and provides a useful measure of device performance. ION−OFFD is simply the on-current

58

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

D(A

)

OF

F

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E 06

-10.0 0.0 10.0 20.0 30.0 40.0

I D

VGS (V)

S

I DO

N-O

Figure 3.8: Log(ID-VGS) transfer characteristics showing the drain current swing, S, andthe drain current on-to-off ratio, ION−OFF

D for the same device as shown in Fig. 3.5. TheTFT is measured at VDS = 30 V.

divided by the off-current,

ION−OFFD =

IOND

IOFFD

(3.31)

For the device shown in Fig 3.8, ION−OFFD ∼108.

3.6 Conclusions

A summary of thin film processing techniques relevant to the fabrication of TFTs

for this thesis is presented. Thin film processing techniques explored include evapora-

tion, sputtering, chemical vapor deposition, atomic layer deposition, and post-deposition

59

annealing. Sputtering is discussed in some detail, as these techniques have been essential

to the development of TFTs presented in Chapter 4.

The Hall measurement is discussed as a method of evaluating mobility, carrier con-

centration, and conductivity of thin-films. Finally TFT characterization techniques are

discussed including several key metrics: turn-on voltage, subthreshold voltage swing and

TFT mobility.

60

4. REACTIVE SPUTTERING OF OXIDE SEMICONDUCTORS

Reactive sputtering using a metallic target has several advantages compared to de-

position methods in which a ceramic target is used. [135, 150] Reactive sputtering using

a metallic target usually results in a higher deposition rate. The physical properties of the

metal lead to a more durable target of higher purity and superior thermal conductivity.

Finally, a metallic target is easier to fabricate, requiring less care and cost than is involved

in the fabrication of a ceramic target.

4.1 Introduction

Zinc oxide-based and zinc tin oxide-based thin-film transistors are fabricated via

reactive rf magnetron sputtering using metallic targets. The oxygen flow rate is found

to be an important process parameter for low-temperature zinc oxide and zinc tin oxide

synthesis. Sputtering using a low oxygen flow rate yields highly conductive metallic

films, whereas a high oxygen flow rate results in transistors with poor mobility. Zinc

oxide-based thin-film transistors fabricated at an optimal oxygen flow rate near room

temperature, i.e. without intentional substrate heating, exhibit incremental mobilities of

∼5 cm2V−1s−1, turn-on voltages of ∼-10 V, and drain current on-to-off ratios of ∼106.

Post-deposition annealing of these films at 300 C and 600 C yields transistors with

incremental mobilities up to 7 and 10 cm2V−1s−1, respectively.

Figure 4.1 shows the cross section and plan view of a typical bottom-gate TFT.

TFTs are prepared on heavily doped p-type silicon substrates with 100 nm of thermal

61

silicon dioxide and a tantalum/gold back contact. An ∼50 nm zinc oxide layer is then

deposited via rf magnetron sputtering through a shadow mask for semiconductor defini-

tion using a 2” diameter zinc metal sputter target purchased from Cerac, Inc. A target-to-

substrate distance of∼7.5 cm, a power of 50 W, and a pressure of 30 mTorr is used during

the zinc oxide deposition. Gas flow for the sputtering ambient is controlled via two MKS

mass flow controllers. 25 sccm of argon and various oxygen flow rates are introduced into

the chamber, and then the chamber pressure is adjusted to 30 mTorr. After the semicon-

ductor deposition, an ∼100 nm layer of aluminum is deposited by thermal evaporation

to form source/drain electrodes which are patterned through the use of shadow masks.

The TFT device length and width are 200 µm and 2000 µm, respectively. Post-deposition

annealing is accomplished in a Thermolyne 47900 box furnace. Samples are annealed at

temperature for 1 hour.

4.2 Reactive Zinc Oxide

Zinc oxide is a wide band gap semiconductor employed in numerous applications.

[151, 152, 153, 154, 155, 150] The piezoelectric nature of zinc oxide lends itself to surface

acoustic wave device and optical waveguide applications. [151, 152] Zinc oxide’s large

band gap and photoelectric properties leads to its use in UV filters and detectors. [153]

Zinc oxide is also used as a transparent conductor because of its optical and electrical

properties. [154, 155, 150]

Recently, zinc oxide has been utilized as the semiconductor layer in thin-film tran-

sistors (TFTs). Hoffman et al. reported fully transparent TFTs utilizing ion-beam sput-

62

Si

Au/Ta

SiO2 (100 nm)

Al Al

AlZnO (50 nm)Al

Zn

O

200 mm

20

00m

m

Figure 4.1: Cross sectional and plan view of a typical bottom-gate TFT.

63

0 5 10 15 20 25 30 35 40

VDS (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

I D (

mA

)

Figure 4.2: Drain current-drain voltage (ID-VDS) characteristics of a zinc oxide TFTwhich is fabricated near room temperature, i.e., without intentional substrate heating.VGS is decreased from 40 V (top curve, showing maximum current) to 0 V in 10 V steps.

tering of zinc oxide. [156] Carcia et al. fabricated zinc oxide-based TFTs on both silicon

substrates and plastic substrates. [9, 157] Masuda et al. demonstrated TFTs using pulsed

laser deposited zinc oxide. [11] All previously reported zinc oxide-based TFTs utilized

ceramic targets. This section discusses the fabrication of zinc oxide-based TFTs via reac-

tive rf sputtering using a metallic zinc target in an argon/oxygen ambient.

Figure 4.2 shows the drain current-drain voltage (ID-VDS) characteristics of a zinc

oxide TFT processed near room temperature, i.e. without intentional substrate heating,

using an oxygen flow of 0.5 sccm. The gate-to-source voltage, VGS, is decreased from

64

-20 -10 0 10 20 30

VGS (V)

400

1

2

3

4

5m

inc (

cm

2V

-1s

-1)

6

Figure 4.3: Incremental mobility-gate voltage characteristics of a zinc oxide TFT whichis fabricated near room temperature, i.e., without intentional substrate heating.

40 V (top curve) to 0 V in 10 V increments. This TFT exhibits qualitatively ideal char-

acteristics, including hard drain current saturation. Notice also that the spacing between

each ID-VDS curve is large, which is indicative of an appreciable induced-channel carrier

mobility. Turn-on voltage and drain-current on-to-off ratio for this device are -10 V and

106, respectively.

Figure 4.3 shows the incremental mobility-VGS characteristics for the device shown

in Fig. 4.2. Notice that the incremental mobility is strongly dependent upon VGS, con-

sistent with trends reported by Hoffman et al. and Nishii et al. [148, 158] On the mo-

65

bility scale used, the mobility increases at VGS > 15 V, and continues to increase to 5.5

cm2V−1s−1 at VGS = 40 V. Thus, an overvoltage of approximately 50 V with respect to

the turn-on voltage, or ∼40 V with respect to the threshold voltage (estimated as ∼0 V

from Fig. 4.2), is required in order to obtain an incremental mobility of 5.5 cm2V−1s−1.

Furthermore, Fig. 4.3 provides no evidence of a saturation in the incremental mobility

with increasing VGS. Thus, a further increase in VGS would result in an even higher in-

cremental mobility. This strong dependence of incremental mobility on VGS and lack of

mobility saturation with respect to increasing VGS is ascribed to grain boundary trapping

and grain boundary energy barrier-inhibited electron transport. [148, 158, 159] Note that

reported mobility values in this paper are measured an overvoltage of∼50 V with respect

to turn-on voltage.

In-situ substrate heating and post-deposition annealing increases the incremental

mobility slightly. A substrate temperature of 300 C yields transistors with peak in-

cremental mobilities of 6.5 cm2V−1s−1. Post-deposition annealing at 300 C and 600

C yields transistors with incremental mobilities of 7 and 10 cm2V−1s−1, respectively.

Turn-on voltages for all of the thermally processed devices are ∼-4 V. Improvements in

incremental mobility due to thermal processing are ascribed to improved crystallinity,

measured via XRD.

The oxygen flow rate is the most important process parameter for determining the

mobility performance of a zinc oxide TFT. Mobilities of transistors fabricated at room

temperature, with substrate heating, and with post-deposition annealing all show signifi-

cant dependence on the oxygen flow rate.

66

For devices processed near room temperature, the window for optimal oxygen flow

is between 0.5 sccm and 1 sccm. Sputtering in an ambient with an oxygen flow 6 0.4

sccm, results in a highly conductive film. The highly conductive nature of the film is

attributed to the incorporation of metallic zinc into the film. A sputtering ambient with an

oxygen flow > 1 sccm yields a films with a low incremental mobility.

For a TFT processed at a substrate temperature of 300 C, the optimal oxygen flow

is∼1.25 sccm. Increasing the oxygen flow above 1.25 sccm results in a drastically smaller

mobility.

For TFTs processed with a post-deposition anneal at 600 C, the optimal oxy-

gen flow is again 1.25 sccm. These devices yield peak incremental mobilities of 10

cm2V−1s−1. Increasing the oxygen flow to 2.5 sccm yields reduced peak incremental

mobilities of 3 cm2V−1s−1.

The decrease in mobility with increasing oxygen partial pressure is attributed to

a reduced density of oxygen vacancies, which in turn leads to an increase in the bar-

rier height at grain boundaries and a diminished carrier mobility. [157, 159] For 600

C annealed TFTs, the diminished carrier mobility is concomitant with an increase in

the turn-on voltage, -10 V and -2 V for oxygen flow rates of 1.25 sccm and 2.5 sccm,

respectively, as is to be expected with a decrease in the oxygen vacancy concentration.

Carcia et al. report a similar trend of decreasing mobility with increasing oxygen

partial pressure. [157] However, the optimal oxygen percentage that is reported by Carcia

et al., ∼0.05%, is significantly lower than the optimal oxygen percentage we obtain for

reactive sputtering, ∼1.67%. This dramatic difference in optimal oxygen percentage is

67

due to two key differences in the zinc oxide deposition procedure: the use of a ceramic

target versus a metallic target, and the use of a low power density versus a relatively high

power density. The ceramic target used by Carcia et al. contains a stoichiometric ratio of

oxygen to zinc. Thus, a small amount of additional oxygen incorporated into the growing

film compensates for oxygen loss during sputtering. In reactive sputtering, all of the

oxygen in the growing film originates from the sputtering ambient, necessitating the use

of a larger oxygen percentage. In addition, Carcia et al. utilize a low power density, 0.3-

0.5 W/cm2, during sputtering to minimize damage to the growing film. This low power

density results in a low deposition rate so that a lower oxygen pressure is required to fully

oxidize this slowly growing film. This is in direct contrast to our reactive sputtering at

a higher power density, 2.5 W/cm2, which necessitates the use of a much higher oxygen

flow rate in order to supply enough oxygen to ensure that the zinc oxide films are fully

oxidized.

4.3 Reactive Zinc Tin Oxide

Zinc tin oxide is a wide band gap semiconductor employed primarily as a transpar-

ent conductor and as a semiconductor layer for thin-film transistors(TFTs.) [160, 161,

162, 163, 164, 165, 166] Previous work with zinc tin oxide as a semiconductor layer for

TFTs focused on sputtering from a ceramic target. This section discusses the fabrication

of zinc tin oxide-based TFTs via reactive sputtering using a metallic zinc/tin target in an

argon/oxygen ambient.

68

Similarly to the zinc oxide TFTs, zinc tin oxide TFTs are prepared on heavily doped

p-type silicon substrates with 100 nm of thermal silicon dioxide and a tantalum/gold back

contact. An ∼50 nm zinc tin oxide layer is then deposited via magnetron sputtering

through a shadow mask for semiconductor definition using a 2” diameter 2:1, zinc:tin

metal sputter target purchased from Kamis Inc. A target-to-substrate distance of∼7.5 cm,

a power of 50 W, and a pressure of 30 mTorr is used during the zinc tin oxide deposition.

Gas flow for the sputtering ambient is controlled via two MKS mass flow controllers. 25

sccm of argon and various oxygen flow rates are introduced into the chamber, and then

the chamber pressure is adjusted to 30 mTorr. The target preparation before deposition of

the semiconductor layer consists of two steps. The zinc/tin target is first sputtered in pure

argon for 20 minutes to remove the target surface oxide layer. Next the zinc/tin target is

sputtered in the processing ambient for 20 minutes to simulate equilibrium conditions at

the target surface. After the semiconductor deposition, an ∼100 nm layer of aluminum

is deposited by thermal evaporation to form source/drain electrodes which are patterned

through the use of shadow masks. The TFT device length and width are 200 µm and 2000

µm, respectively. Semiconductor layer annealing is accomplished in a Thermolyne 47900

box furnace. Samples are annealed at temperature for 1 hour.

Log(ID)−VGS characteristics (at VDS = 40 V) are shown in Fig. 4.4 for zinc tin oxide

TFTs which are subjected to a 300 C and 500 C semiconductor layer anneal. Note that

ID, VGS, and VDS are the drain current, gate-to-source voltage, and drain-to-source voltage,

respectively. The inverse subthreshold slope for both devices are ∼ 500 mV/decade.

69

300oC

-5 5 15 25 35

VGS (V)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

I D (

A)

500oC

Figure 4.4: Log(ID)−VGS characteristics obtained at VDS = 40 V for two zinc tin oxideTFTs fabricated via reactive rf sputtering which are subjected to a 300 C and 500 Cpost-deposition anneal.

70

Electrical parameters often used to characterize a TFT are turn-on voltage, drain

current on-to-off ratio, and semiconductor mobility. The turn-on voltage, Von, is the gate

voltage at the onset of semiconductor conduction, i.e., the gate voltage at the onset of the

initial sharp increase in current in a log(ID)−VGS characteristic. [148] Von is equal to -2 V

and 2 V for the devices shown in Fig. 4.4. The ID on-to-off ratio is ∼ 107. Note that the

transistor “off” current is established by gate leakage, which is typically 10−11 to 10−9 A

for the SiO2 gate dielectric and device dimensions employed here.

Carrier mobility is arguably the most important TFT electrical parameter, as it quan-

tifies the semiconductor layer performance, specifically with respect to current drive ca-

pability and maximum switching frequency. Two estimates for the carrier mobility are the

incremental (µinc) and average (µavg) mobility. [148] While both estimates are assessed

in the linear region of device operation (VDS → 0 V), each has a unique physical inter-

pretation. µinc represents the mobility of incrementally induced carriers with changing

gate voltage, assuming that carriers already present in the semiconductor have a constant

mobility. µavg represents the average mobility of all carriers in the semiconductor. For

the 300 C processed device, µinc and µavg are∼11 and∼6 cm2V−1s−1, respectively. For

the 500 C processed device, µinc and µavg are ∼32 and ∼25 cm2V−1s−1, respectively.

The general shape of the mobility characteristic with respect to gate voltage, although not

shown here, is very similar to previously reported zinc tin oxide TFTs. [160]

Figure 4.5 shows the peak µinc as a function of oxygen partial pressure in the sput-

tering ambient. The mobility increases to a peak at 0.8 mTorr, for both 300 C and

500 C semiconductor layer annealing. At higher oxygen partial pressures, mobility de-

71

300oC

500oC

0.0

10.0

15.0

20.0

25.0

30.0

35.0

mIN

C (

cm

2V

-1s

-1)

5.0

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

O2 (mTorr)

Figure 4.5: Incremental mobility as a function of oxygen partial pressure for zinc tinoxide TFTs which are subjected to a 300 C and 500 C post-deposition anneal.

creases. This is similar to reports for zinc oxide, tin oxide and tin-doped indium oxide.

[150, 167, 168, 169] Turn-on voltage did not show a specific trend and is between -4 V

and 2 V for all devices.

A similar trend in mobility with respect to oxygen partial pressure is seen when the

sputtering ambient is lowered to 5 mTorr total pressure. Mobility peaks at 0.8 mTorr of

oxygen partial pressure and begins to decrease at oxygen partial pressures higher than 0.9

mTorr. Peak µinc as high as 40 cm2V−1s−1 is achievable. However, the turn-on voltage is

highly negative (less than -20 V) for all devices. This is indicative of oxygen vacancies

in the zinc tin oxide which creates carriers and shifts the turn-on voltage negative.

72

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

I D (

A)

-5 5 15 25 35

VGS (V)

300oC

500oC

Figure 4.6: Log(ID)−VGS characteristics obtained at VDS = 40 V for two zinc tin oxideTFTs fabricated via reactive dc sputtering which are subjected to a 300 C and 500 Cpost-deposition anneal.

73

Figure 4.7 shows the DC bias of the target as a function of oxygen partial pressure

at a constant sputtering pressure of 30 mTorr and constant power of 50 W. Notice that

hysteresis is apparent between the forward sweep (increasing oxygen partial pressure)

and backward sweep (decreasing oxygen partial pressure). This is common in reactively

sputtered materials from a metal target. This hysteresis is indicative of target poisoning

by the reactive gaseous species. In the case of zinc tin, on the forward sweep, the target

surface is metallic up to ∼1 mTorr of oxygen partial pressure. On the reverse sweep

the target surface is poisoned, i.e. covered with a thin zinc tin oxide layer, down to

∼0.5 mTorr of oxygen partial pressure. The region of optimal zinc tin oxide deposition

is highlighted. This region is where the DC bias begins to decrease in magnitude with

increasing oxygen partial pressure. This is also the optimal region for titanium nitride

and titanium oxide deposition, where the deposition process retains the high deposition

rate of a metal and the resultant film is of the correct stoichiometry. [135, 170, 171]

At lower oxygen partial pressures, the zinc tin oxide film is anion deficient, resulting in

TFTs with large negative VONs. At higher oxygen partial pressures, the deposition rate

decreases by an order of magnitude and the resultant TFTs exhibit very poor mobility

values.

In addition to a rf power source, sputtering using a dc power source is also explored.

Figure 4.6 shows the log(ID)−VGS characteristics (at VDS = 40 V) for two zinc tin oxide

TFTs sputtered using a dc power source, with semiconductor layer anneals of 300 C

and 500 C. The device exhibits fairly similar characteristics to the rf sputtered device.

On-to-off ratio is > 107 for both devices, inverse subthreshold slope is ∼ 600 mV/decade

74

355

350

355

e (

-V) Region of optimal zinc tin

oxide deposition

345

olt

ag

e

340

ge

t v

o

330

335

ve

ta

rg

325

330

eg

ati

v

320

0 0.5 1 1.5 2 2.5 3 3.5

N

O2 Partial Pressure (mTorr)

Figure 4.7: DC bias on the target as a function of oxygen partial pressure at a constantsputtering pressure of 30 mTorr and constant power of 50 W. A forward sweep (increasingoxygen partial pressure), backward sweep (decreasing oxygen partial pressure), and theregion of optimal zinc tin oxide deposition are shown.

75

and turn-on voltage is ∼ 0 V. Peak incremental mobiliites for the 300 C and 500 C pro-

cessed devices are 8 cm2V−1s−1 and 31 cm2V−1s−1, respectively. For these devices, the

sputtering ambient and oxygen partial pressure are 30 mTorr and 0.9 mTorr, respectively.

Similar to the rf sputtered devices, dc sputtered TFTs exhibit an optimal oxygen

partial pressure, however in the dc case it is slightly higher, ∼ 0.9 mTorr. At higher and

lower oxygen partial pressures peak µinc decreases.

4.4 Conclusion

In this chapter, we demonstrate that zinc oxide-based TFTs with incremental mo-

bilities as high as 10 cm2V−1s−1 can be fabricated via reactive sputtering using a metallic

target. In addition, devices fabricated near room temperature have incremental mobilities

of 5 cm2V−1s−1. Also, we demonstrate that zinc tin oxide-based TFTs with incremental

mobilities as high as 32 cm2V−1s−1 can be fabricated via rf and dc reactive sputtering

using a metallic target. Electrical characteristics of zinc oxide and zinc tin oxide films

deposited via reactive sputtering are shown to be strongly dependent on the oxygen flow

rate during thin film growth. The realization of oxide-based TFTs via reactive sputtering

lends itself to commercial applications due to the higher obtainable deposition rates, and

the cheaper, more durable nature of metallic targets; for zinc tin oxide, the price of the

starting material is halved, while at comparable powers, the deposition rate is 4× as large.

76

5. THIN-FILM TRANSISTOR DIELECTRIC PERFORMANCE

5.1 Introduction

The purpose of this chapter is to examine several types of gate capacitance and

gate insulator trends in IGZO-based TFTs. Increasing the gate capacitance density is

a straightforward way to improve the performance of a thin-film transistor (TFT) since

this leads to higher current drive at a given overvoltage, a decrease in the subthreshold

swing, and a decrease in the magnitude of the turn-on voltage towards zero volts. This is

demonstrated using various thicknesses of silicon dioxide deposited via chemical vapor

deposition as the gate insulator in TFTs employing indium gallium zinc oxide (IGZO)

as the semiconductor layer. The interface state density is estimated from a plot of the

subthreshold swing versus the gate insulator thickness to be equal to 2 × 1012 cm−2

and 1 × 1012 cm−2 for TFTs in which the IGZO semiconductor layer is post-deposition

annealed at 300 C and 500 C, respectively.

Additionally it is shown that the choice of dielectric material greatly affects TFT

performance. A comparison of chemical vapor deposited silicon dioxide, atomic layer de-

posited aluminum-titanium oxide, and chemical vapor deposited silicon nitride suggests

that silicon dioxide is the best and silicon nitride is the worst choice of TFT gate insulator

from the perspective of transfer curve hysteresis and turn-on voltage.

77

5.2 Experimental

Figure 5.1 shows a cross sectional view of a bottom-gate TFT. A silicon coupon

is used as the substrate with 1.75 µm of PECVD silicon dioxide as an isolation layer.

On top of the isolation layer, a gate electrode is formed consisting of titanium (10 nm,)

aluminum:copper (100 nm,) titanium (10 nm,) and titanium nitride (40 nm.) The two

layers of titanium are used as adhesion layers, while the aluminum:copper alloy is used

as a high conductivity layer. The titanium nitride layer is used as a diffusion barrier

to decrease the susceptibility of the gate electrode stack to thermal processing. A gate

dielectric consisting of PECVD grown silicon dioxide from a silane (SiH4) source is

deposited on top of the gate electrode stack. The silicon dioxide gate dielectric for this

study is varied from 25 nm to 200 nm.

TFTs utilizing aluminum titanium oxide(ATO) are fabricated on NEG OA2 glass

coated with indium tin oxide for a bottom gate electrode and 220 nm of ATO. ATO is

a proprietary, engineered insulator deposited by atomic layer deposition which consists

of a thick cap of aluminum oxide, alternative thin layer of aluminum oxide and titanium

oxide, and another thick cap of aluminum oxide. In this way, the high dielectric constant

of the titanium oxide and the large bandgap (concomitant with low leakage current) of

the aluminum oxide are combined to form a very low leakage insulator with a moderate

dielectric constant (∼15). The gate capacitance density for the ATO is 60.3 nFcm−2.

TFTs utilizing thermally grown silicon dioxide and silicon nitride are fabricated on

moderately-doped (3 × 1016 cm−3) silicon, which constitutes both the substrate and gate

electrode. Thermally grown silicon dioxide is grown in a dry environment with a tantalum

78

Al AlIGZO

Al Al

SiO

Ti/Al(Cu)/TiN/Ti

SiO2

SiO2

Ti/Al(Cu)/TiN/Ti

Silicon

SiO2

Silicon

Figure 5.1: Simplified cross-sectional view of the device structure used for this chapter.SiO2 is deposited via PECVD from a silane source, the gate electrode stack and IGZOare deposited via magnetron sputtering, and aluminum pads are deposited via thermalevaporation.

79

and gold back contact. Silicon nitride films are grown via high density plasma chemical

vapor deposition. The gate capacitance density for silicon dioxide and silicon nitride are

34.5 nFcm−2 and 62.0 nFcm−2, respectively.

An ∼40 nm indium gallium zinc oxide (IGZO) layer is then deposited via rf mag-

netron sputtering through a shadow mask for semiconductor definition using a 3” diam-

eter ceramic sputter target purchased from Cerac, Inc. A target-to-substrate distance of

∼7.5 cm, a power of 100 W, and a pressure of 5 mTorr is used during the indium gallium

zinc oxide deposition. After semiconductor deposition, an ∼100 nm layer of aluminum

is deposited by thermal evaporation to form source/drain electrodes which are patterned

through the use of shadow masks. The TFT device length and width are 200 µm and 2000

µm, respectively. Post-deposition annealing is accomplished in a Thermolyne 47900 box

furnace. Samples are annealed at temperature for 1 hour.

5.3 Chemical Vapor Deposited (CVD) Silicon Dioxide

Log(ID)−VGS transfer curves for IGZO-based TFTs fabricated using 100 nm of

thermally grown silicon dioxide and 100 nm of chemical vapor deposited silicon dioxide

via a silane source are shown in Fig. 5.2. TFTs are annealed at 500 C. The inset shows

ID −VGS transfer curves for the same devices, however plotted on a linear scale. As

seen from the figure, TFT current-voltage characteristics are almost identical for the two

devices.

Figure 5.3 shows the extracted incremental mobility for the devices of Fig. 5.2.

Although the current-voltage characteristics for the TFTs exhibit very similar charac-

80

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

D(A

)

1.E-12

1.E-11

1.E-10

1.E-09

-10 10 30 50

I D

Figure 5.2: Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizing thermallygrown silicon dioxide and CVD grown silicon dioxide as the gate insulator. The IGZOsemiconductor layer is post-deposition annealed in air at 500 C. (inset) ID-VGS transfercharacteristics for the same devices, plotted on a linear scale. The TFTs are measured atVDS = 30 V.

81

10

15

20

25

cm2V-1s-1)

0

5

10

0 10 20 30 40 50 60

inc(c

VGS - VON (V)

Figure 5.3: Extracted incremental mobility characteristics for IGZO-based TFTs utilizingthermally grown silicon dioxide and PECVD grown silicon dioxide as the gate insulator.The IGZO semiconductor layer is post-deposition annealed in air at 500 C. at 500 , asshown in Fig. 5.2.

teristics, mobility extraction magnifies any differences in device performance. One key

point to note is that µINC for the CVD TFT exhibits a peak value near VGS = 40 V. This

peak and subsequent decline in incremental mobility is attributed to interface roughness

scattering. [146] In contrast µINC for the TFT with thermally grown silicon dioxide is

still increasing in value at VGS = 60 V, indicating that a smoother surface is achieved with

thermally grown silicon dioxide. Peak mobility for the two devices differ. However this

difference is within the limits of experimental error, and could possibly be attributed to

width-to-length variation during patterning of the source and drain electrodes.

82

Figure 5.4 shows the log(ID)-(VGS−VON) transfer characteristics for four IGZO-

based TFTs utilizing various thicknesses (25, 50, 100, and 200 nm) of CVD silicon diox-

ide from a silane source as the gate insulator. IGZO and aluminum pads are processed

concurrently to reduce run-to-run variation. The overvoltage (VGS-VON) is used in order

to remove any variation due to the VON dependence with respect to the gate insulator.

As seen from this figure, these devices perform in a relatively ideal manner, with the

thinnest gate insulator (25 nm) corresponding to the highest gate capacitance density ex-

hibiting the largest current drive and the TFT with the thickest silicon dioxide (200 nm),

corresponding to the lowest gate capacitance density, exhibiting the lowest current drive.

Additionally, the subthreshold swing decreases with reducing silicon dioxide thickness.

Figure 5.5 shows the extracted incremental mobility as a function of gate-to-source

voltage for IGZO-based TFTs utilizing various thicknesses of CVD silicon dioxide. There

appears to be a trend with respect to peak mobility and gate dielectric thickness. How-

ever, these differences are within the limits of experimental error. The peak mobility

occurs at 10, 20, 40, and 80 V for the 25, 50, 100, and 200 nm thick gate dielectric, re-

spectively. The voltage at which the peak mobility occurs varies linearly with the gate

dielectric thickness. This decrease in mobility with increasing VGS at larger values of

VGS is again attributed to the interface roughness of the CVD silicon dioxide film. The

interface roughness begins to degrade mobility at an applied gate-to-source electric field

of 4.0 MVcm−1 for all four TFTs.

Figure 5.6 shows the turn-on voltage characteristics for the same devices as shown

in Fig. 5.4. The turn-on voltage varies linearly with gate dielectric thickness, with a y-

83

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

25 nm

1.00E-11

1.00E-10

1.00E-09

1.00E-08

0 2 4 6 8 10

25 nm

50 nm

100 nm

200 nm

Figure 5.4: Log(ID-VGS −VON) transfer characteristics for IGZO-based TFTs utilizingvarious thicknesses of silicon dioxide as the gate insulator. All TFTs are measured at VDS= 10 V.

84

10

15

20

m2V-1s-1 25 nm

50 nm 100 nm 200 nm

0

5

10

-5 15 35 55 75

INCcm

VGS (V)

Figure 5.5: Extracted incremental mobility µINC as a function of gate-to-source voltagefor IGZO-based TFTs utilizing various thicknesses of CVD silicon dioxide as the gateinsulator.

85

intercept of 0 V. The y-intercept at the origin indicates that the work function difference

and oxide charge does not significantly affect the turn-on voltage characteristics. By

modeling the MOS gate structure as a simple capacitor, the free carrier concentration of

a uniformly-doped depletion-mode TFT can be estimated by assuming that the turn-on

voltage corresponds to the point where the semiconductor is fully depleted, i.e.

ND =VON ∗CI

q∗ ts, (5.1)

where ND is the doping concentration, q is the fundamental electron charge, and ts is the

thickness of the semiconductor (40 nm for these TFTs). From Fig. 5.6, ND is estimated

to be ∼1 × 1017 cm−3.

Figure 5.7 shows the subthreshold swing as a function of silicon dioxide gate di-

electric thickness for TFTs fabricated at 300 and 500 C. The 500 C processed TFTs

consistently exhibit lower subthreshold swing values. The subthreshold swing varies lin-

early with gate dielectric thickness, with both temperatures exhibiting a y-intercept of ∼

60 mV decade−1. Additionally, the trend line for 200 C processed TFTs (not shown)

intersects the y-axis near 60 mV/decade and results in DIT ≈ 2.1 × 1012 cm−2.

The subthreshold swing (S) can be directly related to the interface trap density (DIT )

via [143]

S =kTq

ln10(

1+qDIT

CI

), (5.2)

where k is Boltzmann’s constant (8.62 × 10−5 eVK−1), T is the temperature in degrees

Kelvin, q is the fundamental charge (1.60 × 10−19 C), and CI is the capacitance density

86

Figure 5.6: Extracted turn-on-voltage VON as a function of CVD silicon dioxide thick-ness.

87

in

g

300 °Cd

Sw

id

e) DIT = 2e12 cm-2eV-1

ho

ldd

ec

ad

500 °C

hre

sm

V/d 500 °C

DIT = 1e12 cm-2eV-1

Su

bth (m S

SiO2 Thickness (nm)

Figure 5.7: Subthreshold swing as a function of CVD silicon dioxide thicknesss forIGZO-based TFTs annealed at 300 C and 500 C The interface state density for eachannealing temperature is also indicated..

88

of the gate insulator. Substituting

CI =εI

tI, (5.3)

where εI is the dielectric constant of the insulator and tI is the thickness of the insulator,

into Eq. 5.2 yields

S =kTq

ln10(

1+qDIT tI

εI

), (5.4)

Note that the subthreshold swing is directly proportional to the insulator thickness. Thus

a plot of S versus tI , such as given in Fig. 5.7, possesses a slope of kTq ln10qDIT

εIand a

y-intercept of kTq ln10. Thus, DIT may be found directly from the slope of a S versus tI

plot. The interface of IGZO and PECVD silicon dioxide exhibits an interface trap density

of DIT = 2 × 1012 cm−2eV−1 after a 300 C post-deposition anneal. At a higher anneal

temperature of 500 C, the interface trap density is reduced to 1 × 1012 cm−2eV−1.

Additionally, the trend line for a 200 C anneal (not shown) intersects the y-axis near 60

mV/decade and results in DIT ≈ 2.1 × 1012 cm−2. In contrast, polycrystalline silicon on

silicon dioxide processed at a temperature of 600 C exhibits a trap density of 1 × 1011

cm−2eV−1 [172], single crystal silicon with thermally-grown silicon dioxide exhibits a

trap density of 3 × 1010 cm−2eV−1 [173], and an organic TFT device utilizing optimized

single crystal rubrene on silicon dioxide, 2 × 1012 cm−2eV−1 [174].

5.4 Silicon Dioxide, Aluminum Oxide, and Silicon Nitride

Figure 5.8 shows the log(ID)-VGS transfer characteristics for two separate IGZO-

based TFTs utilizing thermally grown silicon dioxide as the gate dielectric and annealed

89

300 °C

500 °C

VGS (V)

Figure 5.8: Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizing thermallygrown silicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V.

90

300 °C

500 °C

VGS (V)

Figure 5.9: Log(ID)-VGS transfer characteristics for IGZO-based TFTs utilizing CVDsilicon dioxide as the gate insulator. The TFT is measured at VDS = 1 V.

at 300 and 500 C. As the temperature increases, the turn-on voltage for the device is

shifted more negative, due to reduction in trap density. Additionally, a small amount of

clockwise hysteresis is present in the TFT that is processed at 300 C, which is not seen in

the TFT that is processed at 500 C. This decrease in hysteresis is attributed to a reduction

in the density of interfacial defects by the high temperature anneal. Extracted incremental

mobilities are ∼ 20 cm2V−1s−1 for both the 300 C and 500 C processed TFTs.


based TFTs utilizing CVD silicon dioxide as the gate dielectric and annealed at 300 and

91

300 °C

500 °C

VGS (V)

Figure 5.10: Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizing ALDdeposited aluminum oxide:titanium oxide as the gate insulator. The TFT is measured atVDS = 1 V.

500 C. The characteristics are nearly identical to those of the thermally grown silicon

dioxide. As the temperature increases, the turn-on voltage for the device is shifted more

negative, due to a reduction in trap density. Additionally, a small amount of clockwise

hysteresis is present in the TFT that is processed at 300 C, which is not seen in the TFT

that is processed at 500 C. This decrease in hysteresis is attributed to a reduction in

the density of interfacial defects by the high temperature anneal. Extracted incremental

mobilities are ∼ 19 cm2V−1s−1 for both the 300 C and 500 C processed TFTs.

92


based TFTs utilizing ALD grown aluminum oxide:titanium oxide (ATO) as the gate di-

electric and annealed at 300 and 500 C. Similar to the silicon dioxide devices, as the

temperature increases, the turn-on voltage for the TFTs is shifted more negative, due

to reduction in trap density. ATO TFTs exhibit a more positive VON at 300 C, when

compared to their silicon dioxide counterparts, indicative of a higher empty trap con-

centration. At a processing temperature of 500 C, the ALD ATO and thermally grown

silicon dioxide exhibit similar VON’s. A dramatic clockwise hysteresis is present in the

TFT that is processed at 300 C, which is not seen in the TFT that is processed at 500

C. This is attributed, once again, to a reduction in the density of interfacial defects by

the high temperature anneal. Extracted incremental mobilities are 8 cm2V−1s−1 and 10

cm2V−1s−1 for the 300 C and 500 C processed TFTs, respectively.

A high temperature post-deposition anneal can improve TFT characteristics via

three methods: improvement of the semiconductor layer, improvement of the dielectric

layer or improvement of the semiconductor-dielectric interface. If the improvements to

TFT characteristics are due to improvements to the semiconductor layer, TFT characteris-

tics would be the same regardless of the dielectric used. Due to the fact that TFTs utilizing

silicon dioxide as the dielectric and annealed at 300 do not show the same characteris-

tics as those utilizing ATO, the improvement to the semiconductor layer is unlikely. To

analyze the possibility of improvement of the dielectric layer, a high temperature anneal

is performed to the gate dielectric prior to the semiconductor deposition. Figure 5.11

shows the log(ID)-VGS transfer characteristic for a TFT where the ATO dielectric is an-

93

VGS (V)

Figure 5.11: Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizing ALDdeposited aluminum oxide:titanium oxide as the gate insulator. For this TFT, the alu-minum oxide:titanium oxide is annealed to 500 C prior to the semiconductor deposition,and the TFT stack is annealed at 300 C after the semiconductor deposition. The TFT ismeasured at VDS = 1 V.

94

nealed at 500 C prior to the IGZO deposition. After the IGZO deposition, the TFT stack

is annealed at 300 C. The characteristics for this device are nearly identical to that of

the 300 C annealed device shown in Fig. 5.10. The similarity in log(ID)-VGS transfer

characteristics indicates that improvements to the dielectric is unlikely the cause of the

poor TFT characteristics when annealed at 300 C. Thus, the improvement in TFT char-

acteristics after a 500 anneal for TFTs utilizing ATO as the gate dielectric is attributed

to improvements to the semiconductor-dielectric interface.

Hysteresis in TFTs utilizing aluminum oxide as the gate dielectric is seen in other

studies as well. Electron beam evaporated aluminum oxide with zinc oxide processed at

temperatures up to 200 C as a semiconductor layer also exhibited significant hysteresis,

although zinc oxide on ALD aluminum oxide exhibited minimal hysteresis. [98] Car-

cia et al attribute hysteresis, or the lack thereof, to the quality of the interface between

the zinc oxide and aluminum oxide. Additionally, for the same processing parameters

TFT mobility varied drastically, depending on which gate dielectric is utilized, varying

from 0.3 cm2V−1s−1 on thermally grown silicon dioxide to 17.6 cm2V−1s−1 on ALD

aluminum oxide. The higher mobility seen in aluminum-oxide-based TFTs is contrary

to the trends presented in this chapter. The contrasting data is a result of two different

approaches. Carcia et al optimized their zinc oxide process for deposition on aluminum

oxide. Subsequently, they used the same processing conditions to fabricate zinc oxide de-

vices on silicon dioxide. For the data shown in this chapter, IGZO deposition parameters

are optimized for processing on silicon dioxide, and subsequently the same processing pa-

rameters are utilized for aluminum oxide and silicon nitride devices. This indicates that

95

300 °C 500 °C

VGS (V)

Figure 5.12: Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizing CVDdeposited silicon nitride as the gate insulator. The TFT is measured at VDS = 1 V.

with improved process optimization, stable IGZO-based TFTs with an ALD aluminum

oxide gate dielectric are feasible at lower processing temperatures.


based TFTs utilizing CVD silicon nitride as the gate dielectric and annealed at 300 and

500 C. Extracted incremental mobilities are 8 cm2V−1s−1 and 11 cm2V−1s−1 for the

300 C and 500 C processed TFTs, respectively. The turn-on voltage and clockwise

hysteresis present in the IGZO TFT annealed at 300 C given in Fig. 5.12 is similar to

that shown in Fig. 5.10 when atomic layer deposited aluminum-titanium oxide is used

96

as the gate insulator. However, when silicon nitride is used as the gate insulator, the

500 C anneal shifts the turn-on voltage in a positive direction and increases the amount

of hysteresis present in the transfer curve. This 500 C compared to 300 C annealing

trend is opposite of that found for thermal silicon dioxide, as shown in Fig. 5.8, and for

atomic layer deposited aluminum-titanium oxide, as indicated in Fig. 5.10. These turn-

on voltage and transfer curve hysteresis trends suggest that silicon nitride is a poor gate

insulator choice for IGZO TFTs. Note that oxygen is a common anion for silicon dioxide

and aluminum-titanium oxide gate insulators in conjunction with IGZO, while silicon

nitride and IGZO have different anions. A possible instability mechanism involves the

presence of hydrogen in the silicon nitride film, resulting in a high trap density at the

silicon nitride IGZO interface. Another possible mechanism is the anion exchange of

nitrogen and oxygen, which may account for the anomalous turn-on voltage and transfer

curve hysteresis trends found in silicon nitride-IGZO TFTs. Regardless of the actual

atomic instability mechanism, these turn-on voltage and transfer curve hysteresis trends

suggest that silicon nitride is a poor gate insulator choice for IGZO TFTs.

Souza et al reports that zinc oxide deposited via PLD for zinc oxide-based TFTs on

silicon nitride exhibits significant hystersis. [175] However, Carcia et al and Cross et al

report minimal hysteresis with respect to zinc oxide-based TFTs utilizing silicon nitride

as the gate dielectric with minimal hysteresis. [176, 20] In these two cases, all processing

is carried out at or below 150 C. This indicates that high processing temperatures (>

300 C) create defects at the silicon nitride-IGZO interface, resulting in a positive turn-on

voltage and significant hysteresis.

97

TEOS

precursor

Thermally grown

VGS (V)

SiH4 precursor

Figure 5.13: Log(ID)-VGS) transfer characteristics for IGZO-based TFTs utilizing thermalsilicon dioxide, CVD deposited silicon dioxide from a silane (SiH4) precursor and CVDvia a TEOS (SiC8H20O4) precursor. The TFTs are measured at VDS = 1 V.

98

5.5 Silane and Tetraethyl Orthosilicate (TEOS)-based CVD

With respect to silicon dioxide as a gate dielectric, three sources are compared,

thermally grown silicon dioxide via dry oxidation, CVD silicon dioxide from a TEOS

source, and CVD silicon dioxide from a silane source. The IGZO layer is processed at

300 C for these TFTs. All three samples are grown utilizing silicon as the substrate

and the IGZO semiconductor layers are processed concurrently. The turn-on voltage for

the devices did not vary significantly, 2 V, 1.5 V, and 2.8 V for the thermal, TEOS, and

silane silicon dioxide, respectively. The subthreshold swing did exhibit variation, S = of

337, 466, 570 mV/decade for the thermal, TEOS, and silane-based silicon dioxide. The

subthreshold slope variation is attributed to hydrogen and hydroxide in the dielectric film,

resulting in an increased interface trap density. No hydrogen or hydroxide groups are

present during the formation of the dry thermally grown silicon dioxide, which represents

the lowest subthreshold slope and thus the lowest interface trap density. In the case of

TEOS- and silane-based silicon dioxide, both depositions involve the use of hydroxide

groups. However the formation of a dense, lower defect density silicon dioxide from

TEOS is due to its lower activation energy. [177]

TEOS-based silicon dioxide performs better for polysilicon-based TFTs as well.

[178] In the case of TEOS- and silane-based silicon dioxide on polycrystalline silicon,

the interface trap density is found to be 1 × 1011 cm−2eV−1 and 1.5 × 1011 cm−2eV−1,

respectively.

99

5.6 Conclusion

In this chapter it is demonstrated that chemical vapor deposited silicon dioxide at

low applied fields behaves in a nearly identical fashion to thermally grown silicon dioxide

when utilized as a dielectric layer in thin-film transistors annealed at 500 C. At high

applied fields, the interfacial roughness of the chemical vapor deposited silicon dioxide

detrimentally affects TFT performance.

Additionally, increasing the gate capacitance density is demonstrated to improve

the performance of an IGZO TFT, yielding a higher current drive, a decrease in the sub-

threshold swing and a decrease in the magnitude of the turn-on voltage. The interface

state density for IGZO on CVD silicon dioxide is estimated to be 2.1 × 1012 cm−2eV−1,

2 × 1012 cm−2eV−1, and 1 × 1012 cm−2eV−1 for TFTs annealed at 200 C, 300 C, and

500 C, respectively, in conjunction with chemical vapor deposited silicon dioxide as the

gate insulator.

Finally, silicon nitride appears to be a poor gate insulator choice for IGZO TFTs,

based on turn-on voltage and transfer curve hysteresis trends, with silicon dioxide via a

TEOS source exhibiting the best TFT characteristics of the CVD precursors investigated.

100

6. OXIDE SEMICONDUCTOR THIN-FILM TRANSISTORTWO-TERMINAL ASSESSMENT

6.1 Introduction

Several recent studies have reported on the trap properties of oxide semiconductors

using optical [179, 180] or capacitance measurements [181]. Although these methods are

useful for trap assessment, both optical and capacitance methods require fabrication of

specialized device structures. Additionally, optical characterization provides an estimate

of a convolution of states above the valence band maximum and below the conduction

band minimum, rather than a direct picture of trap states near the conduction band mini-

mum, which is of primary interest with regard to thin-film transistor (TFT) operation.

By analyzing the two-terminal current-voltage characteristics of indium gallium

zinc oxide (IGZO) TFTs, information related to trap states within the IGZO semicon-

ductor can be obtained. This method provides a very simple path to trap assessment.

Extracted trap properties, particularly the trap energy, ET , correlate quite well with IGZO

TFT performance.

6.2 Experimental

Figure 6.1 shows a cross section of the device structure used in this chapter. TFTs

are fabricated on moderately-doped (3 × 1016 cm−3) silicon, which constitutes both the

substrate and gate electrode. Thermal silicon dioxide is grown in a dry environment with

101

a tantalum and gold back contact. The gate capacitance density for this 100 nm thick

silicon dioxide is 34.5 nFcm−2.

An ∼70 nm IGZO layer is then deposited via rf magnetron sputtering through a

shadow mask for semiconductor definition using a 3” diameter ceramic sputter target

purchased from Cerac, Inc. A target-to-substrate distance of ∼7.5 cm, a power of 100 W,

and a pressure of 5 mTorr is used during the IGZO deposition. Oxygen partial pressure

during the IGZO deposition is 7.4 µTorr, with the remainder of the sputtering ambient

composed of argon. Post-deposition annealing is accomplished in a Thermolyne 47900

box furnace. Samples are annealed at temperature for 1 hour. After semiconductor depo-

sition and annealing, an ∼200 nm layer of aluminum is deposited by thermal evaporation

to form source/drain electrodes which are patterned through the use of shadow masks.

The TFT device length and width are 200 µm and 2000 µm, respectively. The aluminum-

IGZO overlap is 200 µm × 2000 µm.

6.3 Transistor characteristics

Figure 6.2 shows the current-voltage characteristics for an IGZO TFT with a post-

deposition anneal of 300 C. The main figure represents the log(ID)-VGS transfer charac-

teristics for the device with VDS = 30 V. The turn-on voltage for this device is 3 V and the

drain current on-to-off ratio is > 106. The inset shows the ID-VDS output characteristics

for the device operated at VGS = 0, 10, 20, and 30 V. This TFT exhibits qualitatively ideal

characteristics, including hard drain current saturation.

102

200

IGZO (70 nm)

Al (200 nm) Al (200 nm)

Silicon dioxide (100 nm)

IGZO (70 nm)

Silicon dioxide (100 nm)

Silicon (p+)

Figure 6.1: Cross sectional view of the test structure used for this chapter. The siliconand silicon dioxide constitute the gate electrode and gate dielectric, respectively. Thealuminum pads are the source/drain contacts and indium gallium zinc oxide (IGZO) con-stitutes the semiconductor layer.

103

1.E-03

1.E-05

1.E-04

A)

ID0 35

0.4

0.45

1 E-07

1.E-06

en

t (A

0.2

0.25

0.3

0.35

D(m

A)

1.E-08

1.E-07

Cu

rre

0

0.05

0.1

0.15I D

1.E-10

1.E-09

C

I

0 10 20 30

VDS (V)

1.E-11

0.0 10.0 20.0 30.0 40.0

IG

VGS (V)

Figure 6.2: Log(ID)-VGS transfer characteristics obtained at VDS = 30 V for an IGZO TFTpost-deposition annealed at 300 C. (inset) Drain current-drain voltage (ID-VDS) outputcharacteristics for the same device. VGS is decreased from 30 V (top curve, showingmaximum current) to 0 V in 10 V steps. Note that the VGS = 10 V and 0 V curves overlapwith the x-axis.

104

6 E 08

5 E-08

6.E-08

4.E-08

5.E 08

Floating Gate

3.E-08

D(A

) Floating Gate(M-S-M operation)

2.E-08

I D

1.E-08VGS = 0 V

0.E+00

0 10 20 30

VDS (V)

Figure 6.3: Current-voltage characteristics for an IGZO TFT operated as a two-terminalM-S-M (Al-IGZO-Al) device. Voltage is applied to the drain with the source groundedfor two situations: with the gate electrode floating and with VGS = 0 V. The IGZO TFTemployed is subjected to a 300 C post-deposition anneal.

6.4 Metal-Semiconductor-Metal Current-Voltage Characteristics

Figure 6.3 shows ID-VDS characteristics for an IGZO-based TFT post-deposition

annealed at 300 C. Two curves are shown, VGS = 0 V and with a floating gate electrode.

Note that ID is negligible when VGS = 0 V, consistent with the positive turn-on voltage of

Fig 6.2. In contrast, with the gate electrode floating, ID exhibits a superlinear relationship

with applied voltage.

Figure 6.4 shows two-terminal metal-semiconductor-metal (M-S-M) current-voltage

characteristics obtained with a floating gate and plotted on a log-log scale for IGZO TFTs

post-deposition annealed at 300, 400, 500, and 600 C. For these devices, two regions

105

of conduction are visible. In the low voltage regions, the slope of the log-log plot is ∼1

decade/decade, indicative of ohmic conduction. In this region the free carrier concentra-

tion (n0) can be obtained from Ohm’s law by using [182]

I = Wtsqn0µVL

, (6.1)

where W and ts are the width and thickness of the semiconductor region, q is the fun-

damental charge of an electon, V is the applied voltage, and L is the distance from the

source contact to the drain contact. Extracted n0 values are shown in Table 6.1. At higher

applied voltages, the slope of the log-log plot increases to a value > 2, indicating that the

dominant conduction mechanism in this region is space-charge-limited current.

For an amorphous semiconductor, such as IGZO, an exponential band tail density

of states is expected,

Nt(E) =Nt

kBTte

E−ECkBTt = N0e

E−ECkBTt , (6.2)

where Nt(E) is the concentration of traps per unit energy (cm−3eV−1) centered at an en-

ergy E, Nt is the total trap density (cm−3), N0 is the concentration of traps per unit energy

(cm−3eV−1) evaluated at the conduction band minimum energy, EC, Tt is a temperature

parameter characterizing the trap distribution, and kB is Boltzmann’s constant. These

band tail states function as trap states. [3, 180, 181] Bulk space-charge-limited current

106

1 E-04

1.E-03

Increasing anneal

1.E-06

1.E-05

1.E 04

A)

Increasing annealtemperature

1.E-08

1.E-07

en

t (A

1 E 11

1.E-10

1.E-09

Cu

rre

1.E-13

1.E-12

1.E-11

1.E-14

3

1.E-02 1.E-01 1.E+00 1.E+01

Applied Voltage (V)

Figure 6.4: Current-voltage characteristics of four IGZO TFTs operated as two-terminalM-S-M (Al-IGZO-Al). Voltage is applied to the drain with the source grounded andthe gate electrode floating. Four different post-deposition anneal temperatures (300(dia-mond), 400(square), 500(triangle), 600(X) C) are shown.

107

through a material with an exponential trap distribution is characterized by [182]

I = WtsNCµq1−m(

εmNt(m+1)

)m (2m+1m+1

)m+1 V m+1

L2m+1 , (6.3)

where W and ts are the width and thickness of the semiconductor, q is the fundamental

charge of an electon, NC is the effective density of states in the conduction band, µ is the

bulk carrier mobility, ε is the dielectric permittivity of the semiconductor, V is the applied

voltage, and L is the device length. The variable m is defined as

m =Tt

T, (6.4)

where T is the measurement temperature and Tt is a temperature parameter characteriz-

ing the trap distribution which can be related to the characteristic trap energy (ET ) via

Boltzmann’s constant (kB), i.e.

ET = kBTt . (6.5)

To accomplish trap parameter extraction, is it convenient to take the logarithm of

both sides of Eq. 6.3, yielding

log(I) = log

(WtsNCµq1−m

(εm

Nt(m+1)

)m (2m+1m+1

)m+1 1L2m+1

)+(m+1)log(V ).

(6.6)

Note that this equation has the form of a linear equation. Estimation of m is accomplished

by recognizing that the slope of the line is (m+1). The first term on the right side of Eq.

108

6.6 corresponds to the y-intercept of the linear equation. With m known from assessment

of the slope, all of the other y-intercept parameters, i.e. W, Ts, L, NC, µ, and m, are

known except for Nt and possibly µ. Thus Nt can be estimated from an evaluation of

the y-intercept. The accuracy to which Nt may be assessed depends on the accuracy

to which µ is known and also on the y-intercept uncertainty. Most of the Nt variability

associated with estimation of the y-intercept since it is located relatively remotely from

the data points from which it is predicted. In contrast, the accuracy of Nt does not depend

critically on the assumed value of µ. For example, the first entry for Nt of Table 6.1

changes from 9 × 1014 cm−3 to 9.8 × 1014 cm−3 when the mobility is assumed to be 40

cm2V−1s−1 rather than the value of 20 cm2V−1s−1 used in the actual assessment.

Additionally, from the extrapolated value of m and using Eq. 6.4, a value for Tt can

be calculated, and subsequently from Eq. 6.5 a value for ET .

109

Tabl

e6.

1:A

sum

mar

yof

IGZ

OT

FTpr

oper

ties

for

vari

ous

post

-dep

ositi

onan

neal

tem

pera

ture

s.In

crem

enta

lmob

ility

µ IN

Can

dtu

rn-o

nvo

ltage

(VO

N)a

reob

tain

edfr

omth

ree-

term

inal

TFT

asse

ssm

entw

hile

spac

e-ch

arge

-lim

ited

para

met

ers,

i.e.,

char

acte

rist

ictr

apen

ergy

and

tem

pera

ture

,ET

and

T t,t

otal

trap

dens

ity,N

t,tr

apco

ncen

trat

ion

peru

nite

nerg

yev

alua

ted

atth

eco

nduc

tion

band

min

imum

,N0,

are

obta

ined

from

two-

term

inal

mea

sure

men

tsbe

twee

nth

eso

urce

and

drai

nw

ithth

ega

teflo

atin

g.T

hefo

llow

ing

valu

esar

eus

edin

the

estim

atio

nof

Nt

and

N0:

NC

=5.

0×

1018

cm−3

,µ=

20cm

2 V−1

s−1 ,a

ndε S

=1.

0×

10−1

0Fc

m−1

.

Ann

eal( C

)µ I

NC

(cm

2 V−1

s−1 )

VO

N(V

)E

T(m

eV)

T t(K

)N

t(cm

−3)

N0(

cm−3

eV−1

)n 0

(cm−3

)30

013

.64

130

1530

9×

1014

6×

1015

unm

easu

rabl

e40

014

.92

8091

32×

1015

3×

1016

unm

easu

rabl

e50

018

.60

6068

78×

1014

1×

1016

6×

1012

600

18.9

050

554

1×

1015

3×

1016

2×

1013

110

1 E+17

1 E 16

1.E+17

1.E+16

V-1

)1.E+15

cm

-3eV

1.E+14

Nt( c

Increasing1.E+13

Increasingannealtemperature

1.E+12

0 0.1 0.2 0.3 0.4 0.5

temperature

EC-E (eV)

Figure 6.5: Estimated band tail state density distribution (Nt(E)) near the conductionband minimum for IGZO annealed at 300, 400, 500, 600 C.

Table 6.1 compiles extracted IGZO TFT and space-charge-limited current parame-

ters. Note that there is a strong correlation between mobility and characteristic trap energy

with respect to the post-deposition anneal temperature. Specifically, with increasing an-

neal temperature, mobility increases while the characteristic trap energy decreases. VON

also decreases while n0 increases with increasing post-deposition annealing temperature.

Finally, Nt and N0 appear to be almost constant and display no obvious trend with respect

to post-deposition annealing temperature.

Figure 6.5 shows estimated band tail state density (Nt(E)) distributions correspond-

ing to the N0 and ET values compiled in Table 6.1 for IGZO annealed at 300, 400, 500,

600 C. Although the total number of traps (Nt), as tabulated in Table 6.1, does not vary

111

significantly for the different anneal temperatures, the band tail state distribution is greatly

affected by the anneal temperature. As the post-deposition anneal temperature increases,

the band tail state distribution is spread across a smaller fraction of the bandgap. Con-

versely as the post-deposition anneal temperature decreases the estimated band tail state

distribution widens.

This post-deposition annealing trend is easier to see if it is assumed that N0 is

a constant, allowing Fig 6.5 to be replotted as shown in Fig 6.6. This figure clearly

indicates that band tail state density spreads out over a smaller range of energy with

increasing post-deposition annealing temperature. This means that for a higher post-

deposition annealing temperature fewer band tail states need to be filled with electrons

as the Fermi level approaches EC. In turn, when the Fermi level is able to more closely

approach EC, more extended conduction band states may be populated, leading to an

improved mobility with increasing post-deposition annealing temperature.

It is difficult to directly compare the band tail state density distribution obtained

herein for IGZO to those previously reported in the literature. Hsieh et al. employ a

device simulator to estimate the band tail state distribution of IGZO TFTs prepared by

pulsed laser deposition and post-deposition annealing at 300 C. For enhancement-mode

devices, such as fabricated herein, they report N0 = 5 × 1016 cm−3eV−1 and ET = 1.0 eV

for a model, model 1, involving band states only, and N0 = 2.3 × 1018 cm−3eV−1 and

ET = 80 meV for a model, model 2, involving both band tail and deep gap states. Their

model 1 value for N0 is approximately one order of magnitude greater than our 300 C

estimate, while their model 2 estimate is almost two orders of magnitude greater. Some of

112

1 E+17

1 E 16

1.E+17

1.E+16

V-1

)1.E+15

cm

-3eV

Increasing1.E+14

Nt(c

Increasingannealtemperature

1.E+13

1.E+12

0 0.1 0.2 0.3 0.4 0.5

EC-E (eV)

Figure 6.6: Estimated band tail state density distribution (Nt(E)) near the conductionband minimum for IGZO annealed at 300, 400, 500, 600 C assuming a constant value ofN0 for all annealing temperatures.

this difference can be attributed to the fact that their extraction procedure is based on the

assessment of accumulation layer electrons which are in very close physical proximity

to the insulator-semiconductor interface while space-charge-limited current presumably

involves electrons transiting within the IGZO bulk. Interface trap densities are expected

to be larger than that of the bulk. Note that Hsieh et al. prefer their model 2 fit to their

data. The model 2 trap energy of 80 meV is closer to the 130 meV value herein found for

the IGZO sample annealed at 300 C.

113

6.5 Conclusion

In this chapter a simple method to characterize the band tail state distribution near

the conduction band minimum of a semiconductor by analyzing two-terminal current-

voltage characteristics of a TFT with a floating gate is presented. The characteristics trap

energy (ET ) as a function of post-deposition annealing temperature is shown to correlate

very well with IGZO TFT performance, with a lower value of ET , corresponding to a

more abrupt distribution of band tail states, correlating with improved TFT mobility.

114

7. CONCLUSIONS AND RECOMMENDATIONS FOR FUTUREWORK

The focus of this research is towards the commercialization of oxide-based thin-film

transistors. As such, there are two primary focuses for this dissertation, the utilization of

a commercially feasible route (reactive sputtering from a metal target) towards fabrica-

tion of oxide-based thin-film transistors (TFTs) and an exploration of the effect of gate

dielectric variations on TFT device performance.

Reactive sputtering using a metallic target has several advantages compared to de-

position methods in which a ceramic target is used. [135, 150] Reactive sputtering using

a metallic target usually results in a higher deposition rate. The physical properties of the

metal lead to a more durable target of higher purity and superior thermal conductivity.

Finally, a metallic target is easier to fabricate, requiring less care and cost than is involved

in the fabrication of a ceramic target. By utilizing sputtering from a metal target TFT

performance on par or better than those from a ceramic target is achievable. By varying

oxygen partial pressure, optimized zinc oxide TFTs with mobilities of ∼10 cm2V−1s−1

can be fabricated via reactive sputtering using a metallic target. In addition, devices fab-

ricated near room temperature have incremental mobilities of ∼5 cm2V−1s−1. Also, it is

demonstrated that zinc tin oxide-based TFTs with incremental mobilities as high as ∼32

cm2V−1s−1 can be fabricated via rf and dc reactive sputtering using a metallic target.

By utilization of a metal target, a cheaper and faster route towards oxide semiconductor

deposition is achieved.

115

TFT characteristics are shown to be dominated by the semiconductor-dielectric in-

terface, with silicon dioxide via a TEOS source material being shown to be a relatively

optimal candidate as a gate dielectric for TFT performance. Additionally for each dielec-

tric material, it is hypothesized that deposition parameters for the semiconductor have to

be optimized specifically for each dielectric material.

It is demonstrated that chemical vapor deposited silicon dioxide at low applied

fields behaves identically to thermally grown silicon dioxide when utilized as a dielec-

tric layer in thin-film transistors annealed at 500 C. At high applied fields, the interfacial

roughness of the chemical vapor deposited silicon dioxide detrimentally affects TFT per-

formance of the insulators investigated.

Increasing the gate capacitance density is demonstrated to improve the performance

of an IGZO TFT, yielding a higher current drive, a decrease in subthreshold swing, and a

decrease in the magnitude of the turn-on voltage. The interface state density for IGZO on

CVD silicon dioxide is estimated to be 2.1 × 1012 cm−2eV−1, 2 × 1012 cm−2eV−1, and

1 × 1012 cm−2eV−1 for TFTs annealed at 200 C, 300 C, and 500 C, respectively, in

conjunction with chemical vapor deposited silicon dioxide as the gate insulator.

Additionally, silicon nitride appears to be a poor gate insulator choice for IGZO

TFTs, based on turn-on voltage and transfer curve hysteresis trends, with silicon dioxide

via a TEOS source exhibiting the best TFT characteristics.

Finally, a simple method to characterize the band tail state distribution near the

conduction band minimum of a semiconductor by analyzing two-terminal current-voltage

characteristics of a TFT with a floating gate is presented. The characteristics trap energy

116

(ET ) as a function of post-deposition annealing temperature is shown to correlate very

well with IGZO TFT performance, with a lower value of ET , corresponding to a more

abrupt distribution of band tail states, correlating with improved TFT mobility.

7.0.1 Recommendations for future work

1. Dielectric-semiconductor interface: The majority of carrier movement in TFTs

occurs at the semiconductor-dielectric interface. It follows that the semiconductor-

dielectric interface is crucial to proper TFT operation, as shown in this thesis. Fur-

ther studies into techniques such as a low energy in-situ plasma clean prior to the

semiconductor deposition or sequential deposition of the dielectric and semicon-

ductor layers while maintaining high vacuum may yield TFTs with improved per-

formance.

2. Circuit integration: IGO and IGZO-based ring oscillators have been reported, but

it may be useful to attempt other circuits, such as current mirrors or logic gates.

These circuits place additional requirements on the TFT, such as congruency (for

the current mirror), and may be useful in learning the limits of this nascent technol-

ogy.

3. Vertical integration: Up to this point circuit layout utilizing thin-film transistor

has consumed horizontal surface coverage. Additionally, the effect of stacking

TFTs vertically on device performance is an interesting venue. This approach can

increase display performance two fold: increased switching speed due to higher

current drive and higher resolution due to smaller pixel size. Additionally, with

117

respect to circuit performance, the parasitic resistance can be reduced by reducing

interconnect distances between TFTs.

4. Device stability: It is important to investigate the physical mechanisms (such as

hydrogen diffusion in a-Si:H TFTs) that hinder device stability. Testing of devices

at different temperatures may also be useful; this testing methodology can be used

to extract an activation energy related to device degradation and can be helpful

in fitting oxide semiconductor-based TFT stability data to a degradation model.

Additionally the testing of various device structures, such as passivated TFTs or

dual-gate TFTs, can aid in the analysis of instability and recovery mechanisms.

5. Alternative processing: In this study, temperatures up to 500 C are utilized to im-

prove device performance. This is appropriate when glass is the intended substrate,

however to move from transparent electronics towards flexible electronics requires

the reduction of processing temperatures. Alternatives to thermal processing, such

as laser annealing, microwave treatment, or localized heating via electrical conduc-

tion should be studied as a route towards lower temperature processing.

6. Frequency analysis: Several ring oscillators have been fabricated utilizing oxide-

based TFTs, however the performance of these circuits, operating at frequencies

less than 5 MHz, has been limited by interconnect resistance and parasitic capaci-

tance. How these oxide semiconductors operate at higher frequencies and whether

there is an inherent limitation to their high frequency operation will eventually limit

the utilization of oxide based TFTs.

118

7. Semiconductor layer structure: To date, most TFTs utilize a homogenous semi-

conductor layer. The one exception is the initial IGZO report by Nomura et al. [129]

where the single crystal semiconductor layer consisted of two individual compo-

nents, an InO−2 layer, parallel to the dielectric-semiconductor interface, which al-

lowed electron conduction and a GaO(ZnO5)+ layer which controlled carrier dop-

ing. A similar structure composed of amorphous materials, with a carrier transport

layer capped with a layer to limit carrier doping might be utilized to form a TFT

with a high mobility and turn-on voltage near 0 V.

8. Exploration of degenerate oxide semiconductors: In addition to semiconductor

layer exploration, alternative degenerate oxide semiconductors should be investi-

gated due to the limited supply of In and as a means to reduce parasitic resistance

that degrades circuit performance. A degenerate p-type semiconductor might be

the key to realization of an oxide-based p-type TFT.

9. Exploration of p-channel TFTs: Exploration of p-channel TFTs is recommended

as a means of realizing a complementary circuit technology with oxide-based TFTs.

Potential semiconductor materials include NiO and Cu2O. Additionally, note that

hole injection will likely pose a difficult challenge in forming these TFTs. One

drawback is that most p-type oxides either have poor mobility or require a high

temperature annealing treatment to achieve reasonable performance.

119

BIBLIOGRAPHY

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2. H. Hosono, M. Yasukawa, and H. Kawazoe, “Novel oxide amorphous semicon-ductors: transparent conducting amorphous oxides,” J. Non-Crys. Sol., vol. 203,p. 334, 1996.

3. S. Narushima, M. Orita, M. Hirano, and H. Hosono, “Electronic structure andtransport properties in the transparent amorphous oxide semiconductor 2 cdogeo2,”Phys. Rev. B, vol. 66, p. 035203, 2002.

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Fabrication and Characterization of Thin-Film Transistor Materials and Devices

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