En 528345

© 2004 Microchip Technology Incorporated. All Rights Reserved. dsPIC30F Interrupts 1

DSDigital Signal Controller

dsPIC30F Interrupts

Microchip Technology Inc.Microchip Technology Inc.

Welcome to the dsPIC30F Interrupts Web seminar. My name is RalphFulchiero and in this session you're going to learn how to use the Interrupt Controller on the dsPIC30F.


Session AgendaSession Agenda

ll Interrupt Vectors and Priority SchemeInterrupt Vectors and Priority Schemell Interrupt Nesting and Context SavingInterrupt Nesting and Context Savingll TrapsTrapsll Interrupt ConfigurationInterrupt Configurationll Interrupt TimingInterrupt Timing

The goal of this presentation is to introduce you to the dsPIC30F interrupt controller. The dsPIC30F interrupt controller provides a significant amount of flexibility for the design of your system.

We will start with a review of the interrupt vector table and the interrupt priority scheme. The individual interrupt sources can be assigned to different priority levels to meet the real-time processing requirements of your application. We will also see how the CPU context is saved and restored during interrupt processing.

Special interrupt conditions, such as SLEEP and IDLE mode operation, interruption of DO and REPEAT hardware loops, and the software interrupt disable instruction, DISI, will also be discussed.

A summary of the interrupt control registers and a discussion oninterrupt coding is provided throughout the presentation to help you write your own interrupt handling code.

A discussion about interrupt timing is included in this presenta tion, since interrupt processing latency can be critical in real time processing applications.


Reset - GOTO AddressReserved

Address Error TrapStack Error Trap

Math Error TrapReservedReservedReserved

Oscillator Fail Trap

Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 2

••

Interrupt Vector 53 Reserved

0x0000000x000002

0x0000800x0000820x000084

0x0000FE

Inte

rru

pt

Vect

or

Tab

le

0x000004

Reset - GOTO Instruction

Reserved

0x00007E

Oscillator Fail Trap

Interrupt Vector 53

••••A

ltern

ate

In

terr

up

t V

ect

or

Tab

le

Decreasing Natural Order Priority

Interrupt Vector TableInterrupt Vector Table

Reserved

The dsPIC30F interrupt vector table, or IVT, has a unique interrupt vector associated with each source of interrupt. Each vector location is programmed with the address of the Interrupt Service Routine, or ISR. The IVT supports up to 54 sources of interrupt. The number of implemented vector locations will depend on the peripherals thatare available on the particular dsPIC30F device being used.

There are 4 non-maskable trap vectors at the beginning of the IVT to handle critical hardware problems such as an oscillator failure, math errors, and so on. Later in this presentation, we will explore the various events that cause traps.

There is an alternate Interrupt Vector Table, or AIVT, that can be enabled using a control bit. The AIVT is identical to the IVT, and immediately follows the IVT in the program memory map. The AIVT can be loaded with a different set of ISR addresses than the IVT. This allows the user to use a second set of interrupt handling routines that utilize the peripherals in different ways. The AIVT could also be used for software diagnostic purposes. For example, you might want to program the UART to upload test data to a PC when testing an application.

Note that the RESET vector consumes two program memory locations . The RESET vector is loaded with a GOTO instruction that jumps to the startup code. The RESET location is not a true interrupt vector, as resets are not handled by the interrupt controller.


ll 7 user assigned priority levels 7 user assigned priority levels ll IPL bits (SRL<7:5>) set current CPU priorityIPL bits (SRL<7:5>) set current CPU priorityll Source greater than CPU level can interruptSource greater than CPU level can interruptll CPU updates IPL bits during interrupt CPU updates IPL bits during interrupt

processing processing ll Interrupts with same priority...Interrupts with same priority...

ll Natural priority resolves conflictsNatural priority resolves conflictsll UserUser--assigned priority can override natural priorityassigned priority can override natural priority

Interrupt PriorityInterrupt Priority

You are likely to have a variety of interrupt tasks in your application, with different levels of processing importance. The dsPIC30F interrupt controller allows the user to manage interrupts by setting different priority levels for each interrupt source. There are 8 user-assigned priority levels for each source of interrupt. At the lowest level, level 0, the interrupt source is effectively disabled. Level 7 is the highest programmable priority, and effectively configures the interrupt source to be ‘non-maskable’.

At various stages of program execution, the CPU may operate at different priority levels. After a device reset, the CPU operates at level 0. In order to interrupt the normal program execution flow of the CPU, an interrupt source must have a priority level greater than the present CPU priority. Therefore, an interrupt source programmed to level 0 priority is effectively disabled. While a particular interrupt is being processed, the CPU priority is temporarily raised to the user-assigned priority of that interrupt.

The lower byte of the CPU Status Register, known as SRL, has 3 status bits that indicate the present CPU priority. During the interrupt, SRL is pushed on to the stack to save the old CPU priority level, and the CPU priority status bits then change to indicate the new priority level. Later in this presentation, we will study the stack operation during interrupt entry .

It is possible that multiple interrupt sources can have the same user-programmed priority level. In fact, all interrupt sources default to level 4 priority when the device is reset. When multiple interrupt sources become pending with the same priority level, the final processing order will be resolved by their natural order priority in the IVT. An interrupt vector located at a lower address in the vector table always has a higher natural priority than one at a higher address.

Once the vectoring process for an interrupt source begins, all other pending interrupts with the same programmed priority level remain pending until processing of the current interrupt completes.


Natural Order PriorityNatural Order PriorityHighest Priority

Lowest Priority

IRQ 0, Vector 8

IRQ 1, Vector 9

IRQ 2, Vector 10

IRQ 3, Vector 11

IRQ 4, Vector 12

IRQ 5, Vector 13

TMR2 - Timer 2

TMR3 - Timer 3

IRQ 6, Vector 14

IRQ 7, Vector 15

INT0 - External Int 0

IC1 - Input Capture 1

OC1 - Output Compare 1

TMR1 - Timer 1

IC2 - Input Capture 2

OC2 - Output Compare 2

IRQ 38, Vector 46

IRQ 39, Vector 47

IRQ 40, Vector 48

IRQ 41, Vector 49

IRQ 42, Vector 50

IRQ 43, Vector 51

FLTB - MPWM Fault B

Reserved

IRQ 44, Vector 52

IRQ 45-53, Vector 53-61

CAN2 - Combined IRQ

PWM - Period Match

QEI - Counter Compare

DCI - Transfer Done

PLVD - Low Volt. Detect

FLTA - MPWM Fault A

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.

.

.

.

.

This slide shows a section of the IVT depicting the natural order priority for various interrupt sources. Remember that the natural priority provided by the IVT can be always be overridden by assigning a source with low natural priority to a high user priority level or vice versa.

The fixed natural priority of the IVT is only considered when multiple interrupt sources with the same user assigned priority level become pending.

For instance, if the Timer2 and Timer3 interrupts have the same user-defined interrupt level and simultaneously become asserted, Timer2 will be serviced first, since it has a higher natural priority.


W15 (before interrupt)

W15 (after interrupt)

PC<15:0>PC<22:16>

0150x0800

SRL

SRL pushed ontostack to preserveprevious priority level.

Stack OperationStack Operation

ll PC<23:0> and SRL pushed onto software stackPC<23:0> and SRL pushed onto software stackll SRL contains IPL status bitsSRL contains IPL status bits

IPL3 bit saved on stack here.

LL

0xFFFF

This diagram illustrates the stack operation for an interrupt. When an interrupt is serviced the current Program Counter, lower Status Register byte (called SRL) and IPL3 bit are pushed onto the stack.

The SRL register contains the CPU Interrupt Priority Level, called IPL, such that the CPU priority level before the interrupt is saved. There is actually a fourth priority level status bit, called IPL3, in the Core Control register or CORCON.

The IPL3 bit is used to indicate when a trap is in progress. The IPL bits 0 through 2 in SRL and the IPL3 bit in CORCON, are combined to form a priority level number between 0 and 15.

In special situations, the user application could potentially modify the values saved on the stack to allow the CPU to return to a higher or lower priority after the ISR executes.


Interrupt Context Interrupt Context Save/Restore Save/Restore

ll SRL and PC saved automatically to stackSRL and PC saved automatically to stackll Use PUSH(.D) and POP(.D) to save/restoreUse PUSH(.D) and POP(.D) to save/restorell PUSH.S and POP.S allow fast context savePUSH.S and POP.S allow fast context save

ll W0, W1, W2 and W3W0, W1, W2 and W3ll MCU ALU Status Bits (DC, Z, N, OV, C)MCU ALU Status Bits (DC, Z, N, OV, C)

ll Be careful when using W shadows for Be careful when using W shadows for different priority tasksdifferent priority tasks

As we just saw, the SRL register, interrupt priority level bits, and PC value are saved automatically on the software stack when an inte rrupt occurs. This preserves the MCU status bits (except DC), the old CPU priority, and the RA (repeat active) status bit.

Any other registers that are shared between the user’s mainline code and ISR must be preserved by the user software.

The Working registers can be saved using PUSH and PUSH.D instructions to place them on the software stack. The PUSH instruction saves a single W register, while the PUSH.D instructions will save two consecutive W registers using a single instruction. The POP and POP.D instructions complement the push instructions and can be used torestore the W registers.

The dsPIC30F has a special set of shadow registers for quickly saving multiple registers. The PUSH.S and POP.S instructions can be used to save the W0, W1, W2 and W3 registers into shadow registers in a single cycle. They also save the DC, Z, N, OV, and C MCU ALU status bits.

The shadow registers are only one level deep, so care should be taken when using the PUSH.S and POP.S instructions.


Interrupt Nesting Interrupt Nesting

ll Interrupts are nestable by defaultInterrupts are nestable by defaultll An ISR may be interrupted by a higher An ISR may be interrupted by a higher

priority interruptpriority interruptll Nesting can be disabled by setting NSTDIS Nesting can be disabled by setting NSTDIS

bit in INTCON1 registerbit in INTCON1 registerll Priority of interrupts set to 7 when servicedPriority of interrupts set to 7 when servicedll IPL bits are readIPL bits are read--only in this mode only in this mode

ll Temporarily raising CPU interrupt priority to Temporarily raising CPU interrupt priority to 7 in ISR can also disable nesting7 in ISR can also disable nesting

By default, interrupts are nestable, which means that any ISR that is in progress may be interrupted by another interrupt source with a higher user assigned priority level. Interrupt nesting may be optionally disabled by setting the Nesting Disable control bit in the INTCON1 register. When the Nesting Disable bit is set and an interrupt is being processed, the hardware automatically forces the CPU interrupt priority to level 7 by setting the IPL bits in the CPU Status Register. This effectively masks all other interrupt sources until the current ISR has been completely executed.

When interrupt nesting is disabled, the user assigned interrupt priority levels will have no effect, except to resolve conflicts between simultaneous pending interrupts. Also, note that the CPU interrupt priority bits become read-only when interrupt nesting is disabled. This prevents the user software from re-enabling interrupt nesting by manually lowering the CPU interrupt priority.


Traps for Robust OperationTraps for Robust Operation

ll NonNon--maskable interrupt sourcesmaskable interrupt sourcesll Detect catastrophic hardware/software Detect catastrophic hardware/software

problemsproblemsll Traps have priority above all user interrupt Traps have priority above all user interrupt

levelslevelsll level 8 to level 15level 8 to level 15

ll Adhere to natural priority in IVTAdhere to natural priority in IVTll Status flags indicate source of trapStatus flags indicate source of trapll Hard traps halt normal executionHard traps halt normal executionll Soft traps function similar to an interrupt sourceSoft traps function similar to an interrupt source

Traps act as non-maskable sources of interrupt that are used to signal hardware errors. The dsPIC30F recognizes four trap sources - oscillator failure, address error, stack error, and math error.

There is no user-assigned priority for traps. The priority level for each trap is determined by the position of the corresponding trap vector in the IVT. Trap sources have priority levels 8 through 15. As indicated previously, the IPL3 bit is used with the IPL<2:0> status bits to indicate a priority level between 0 and 15. When a trap is in progress, the IPL3 bit will be set to indicate that the priority level is 8 or higher.

There are two types of traps - ‘hard’ traps and ‘soft’ traps. A hard trap source stops all further execution of instructions when the trap becomes pending. No other code can be executed other than the trap handler code for the hard trap source. As a result, a trap conflict will result if and when multiple hard traps become pending. A trap conflict will cause the device to get reset.

In contrast, a soft trap functions more like an ordinary interrupt source in that instruction execution in the normal program flow can continue during the arbitration and vectoring process.

A trap handler can be written to either correct a problem if possible, or perform an orderly shutdown in the event of a serious problem. If no corrective action is to be taken, a RESET instruction can be used in the trap handler in order to cleanly reset the CPU.


Traps for Robust OperationTraps for Robust Operation

ll Oscillator Failure Trap (level 14 Oscillator Failure Trap (level 14 -- hard trap)hard trap)ll Address Error Trap (level 13 Address Error Trap (level 13 -- hard trap)hard trap)

ll Instruction fetch from illegal program spaceInstruction fetch from illegal program spacell Data fetch from unimplemented data spaceData fetch from unimplemented data spacell Unaligned word access from data spaceUnaligned word access from data space

ll Stack Error Trap (level 12 Stack Error Trap (level 12 -- soft trap)soft trap)ll Stack overflow or underflowStack overflow or underflow

ll Math Error Trap (level 11 Math Error Trap (level 11 -- soft trap)soft trap)ll Divide by ZeroDivide by Zeroll Unsaturated Accumulator Overflow (A or B)Unsaturated Accumulator Overflow (A or B)ll Catastrophic Accumulator Overflow (either)Catastrophic Accumulator Overflow (either)ll Accumulator Shift OverflowAccumulator Shift Overflow

The 4 trap sources available in the dsPIC30F are listed here. The oscillator failure trap and address error trap fall into the category of hard traps. The stack error trap and math error trap are soft traps.

An oscillator failure trap will occur if the fail-safe clock monitor (FSCM) is enabled and detects a clock failure. In such cases, the device will switch to and run on the 8 MHz Fast RC oscillator.

Address error traps can be caused by multiple reasons, including an attempt to fetch data from unimplemented data or program memory spaces. The illegal program space includes the interrupt vector table. To ensure robust operation, the dsPIC30F forces the address of all word (16-bit) operations in data memory to be aligned to an even address. If a word access is attempted with the LSbit of the data address value set, an address error trap will occur.

A stack error trap will occur if the stack pointer W15 is less than 0x800, W15 is greater than the user-programmed Stack Pointer Limit register value, or W15 wraps around the end of data space.

A math error trap can be generated for several, as shown here. An unsaturated accumulator overflow occurs when the accumulator value overflows from the lower 32 bits into the upper 8 guard bits. A catastrophic overflow occurs when the entire 40 bit accumulator overflows, causing the sign of the accumulator value to change. A math error trap will also occur if the result of a DSP shifting operation causes the accumulator to overflow.

All traps are non-maskable, with the exception of the unsaturated and catastrophicaccumulator overflow traps. These sources of trap can be enabled or disabled using control bits in the INTCON1 control registers to achieve the desired operation.


Interrupt DisableInterrupt Disable““DISIDISI”” InstructionInstruction

ll DISIDISI disables level 1 disables level 1 -- 6 interrupts for 6 interrupts for ““N+1N+1””instruction cyclesinstruction cyclesll Supports a maximum of 16384 cyclesSupports a maximum of 16384 cyclesll Example UsageExample Usage

DISI #5 ; disable for 6 cyclesDISI #5 ; disable for 6 cyclesll DISICNT register holds disable count valueDISICNT register holds disable count value

ll DISI expires when DISICNT decrements to 0DISI expires when DISICNT decrements to 0

ll DISICNT can be written to modify DISI timeDISICNT can be written to modify DISI timell DISICNT can be cleared to cancel instructionDISICNT can be cleared to cancel instruction

ll DISI status bit (INTCON2<14>)DISI status bit (INTCON2<14>)

The Disable Interrupts, or DISI, instruction is useful for temporarily suspending interrupt processing during critical tasks. For example, you may need to run a filter algorithm in a certain amount of time to meet real-time requirements, or you may want to disable interrupts while performing a clock switch or reprogramming FLASH memory.

The DISI instruction will temporarily disable interrupts with priorities from level 1 to level 6 for a time period up to 16,384 cycles. When the DISI instruction is executed, the specified count value is loaded into the DISI Count register. The DISI Count register will be decrement by the hardware on each successive instruction cycle and interrupts will be re-enabled after the count value reaches 0. There is a status bit that specifies when the DISI instruction is active.

If you wish to extend the amount of time the DISI instruction is active, it is possible to write a new value to the DISI Count register after a DISI instruction has been executed and the DISICNT register has a non-zero value. Note that interrupts cannot be disabled by simply writing a value to DISICNT. It is necessary to first execute the DISI instruction.

Once interrupts have been disabled, one can cancel the effect of the DISI instruction by clearing the DISI Count register.

Note that DISI only disables interrupts with priorities up to level 6. Interrupts with priority level 7 are not disabled by the DISI instruction.


SLEEP and IDLESLEEP and IDLE

ll Device will wake from SLEEP or IDLE with Device will wake from SLEEP or IDLE with any enabled interrupt source (IE bit set)any enabled interrupt source (IE bit set)

ll Execution will continue from ISR if Interrupt Execution will continue from ISR if Interrupt priority is higher than the current CPU prioritypriority is higher than the current CPU priority

ll Execution will continue with the main Execution will continue with the main program flow if the interrupt priority level is program flow if the interrupt priority level is equal to or less than the current interrupt equal to or less than the current interrupt prioritypriority

The dsPIC30F has two power-saving modes of operation: SLEEP and IDLE. In the SLEEP mode, all CPU and peripheral functions are turned off and the system clock source is shut down. Only peripherals that are externally clocked or provide their own clock source will continue to run in SLEEP. In IDLE mode, the CPU is shut down but the system clock source and selected peripherals continue to operate. These power-saving modes are very useful in applications in which the processor is idle except when responding to specific peripheral events such as an incoming message on a communication channel.

An interrupt source must be used to ‘wake-up’ the processor from SLEEP or IDLE mode. When the interrupt status flag for a source is set and the interrupt source is enabled via the corresponding bit in the IEC Control registers, a wake-up signal is sent to the CPU. When the device wakes from SLEEP or IDLE mode, one of two actions may occur:

1. If the interrupt priority level for that source is greater than the current CPU priority level, then the processor will process the interrup t and branch to the ISR for the interrupt source.

2. If the user assigned interrupt priority level for the source is less than or equal to the current CPU priority level, then the processor will simply continue execution, starting with the instruction immediately fo llowing the PWRSAV instruction that previously put the CPU in SLEEP or IDLE mode.


REPEAT LoopsREPEAT Loops

ll REPEAT can be interrupted and nestedREPEAT can be interrupted and nestedll RA bit is stacked with SRLRA bit is stacked with SRLll RA bit is cleared on interrupt entryRA bit is cleared on interrupt entry

ll User must manually stack RCOUNT to User must manually stack RCOUNT to nest REPEAT loopsnest REPEAT loops

The REPEAT instruction allows a single instruction to be executed multiple times. Unlike other competitive architectures, the target REPEAT instruction may be interrupted.

If a REPEAT instruction is interrupted, the Repeat Active or RA status bit, being part of the SRL register, is automatically saved on the stack. The RA bit is then automatically cleared by the hardware within the ISR so normal execution can occur. You can then execute another REPEAT loop within the ISR, but you must manually save and restore the RCOUNT register that holds the count value of the REPEAT loop that was underway in the mainline code.


DO LoopsDO Loops

ll DO can be interruptedDO can be interruptedll Hardware provides 2 levels of DO context Hardware provides 2 levels of DO context

savingsavingll DOSTART, DOEND, DCOUNTDOSTART, DOEND, DCOUNT

ll Must consider number of nested DO levels Must consider number of nested DO levels for interrupt processingfor interrupt processing

ll DL status bits (CORCON register) shows DL status bits (CORCON register) shows the level of nestingthe level of nesting

A DO loop can also be interrupted. If you plan to execute DO loops in the foreground code as well as in the ISR, you should consider the number of nested DO loops so that the status of outer loops can be properly saved. The DO instruction hardware provides automatic context saving for the first two levels of DO loops. For DO levels beyond the the second, the user software needs to manually save and restore the DOSTART, DOEND, and DCOUNT registers. The DL status bits in the CORCON register can be read to determine the current level of DO loop nesting.


-U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

bit7 6 5 4 3 2 1 bit0OSCFAILSTKERRADDRERRMATHERR---

COVTER/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

bit15 14 13 12 11 10 9 bit8OVBTEOVATE----NSTDIS

INTCON1

INT0EPU-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit7 6 5 4 3 2 1 bit0INT1EPINT2EPINT3EPINT4EP---

-R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

bit15 14 13 12 11 10 9 bit8-----DISIALTIVT

INTCON2

Interrupt ConfigurationInterrupt Configuration

INT0IER/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit7 6 5 4 3 2 1 bit0IC1IEOC1IET1IEIC2IEOC2IET2IET3IE

SPI1IER/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit15 14 13 12 11 10 9 bit8U1RXIEU1TXIEADIENVMIEI2CIEBCLIECNIE

IEC0 (One of four Interrupt Enable Registers)

The INTCON1 and INTCON2 registers are used to control operation of interrupts. Bits 1 through 4 if the INTCON1 register have status flags that indicate which non-maskable trap events have occurred. Bits 8 through 10 contain control bits that optionally enable catastrophic and non-catastrophic accumulator overflow traps. Bit 15 is the NSTDIS control bit, which disables interrupt nesting. When the NSTDIS bit is set, all interrupts are forced to execute as a level 7 priority interrupt. This prevents other interrupt sources from interrupting the ISR in progress.

Bits 0 through 4 of the INTCON2 register set the edge polarity for each of the external interrupt pin sources. Each of the five external interrupt pins can trigger an interrupt on a rising edge or falling edge of the input signal. Bit 14 contains the DISI status bit, which indicates when interrupts have been disabled as a result of the DISI instruction. Bit 15 is the ALTIVT control bit, which is used to enable the alternate interrupt vector table for interrupt processing.

Also shown here is an example of an Interrupt Enable Control, or IEC, register. There are three IEC registers in the dsPIC30F. Each bit contains an interrupt enable bit for an interrupt source. To interrupt the CPU, the user must set the corresponding IE bit to enable the interrupt source.


INT0IFR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit7 6 5 4 3 2 1 bit0IC1IFOC1IFT1IFIC2IFOC2IFT2IFT3IF

SPI1IFR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit15 14 13 12 11 10 9 bit8U1RXIFU1TXIFADIFNVMIFI2CIFBCLIFCNIF

IFS0 (one of four Interrupt Flag Status Registers)

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

bit7 6 5 4 3 2 1 bit0INT0IP<2:0>IC1IP<2:0>-

bit15 14 13 12 11 10 9 bit8

IPC0

-

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0OC1IP<2:0>T1IP<2:0>- -

(One of twelve Interrupt Priority Control Registers)


Shown here is an example of an Interrupt Priority Control, or IPC, register. The dsPIC30F has up to twelve IPC registers. The IPC registers have 3-bit fields that specify the priority level of each interrupt source.

Also shown here is an example of an Interrupt Flag Status, or IFS, register. There are three IFS registers in the dsPIC30F. Each bit contains an interrupt flag status bit that indicates if a particular interrupt source generated an interrupt request to the Interrupt Controller. An interrupt is generated only when the interrupt flag associated with the corresponding interrupt source becomes set. Note that interrupt flags get set even if the interrupt is not enabled, or even if the interrupt is of insufficient priority.


ll General steps to configure an interrupt:General steps to configure an interrupt:ll Set the priority bits in the appropriate IPC Set the priority bits in the appropriate IPC

registerregisterll Clear the interrupt flag in the appropriate IFS Clear the interrupt flag in the appropriate IFS

registerregisterll Set the interrupt enable bit in the appropriate Set the interrupt enable bit in the appropriate

IEC registerIEC registerll Configure the peripheral interrupt sourceConfigure the peripheral interrupt sourcell Enable the peripheral interrupt sourceEnable the peripheral interrupt source


The steps that you will need to take to initialize an interrupt source are listed here.


Interrupt Entry Timing: Interrupt Entry Timing: 11--cycle Instructioncycle Instruction

The dsPIC30F interrupt controller has a 5 instruction cycle entry latency while entering an ISR, and a 3 cycle latency when returning from the ISR. It is important to know the interrupt processing latency for many real time applications. Let us look at the interrupt processing timing in greater detail.

This example shows the interrupt timing when a one cycle instruc tion is interrupted. The interrupt flag status bit is set during the ins truction cycle after the peripheral interrupt event occurs. The current instruction completes during this instruction cycle. In the second instruction cycle after the interrupt event, the contents of the Program Counter and SRL registers are saved into a temporary buffer register. The second cycle of the interrupt process is executed as a forced No-operation to maintain consistency with the sequence taken during a two-cycle instruction. In the third cycle, the Program Counter is loaded with the vector table address for the interrupt source and the starting address of the ISR is fetched. In the fourth cycle, the Program Counter is loaded with the ISR address. The fourth cycle is executed as a No-op while the first instruction in the ISR is fetched. Thus, the interrupt entry latency is 5 cycles when the cycle during which the interrupt event occurred is considered.


Interrupt Entry Timing: Interrupt Entry Timing: 22--cycle Instructioncycle Instruction

Now, let us look at the timing that occurs when a two cycle instruction is interrupted. The 5-cycle latency is exactly the same as when a single cycle instruction is interrupted. The second cycle after the interrupt event is used to execute the second cycle of the two cycle instruction. You would recall that this second cycle is executed as a forced No-op when a single cycle instruction is interrupted.

It is possible that an interrupt event coincides with the first cycle of a two cycle instruction. In such a situation, the second cycle of the instruction is completed in the cycle following the interrupt event. Again, the second cycle following the interrupt event will be executed as a forced No-op.


Return from Interrupt TimingReturn from Interrupt Timing

The Return From Interrupt instruction takes 3 cycles to execute. The SRL and the upper byte of the PC are popped off the stack during the first cycle. The lower word of the Program Counter is popped during the second cycle. The third cycle is executed as a forced No-op to allow the pipeline to refill.

Note that “Return From Interrupt”, RETURN, and “Return with Literal in W-register” are all 3 cycle instructions. If the CPU is interrupted during one of these instructions, the forced No-op cycle will be aborted and the instruction will execute as if it were 2 cycles. This helps maintain a consistent interrupt latency of 5 cycles under all conditions.


Device Selection ReferenceDevice Selection Reference Document #Document #

ll General Purpose and Sensor Family Data SheetGeneral Purpose and Sensor Family Data Sheet DS70083DS70083

ll Motor Control and Power Conv. Data SheetMotor Control and Power Conv. Data Sheet DS70082DS70082

ll dsPIC30F Family Overview dsPIC30F Family Overview DS70043DS70043

Base Design ReferenceBase Design Reference Document #Document #

ll dsPIC30F Family Reference ManualdsPIC30F Family Reference Manual DS70046DS70046

ll dsPIC30F ProgrammerdsPIC30F Programmer’’s Reference Manuals Reference Manual DS70030DS70030

ll MPLABMPLAB®® C30 C Compiler UserC30 C Compiler User’’s Guides Guide DS51284DS51284

ll MPLAB ASM30, LINK30 & Utilities UserMPLAB ASM30, LINK30 & Utilities User’’s Guides Guide DS51317DS51317

ll dsPICdsPIC®® Language Tools Libraries UserLanguage Tools Libraries User’’s Guides Guide DS51456DS51456

Key Support Documents

For more information, here are references to some important documents that contain a wealth of information about the dsPIC30F family of devices.

The Family Reference Manual contains detailed information about the architecture and peripherals, whereas the Programmer’s Reference Manual contains a thorough description of the instruction set.


Device Specific ReferenceDevice Specific Reference Document #Document #

ll dsPIC30F2010 Data SheetdsPIC30F2010 Data Sheet DS70118DS70118

ll dsPIC30F2011/2012/3012/3013 Data SheetdsPIC30F2011/2012/3012/3013 Data Sheet DS70139DS70139

ll dsPIC30F3014/4013 Data SheetdsPIC30F3014/4013 Data Sheet DS70138DS70138



ll dsPIC30F6010 Data SheetdsPIC30F6010 Data Sheet DS70119DS70119

ll dsPIC30F6011/12/13/14 Data SheetdsPIC30F6011/12/13/14 Data Sheet DS70117DS70117

Microchip Web Site: Microchip Web Site: www.microchip.com/dspicwww.microchip.com/dspic

Key Support Documents

For device-specific information such as pinout diagrams, packaging and electrical characteristics, the device datasheets listed here are the best source of information.

All these documents can be obtained from the Microchip web site shown, by clicking on the “dsPIC® Digital Signal Controllers” or “Technical Documentation” link.

Well… this wraps up the seminar on dsPIC30F Interrupts. Thank you for your interest in the dsPIC30F Family of Digital Signal Controllers.

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