ACTIVITIES OF THE GROUP OF HIGH PERFORMANCE INTEGRATED CIRCUITS DESIGN GROUP

Variations-Aware Circuit Designs for Microprocessors

Marc Pons, Thesis Advisors: Francesc Moll, Jaume Abella
Electronic Engineering DepartmentUniversitat Politcnica de Catalunya

OUTLINE

Integrated Circuits ManufacturingThe Need for RegularityConclusion
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IC MANUFACTURING
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[ASML]

LITHOGRAPHY LIMITS
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RESOLUTION ENHANCEMENT TECHNIQUES
RETs are applied to mitigate process variationsHowever RETs are computationally expensive for large circuits with arbitrary layout patterns

DECREASING YIELD
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[Synopsys]

INCREASING COSTS
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DECREASING BENEFITS
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DECREASING YIELD
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[Synopsys]

REGULARITY
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LAYOUT LAYERS
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CONVENTIONAL(IRREGULARITY)
OUR PROPOSAL(REGULARITY)

ADDER LAYOUTS
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CONCLUSION
Lithography Process Variations reduce Integrated Circuits YieldWe propose to include Regularity in design to mitigate Process VariationsWe are studying the trade-offs involved

Thank you for your attention!
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WYS is not WYG
RETs are computationally expensive and very time-consuming for large integrated circuits with arbitrary layout patterns