ELEC2141 (Digital Circuit Design)
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Faculty of Engineering School of Electrical Engineering & Telecommunications ELEC 2141 DIGITAL CIRCUIT DESIGN SESSION I, 2014
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Transcript of ELEC2141 (Digital Circuit Design)
Faculty of Engineering
School of Electrical Engineering & Telecommunications
ELEC 2141
DIGITAL CIRCUIT DESIGN
SESSION I, 2014
THE UNIVERSITY OF NEW SOUTH WALES
SCHOOL OF ELECTRICAL ENGINEERING & TELECOMMUNICATIONS
ELEC2141 – DIGITAL CIRCUIT DESIGN
SESSION I – 2014
COURSE STAFF
Academic-in-
Charge:
Dr. Aron Michael Room EE 305 [email protected]
Lecturer: Dr. Aron Michael Room EE 305 [email protected]
Tutors: Dr. Aron Michael
Dr. Ediz Cetin
Room EE 305
Room EE 127
Laboratory
Demonstrators:
Astria Irfansyah
Christopher Hines
Cam Brown
Hayden Wittig
Hugh Braico
John Lam
Mark Johnson
William Andrew
[AI]
[CH]
[CB]
[HW]
[HB]
[JL]
[MJ]
[WA]
Consultations:
Official consultation hour for this subject is on every Tuesday 16-17 throughout the session.
The session is to provide students with an opportunity to discuss technical and other issues
related to the course with the course lecturer.
Although there is official consultation hour, students may seek consultation at any convenient
time in the lecturer’s office, room EE 305. Prior appointment is recommended.
Students are encouraged to post questions related to the course syllabus on the Moodle
discussion forums. Such questions will be addressed by the lecturer, other course staff and
fellow students.
COURSE DETAILS
Credits:
The course is a 6 UoC course; expected workload is about 10-12 hours per week throughout the
12 week session.
Contact Hours:
The course consists of 3 hours of lectures, 1 hour of tutorials and 2 hours of laboratory sessions
each week.
Lectures:
Tuesday
Thursday
14-16
16-17
CLB 8
CLB 6
Tutorial:
Monday
Monday
Wednesday
Wednesday
Thursday
11 - 12
14 - 15
16 - 17
17 - 18
14 - 15
Quad G031
JGoodsLG21
OMB144
Col LG02
JGoodsLG21
Laboratory:
Monday
Tuesday
Wednesday
Wednesday
Thursday
Friday
Friday
Friday
17 - 19
11 - 13
11 - 13
14 - 16
13 - 15
09 - 11
11 – 13
13 - 15
EE 233
EE 233
EE 233
EE 233
EE 233
EE 233
EE 233
EE 233
Tutorial and laboratory classes will start in week 2 and week 4, respectively.
COURSE INFORMATION
Scopes: Digital circuits are integral parts of many areas of engineering and technology such as personal
computers, digital signal processing, telecommunications, speech analysis and recognition, and
control systems. The objective of this course is to equip students with the necessary
fundamental knowledge and skill that enable them to understand, analyse and design digital
circuits in the real world. The first half of the course will focus on the analysis and design of
combinational and sequential logic circuits. Verilog Hardware Description Language,
arithmetic circuits, computer design fundamentals and CMOS and TTL technologies will be
covered in the second half of the course. At the completion of the course, students should be in
a position to be able to design and build reliable and cost-effective digital circuits.
Aims:
The course aims to provide students with fundamental knowledge of digital systems with
respect to several different levels of abstraction – from a low-level dealing with electrical
circuits through to a high-level dealing with software tools and hardware description languages.
Relation to other courses:
The course is a second-year subject in the school of Electrical Engineering and
Telecommunications at the University of New South Wales. It is a core subject for students
following a BE (Electrical) or (Telecommunications) program.
Pre-requisites:
The pre-requisite for this course is ELEC1111(2): Electrical and Telecommunications
Engineering, which introduced basic concept of electrical circuits.
Following courses:
This course is a pre-requisite for ELEC2142: Embedded Systems Design, in which the digital
system design concepts introduced in ELEC2141 will be applied extensively. It is also a pre-
requisite for ELEC3106: Electronics, in which low-level analysis and implementation of
various logic gates are undertaken.
References:
The textbook prescribed for this course is:
M. M. Mano & C. R. Kime, Logic and Computer Design Fundamentals, 4th
Edition,
Prentice Hall, 2008
Students are strongly encouraged to purchase a copy of this book as lectures will follow the
book very closely and the book provides detailed explanations for most topics covered in the
course. The textbook can also serve as a reference for some of the low-level material covered in
ELEC2142: Embedded System Design.
The following textbooks provide alternate coverage of many of the topics discussed in lectures
and constitute adequate reference material:
R. H. Katz & G. Borriello, Contemporary Logic Design, 2nd
Edition, Prentice Hall,
2005
M. M. Mano & M. D. Ciletti, Digital Design, 4th
Edition, Prentice Hall, 2007
J. F. Wakerly, Digital Design: Principles and Practices, 4th
Edition, Prentice Hall, 2006
LEARNING OUTCOMES AND ATTRIBUTES
Learning outcomes: The aim of this subject is to provide students with a general understanding and an appreciation
of the fundamentals of digital circuits and simple microprocessor design. At the successful
completion of this course, students should be able to:
Analyse and design combinational circuits
Display a basic understanding of standard digital circuit elements such as multiplexers,
decoders, etc.
Design and optimize simple synchronous sequential circuits
Understand the fundamentals of the central processing unit (CPU) in a computer
Demonstrate knowledge in practical aspects of digital circuits and systems, and their
use in more complex systems
Demonstrate understanding of the various hardware realizations of the basic digital
circuit elements
Demonstrate basic skills in working with computer-aided design tools, including
knowing the rudiments of a hardware description language (Verilog)
Implement simple designs at various levels, from discrete components to programmable
logic devices
Contribution of course to graduate attributes:
Graduate attributes are those which the University and the Faculty of Engineering agree
students should develop during their degree. This course aims to aid students in attaining the
following attributes:
Information literacy – the skills to appropriately locate, evaluate and use relevant
information, which is addressed by tutorial questions, assignments and laboratory tasks
The ability to engage in independent and reflective learning, which is addressed by
laboratory exercises and assignments.
The capacity for enterprise, initiative and creativity, which is addressed by design and
implementation assignments
The capacity for analytical and critical thinking and for creative problem-solving,
which is addressed by tutorial questions, weekly quizzes, assignments and final exam.
Further information can be obtained in the document available at:
http://learningandteaching.unsw.edu.au/content/userDocs/grad_attributes.pdf .
SYLLABUS
Introduction to digital systems, number systems, binary numbers, base conversion, binary
codes. Binary variables, logical operators, logic gates, Boolean functions, Boolean algebra,
standard forms, two-level optimization, Karnaugh maps, don’t-care conditions, multi-level
optimization, high-impedance outputs. Combinational logic design procedures, technology
mapping, function blocks, multi-bit variables, encoders, decoders, multiplexers,
demultiplexers. Sequential circuits, basic storage elements, latches and flip-flops structures,
direct inputs, finite state machines, transition equations, state tables and diagrams, state
assignments, logic diagrams, Mealy and Moore models, state minimization. Arithmetic circuits,
half and full adders, cascading adders, signed numbers and 2’s complements, subtractors.
Programmable devices, FPGAs, hardware description languages, Verilog implementations,
simulations. Introduction to computer design, datapaths, arithmetic/logic unit (ALU), shifters,
instructions set. Integrated circuits (ICs), CMOS technology, CMOS logic gates.
TEACHING STRATEGIES
Delivery mode:
The course consists of the following elements: face-to-face lectures delivered in class, tutorials,
laboratory works, short quizzes and two assignments.
Course web page:
The course web page is hosted on the UNSW’s Moodle server, which can be accessed at:
https://moodle.telt.unsw.edu.au/. All lectures, tutorial, lab and any other notes will be available
on this page, as well as access to the fortnightly quizzes, student marks, discussion forums and
official course announcements. It is a requirement of the course that students check this page
for new announcements on a daily basis.
Course Schedule:
Week Topic
1 Introduction to digital systems and Number systems
2 Combinational Logic Circuit I
3 Combinational Logic Circuit II
4 Combinational Logic Design I
5 Combinational Logic Design II
6 Sequential Circuit Elements
7 Sequential Circuit Analysis
BREAK
8 Sequential Circuit Design
9 Verilog HDL
10 Arithmetic Circuits
11 Computer Design Fundamentals
12 CMOS Technology
Lectures:
The lectures form the core of this subject. Topics presented in lectures will generally be
followed by detailed examples to provide students with the real-life applications. Detailed
explanations of the topics will be available to students in the form of lecture notes and the
prescribed textbook.
Tutorials:
The tutorial problems provide students with in-depth quantitative understanding of the topics
covered in lectures. Every tutorial session will have a corresponding problem sheet that covers
the topics taught in the previous week’s lectures. Students are expected to attempt the tutorial
questions before attending the class and raise any problems incurred during the tutorial session.
Laboratory work:
During the laboratory sessions, students will be introduced to real-life digital design scenarios.
Each week, a new design problem related to the lectured material is presented. Students will be
required to step through the problem to a complete solution using the guidelines given per lab
exercise. The laboratory exercises cover a wide scope ranging from using breadboards and
discrete IC components to using industry-standard design software and FPGA implementation.
The exercise will follow similar (although simplified) design procedures used in industry.
Students will need to bring their own breadboards, previously used in ELEC1111, to the
laboratory. Breadboards will also be offered for sale through the school office.
A broad understanding of the tools utilized in these exercises is highly encouraged and a bonus
lab task will be available to students after the successful completion of all other exercises. The
bonus task will carry on from the last lab exercise and will be accompanied by minimal
guidelines, allowing students to further demonstrate their ability to analyse and resolve issues
independently. There are two optional labs which students are encourage to carry out for an
extra lab mark on the top of the bonus task. These optional labs should be done under minimal
supervision and only considered or marked after the student has finished all mandatory labs.
Short online quizzes:
There will be fortnightly quizzes throughout the semester. The purpose of the quizzes is to keep
students up-to-date with the lecture material and to test basic understanding of the course
concepts. Each quiz will consist of several multiple choice questions that target specific topics
from the previous two weeks lectures.
The quizzes are delivered through Moodle and will each be made available for a period of two
weeks between every Saturday at 9:00am to the following Saturday at 9:00am, after which a
new quiz will become available.
Assignments:
There will be two assignments for this subject due at the end of Week 6 and 11. The
assignments will be released at the end of week 3 and week 7, respectively, on Moodle. The
assignments will consist of one or more design problems and students are required to provide a
complete design solution with verified implementations. Through these assignments, students
will address most of the core topics covered in lectures thus far.
Though generic guidelines will be provided, there will be no one “correct” solution to the
assignments. Students will be expected to work independently on their implementation and to
be able to justify the unique design choices along the way.
ASSESSMENT There are four components of the assessment in this course:
Fortnight quizzes 5%
Assignments (2) 15%
Assignment 1 due at the end of week 6
Assignment 2 due at the end of week 11
Laboratory work 15% (+ 5% bonus +
2% optional labs)
Laboratory Exam 5%
Final Exam 60%
Total 100%
1. Fortnight quizzes:
The fortnightly quizzes will make up 5% of the overall mark. Each quiz will consist of a
number of multiple choice questions and will be marked according to the number of correct
answers. The quizzes are a mandatory component of the overall assessment and failure to
attempt a quiz will result in no marks being given for the quiz. Each quiz will be available
for a period of two weeks and the results per quiz will be published at the end of the period.
No late attempts will be permitted. Students must attempt all quizzes to pass this
subject.
2. Assignment:
The assignments, which will consist of design challenges, form 15% of the overall mark. It
will be assessed upon the successful completion of the implementation and the steps taken
during the design process. Marks will be weighted towards students’ understandings and
their ability to justify the design decisions. The assignments will be available at the end of
week 3 and week 7. Submissions of the assignments will close at the end of Week 6 and
Week 11, respectively. Late submissions will attract penalty.
3. Laboratory work:
The laboratory work will contribute to 15% of the overall mark. Each lab exercise will have
one check point that will be marked by the lab assessors. Although there is only one check
point for each lab, there are a number of results that students are required to demonstrate
when marked for the check point. Therefore, students are strongly advised to: (i) record
results on the lab manual; (ii) save the accomplished task or results on working directory in
the lab PC; (iii) keep the working circuit on the breadboard for demonstrator to check.
Demonstrators will be available to help students with any questions or difficulties.
Upon completion of a checkpoint, students will be required to write down their student and
bench numbers on the Laboratory Queue Sheet and wait for the laboratory assessor to mark
their work. Students may continue working on subsequent lab tasks while waiting to be
assessed. Students will be required to show the working of their task for each checkpoint
and answer questions asked by the assessor to demonstrate their understanding of the ideas
addressed within each task. Attendance to the allocated weekly lab session is mandatory
and a roll will be taken at the beginning of each lab.
There are absolutely no lab exemptions given for ELEC2141. All students, including
repeating ones, must complete the laboratory component for this course.
Students will work in pair, but be marked individually. Each student will be asked a few
questions. There will also be a mark for the group based on demonstrating the required lab
tasks.
There will be 5% bonus marks and 2% optional lab marks available for those students who
wish to attempt the additional lab task at the completion of all laboratory exercises. The
exercises may require a substantial amount of time to complete successfully and students
attempting it are expected to work independently as there will be minimal support provided
for this task. It should be stressed, however, that marking of bonus and optional labs is
subjected to the availability of demonstrators and other course staff members. Every
possible effort will be made to accommodate the marking.
4. Laboratory Exam:
There will be a laboratory exam in week 13 and it contributes 5% toward the overall mark.
The exam will assess students’ technical understanding of using design software tool that
has been used throughout the labs in simulating, verifying, and implementing their digital
circuit on the FPGA board. They will be given simple design problem, asked to implement
and verify the design on the FPGA board.
5. Final examination:
The final examination will be a 3-hour, closed-book exam dealing with material from the
lectures and the supporting laboratory program. It is worth 60% of the overall mark. The
questions will be in a similar style to the tutorial exercises.
Note: For all class assessment tasks, if the student is unable to attend for medical or other
serious reasons (e.g. death in the family) the student must present medical certificates
and/or other relevant documentations within 3 days of the assessment to the course
convener. If this is not done within the required time period, then no consideration will
be given.
OTHER MATTERS
Academic honesty and plagiarism:
What is Plagiarism?
Plagiarism is the presentation of the thoughts or work of another as one’s own.* Examples
include:
direct duplication of the thoughts or work of another, including by copying material, ideas
or concepts from a book, article, report or other written document (whether published or
unpublished), composition, artwork, design, drawing, circuitry, computer program or
software, web site, Internet, other electronic resource, or another person’s assignment
without appropriate acknowledgement;
paraphrasing another person’s work with very minor changes keeping the meaning, form
and/or progression of ideas of the original;
piecing together sections of the work of others into a new whole;
presenting an assessment item as independent work when it has been produced in whole or
part in collusion with other people, for example, another student or a tutor; and
claiming credit for a proportion a work contributed to a group assessment item that is
greater than that actually contributed.†
For the purposes of this policy, submitting an assessment item that has already been submitted
for academic credit elsewhere may be considered plagiarism.
Knowingly permitting your work to be copied by another student may also be considered to be
plagiarism.
Note that an assessment item produced in oral, not written, form, or involving live presentation,
may similarly contain plagiarised material.
The inclusion of the thoughts or work of another with attribution appropriate to the academic
discipline does not amount to plagiarism.
The Learning Centre website is main repository for resources for staff and students on
plagiarism and academic honesty. These resources can be located via:
www.lc.unsw.edu.au/plagiarism
The Learning Centre also provides substantial educational written materials, workshops, and
tutorials to aid students, for example, in:
correct referencing practices;
paraphrasing, summarising, essay writing, and time management;
appropriate use of, and attribution for, a range of materials including text, images, formulae
and concepts.
Individual assistance is available on request from The Learning Centre.
Students are also reminded that careful time management is an important part of study and one
of the identified causes of plagiarism is poor time management. Students should allow
sufficient time for research, drafting, and the proper referencing of sources in preparing all
assessment items.
* Based on that proposed to the University of Newcastle by the St James Ethics Centre. Used
with kind permission from the University of Newcastle
† Adapted with kind permission from the University of Melbourne.
Contact Information:
All queries or concerns about ELEC2141 should be directed to [email protected]. Please
ensure that the subject line of any e-mail sent is informative and includes the word
‘ELEC2141’.
Continual Course improvement: This course is continually under review and constructive student feedback is always valued.
Students are encouraged to forward any positive or negative feedback on the course to the
course lecturer or academic-in-charge. Periodically student evaluative feedback on the course is
gathered, using among other means, UNSW's Course and Teaching Evaluation and
Improvement (CATEI) Process. Student feedback is taken seriously, and continual
improvements are made to the course based in part on such feedback.
Administrative Matters:
It is important that students familiarise themselves with all the School of Electrical Engineering
and Telecommunications policy and procedures. These are available at:
http://scoff.ee.unsw.edu.au/information/information.htm
The major information headings are listed below.
Information for Current Students
USE OF EE&T FACILITIES
Laboratory Regulations and Safety
Evacuation Procedures
OHS
First Aid
ACADEMIC ISSUES
The Learning experience
Submission of Written Work
Resubmission
Late Submission
Plagiarism and Academic Honesty
UNSW Examination Rules
Special Consideration, Illness and Misadventure
EE&T Supplementary Assessment Policy
Supplementary Examinations
Attendance
Conduct
Academic Standing
Grading
Grievance Procedures
Equity and diversity: those students who have a disability that requires some adjustment in
their teaching or learning environment are encouraged to discuss their study needs with the
course convener prior to, or at the commencement of, their course, or with the Equity Officer
(Disability) in the Equity and Diversity Unit (9385 4734 or
www.equity.unsw.edu.au/disabil.html). Issues to be discussed may include access to materials,
signers or note-takers, the provision of services and additional exam and assessment
arrangements. Early notification is essential to enable any necessary adjustments to be made.
Information on designing courses and course outlines that take into account the needs of
students with disabilities can be found at:
www.secretariat.unsw.edu.au/acboardcom/minutes/coe/disabilityguidelines.pdf
