CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design...
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Transcript of CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design...
![Page 1: CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19.](https://reader035.fdocuments.in/reader035/viewer/2022070413/5697bfdb1a28abf838cb0992/html5/thumbnails/1.jpg)
CEC 220 Digital Circuit DesignIntroduction to VHDL
Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19
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Lecture Outline
Wed, February 25 CEC 220 Digital Circuit Design
• Introduction to VHDL VHDL - (VHSIC) Hardware Description Language
o VHSIC - Very High Speed Integrated Circuit
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Introduction to VHDL
Wed, February 25 CEC 220 Digital Circuit Design
• Large digital systems are unwieldy to design manually E.g., design a h.264 video transcoder
• Hardware Description Languages (HDL) allow for design automation Design Simulation Synthesis Verification
RTL: Register Transfer Level
ESL: Electronic Sys Level
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Introduction to VHDL
Wed, February 25 CEC 220 Digital Circuit Design
• History of VHDL In December 1987, VHDL became IEEE Standard 1076-198 In September 1993, VHDL was restandardized to clarify and
enhance the language (IEEE Standard 1076-1993) In February 2008 VHDL 2008 (i.e., VHDL 4.0) was approved
and IEEE 1076-2008 was published in January 2009.
• VHDL is an international standard specification language for describing digital hardware used by industry worldwide
• VHDL enables hardware modelling from gates to system-level
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Introduction to VHDL
Wed, February 25 CEC 220 Digital Circuit Design
• VHDL can describe a digital system at The Behavioral level, The Structural level, or The Data-Flow level.
• Example of a full adder: Behavioral level:
o A functional description:C <= A + B;
» A, B, and C may be integers and ‘+’ an arithmetic operator– No implementation details– A high-level description
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Introduction to VHDL
Wed, February 25 CEC 220 Digital Circuit Design
Structural level:o Schematic with gates:
Data-Flow level :o Logic equations:
– Sum <= A xor … ;– Cout <= (A and B) or … ;
• VHDL leads naturally to a top-down design methodology
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Basic example:
E <= D or (A and B);
Signal_Name <= Expression;
Behavioral Description
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Basic example
Assignment operator
Concurrent statements
Evaluated anytime variables changes
If a delay time is not specified then the default is used
Dataflow Description
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• A Second Example:
CLK <= not CLK after 10 ns;
A concurrent statement
nsec
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Consequences of a concurrent statement
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• VHDL Syntax: Signal names and other VHDL identifiers may contain
letters, numbers, and the underscore character (_). An identifier must start with a letter, and it cannot end with
an underscore. VHDL is mostly case insensitive. Thus, C123 and ab_23 are legal identifiers, but 1ABC and
ABC_ are not. Every VHDL statement must be terminated with a
semicolon. White space is ignored. In VHDL double dash (--) precedes a comment. Words such as and, or, and after are reserved words with
special meanings.
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• VHDL Operators: Binary Logical Operators: and, or, nand, nor, xor, xnor Relational Operators: =, /=, <, <=, >, >= Shift Operators: sll, srl, sla, sra, rol, ror Arithmetic Operators: +, -, &, *, /, mod, rem
concatenation
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Introduction to VHDLPrecedence of VHDL Operators
Wed, February 25 CEC 220 Digital Circuit Design
• Highest precedence first, then left to right within same precedence group, Use parenthesis to control order. Unary operators take an operand on the right.
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Introduction to VHDLPrecedence of VHDL Operators
Wed, February 25 CEC 220 Digital Circuit Design Slide 14 of 19
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Vector Operations
Vector Notation:
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• VHDL Models for Multiplexers
sel <= A & B; -- select signalwith sel select F <= I0 when “00”, I1 when “01”, I2 when “10”, I3 when “11”;
F <= I0 when (A = ‘0’) else I1;
Conditional assignment Selective assignmentSlide 16 of 19
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Examples: Implement the following VHDL conditional statement using
two 2:1 MUXs: o F <= A when D=‘1’ else (B when E = ‘1’ else C);
Given that A <= “01101” and B <= “11100”, what is the value of:o F<= (not B & ‘1’ or A & ‘1’) and ‘1’ & A;
(000111 or 011011) and 101101 (011111) and 101101
001101Slide 17 of 19
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Introduction to VHDLVHDL Description of Combinational Logic Circuits
Wed, February 25 CEC 220 Digital Circuit Design
• Examples: Draw the circuit represented by the
following VHDL statements: o F <= not A and not B and I0;
G <=not A and B and I1;
Write the VHDL statements for 2-input NAND gates with 4-ns delays to implement a function
F <= X nand Y after 4 ns;
X <= A nand B after 4 ns;Y <= C nand D after 4 ns;
0
A
B
I
F
1
A
B
I
G
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Next Lecture
Wed, February 25 CEC 220 Digital Circuit Design
• More VHDL Entity, architecture, modules, arrays, …
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