CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit...
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Transcript of CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit...
CEC 220 Digital Circuit DesignLatches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design Slide 1 of 19
Lecture Outline
Monday, March 03 CEC 220 Digital Circuit Design
• Latches • Flip-Flops
Slide 2 of 19
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• Up until this point – Combinational Logic No memory
• Now we will consider – Sequential circuits Circuits with memory Typically, this is accomplished via feedback!!
Slide 3 of 19
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• A simple feedback circuit (inverter with a delay)
Slide 4 of 19
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• An Inverter with Stable Feedback Assume 10 ns gate delays
Time = 0 ns
0 ? ?1
Time = 10 ns
0
Time = 20 ns
Circuit retains the values Has memory
Slide 5 of 19
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• An Inverter with Stable Feedback Assume 10 ns gate delays
Time = 0 ns
1 ? ?0
Time = 10 ns
1
Time = 20 ns
Circuit retains the values Has memory
Slide 6 of 19
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• Consider the NOR-NOR circuit Assume 10 ns gate delays
A B0 0 10 1 01 0 01 1 0
0
0
S R
Q
1
0
0
Slide 7 of 19
Latches and Flip-FlopsThe S-R Latch
Monday, March 03 CEC 220 Digital Circuit Design
S R
Q
=
A B
0 0 1
0 1 0
1 0 0
1 1 0
0 500 1000
R
S
Q
Q’
0
10
0
Res
et
Set
Hol
d
Hol
d
Set
For
bidd
en
Slide 8 of 19
Latches and Flip-FlopsThe S-R Latch
Monday, March 03 CEC 220 Digital Circuit Design
• Behavior of the S-R Latch:
S-RLatch
R
S
𝑄
𝑄
S R Q0 0 Hold0 1 Reset1 0 Set1 1 Not
Allowed
Slide 9 of 19
Latches and Flip-FlopsThe S-R Latch
Monday, March 03 CEC 220 Digital Circuit Design
• The “Next-State” or “State Transition” Chart
S(t) R(t) Q(t) Q(t+t)0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
QUESTION:
What is the “state” of the latch?
ANSWER:
The “state” of the latch refers to the value of the output.
The current output depends on past output – the circuit has memory!!
010011XX
Hold
Reset
Set
NotAllowed
Inputs State Next State
Slide 10 of 19
Latches and Flip-FlopsThe S-R Latch
Monday, March 03 CEC 220 Digital Circuit Design
• What is the logic expression for the “Next State” ? Use a K-map!! S(t) R(t) Q(t) Q(t+t)
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
010011XX
S(t) R(t)Q(t) 0 1
00 0 1
01 1 1
11 0 X
10 0 X
Q(t+t)
Q S RQ
Slide 11 of 19
Latches and Flip-FlopsThe S-R Latch
Monday, March 03 CEC 220 Digital Circuit Design
• An application of the S-R Latch Debouncing a mechanical switch
Slide 12 of 19
Latches and Flip-FlopsThe Gated Latch
Monday, March 03 CEC 220 Digital Circuit Design
• The Gated D-Latch Solve the S=1 & R=1 not allowed issue!! Now we have a D-Latch
S-R Latch
S
R
𝑄
𝑄
S=1 & R=1 can NOT occur!!
D1
10
0
01The D-Latch:
Q simply follows D
Slide 13 of 19
Latches and Flip-FlopsThe Gated Latch
Monday, March 03 CEC 220 Digital Circuit Design
• The Gated D-Latch Now “Gate” the inputs
S-R Latch
S
R
𝑄
𝑄
D
G
S = 0 & R = 0(hold)
Slide 14 of 19
Latches and Flip-FlopsVHDL Code for Gated D-Latch
Monday, March 03 CEC 220 Digital Circuit Design
entity GDL is port( D, G : in bit; -- D is the Data input & G is the gate input Q, QN: out bit); -- Q and QNot are the outputsend GDL;
architecture GDL_eqns of GDL issignal S,R, Qinternal: bit;begin S <= D and G after 5 ns; R <= not D and G after 5 ns; Qinternal <= '1' when S = '1' and R = '0' else '0' when S = '0' and R = '1'; -- S&R = “11” is not allowed -- S&R = “00” is the hold state Q <= Qinternal after 10 ns; QN <= not Qinternal;End GDL_eqns;
S-R Latch
S
R
D
G
Run The
Simulation
Slide 15 of 19
Latches and Flip-FlopsFlip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• Edge-Triggered devices The D Flip-Flop
DQ Q+ 0 0 0 0 1 0 1 0 1 1 1 1
Q D Slide 16 of 19
Latches and Flip-FlopsTiming Diagram
Monday, March 03 CEC 220 Digital Circuit Design
D
Clk
Qrise
Qfall
100
QGated
latch
Rising edgetriggered D FF
Falling edgetriggered D FF
50
Gated D Latch
Slide 17 of 19
• Assume that all Q’s starts at ‘0’
G=
Latches and Flip-Flops
Monday, March 03 CEC 220 Digital Circuit Design
• Setup and Hold Time
Input
Clock
T su T h
Setup Time (Tsu)
Clock: Periodic Event, causes state of memory element to change
rising edge, falling edge, high level, low level
There is a timing "window" around the
clocking event during which the input
must remain stable
Minimum time before the clocking event by which the input must be stable
Hold Time (Th)Minimum time after the clocking event during which the input must remain stable
Slide 18 of 19
Next Lecture
Monday, March 03 CEC 220 Digital Circuit Design
• D Flip-Flop review• VHDL code for a D Flip-Flop• S-R, J-K, T Flip-Flops• Registers
Slide 19 of 19