EECS 473Advanced Embedded Systems

Lecture 9:

Groups introduce their projects

Power integrity issues

Final proposal due today

• Final proposal

– I should have signed group agreement now.

• I should have feedback by Tuesday night to all groups.

– Expect sooner actually.

Where we are;where we are going

• Labs 1-3 done, lab 4 due this week.• PCB lab

– Much less conceptual—it’s about learning a tool

• Entering full-time project mode.– Have midterm and 2 homework assignments before project due.

• Everything else is project (and lecture).• HW1 posted by the end of the day Friday. Due 10/16 (13 days from

now)– I expect it will take ~4 hours– It’s a nice prep for the midterm.

» Also practice midterms are posted.

– You should be putting in ~15 hours/week into the project.• The more you put in now, the less you have later.

– And some things (reorders, PCB redos) just take time—can’t cram.

• You really (really) want time to debug!• Large part of project grade based upon fully working.

– More complex projects get a bit more slack, but…– Project due a week before classes end (design expo)

Today: Restart on electrical issues

• Talked about PCBs last time.– Talked about sizing traces– Started on power integrity (keeping power/ground at the

desired voltage differential)

• Will talk about power integrity in a lot more detail today.

• But first, pitches:• Today: GROUP 1: Balloon, Hiking, Fish, Ear, Fence, Drone, Cane • Tuesday: GROUP 2: Mesh, Bag, Body, Microphone, IoT, Shoes,

Printer

0.001

0.010

0.100

1.000

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Imp

ed

an

ce

Frequency

Pureinductor

Cap/resistor

Pure cap.

A look at impedance(with capacitors, inductors and resistors vs. frequency)

Notice the log scales!

EECS 215/Physics 240 “review”

Power Integrity

• In order to get digital electronics to work correctly, they need a minimum* voltage differential. – If we get below that, the devices might

• Be slow (and thus not meet setup times)

• Lose state

• Reset or halt

• Just plain not work.

• Even a very (very) short “power droop” can cause the chip to die.– In my experience, this is a really common problem.

• Keeping power/ground constant and noise/droop free is “Power Integrity”

Power Integrity

*and maximum. Don’t forget this is really a range though we usually talk about the minimum

So?

• We need the Vcc/Ground differential to be fairly constant.– But rapid changes in the

amount of current needed will cause the voltage to spike or droop due to inductance.

• We basically want a “no-pass” filter.– That is we don’t want to

see any signal on the Vcc/Ground lines.

– The obvious thing?• “Add a capacitor”

– That should keep the voltage constant, right?

• The problem is we need to worry about a lot of frequencies AND capacitors aren’t ideal.

Power Integrity

Lots of frequencies

• Even fairly slow devices these days are capableof switching at very high frequencies.

– Basically we get drivers that have rise and fall times capable of going 1GHz or so.

• This means we generally have to worry about frequencies from DC all the way to 1GHz.

– Because our chip may be varying its draw at rates up to that fast.

Power Integrity

Non-ideal devices.

• ESR is Effective Series Resistance• ESL is Effective Series Inductance• Ceff is the effective capacitance.

– How does quantity effect these values?

• Obviously impendence will be varying by frequency.

Power Integrity

Other things can add to ESR/ESL

• Generally a bad solder job can make ESR/ESL worse.

• Packaging has an impact

– wires have inductance so surface-mount packages preferred

• Pads can have an impact

Power Integrity

Power Distribution Network

• Talked a lot about keeping the power supply voltage constant.– Should think of situation as follows:

– If the processor drops 3.3V and uses 100mA, what is it’s effective resistance?

– If the power supply is 3.3V, the processor uses 100mA and the total resistance of the PDN (Power distribution network) is .01Ω, what voltage does the processor really see?

InputPDN

Processor OutputPDN

Power Integrity

Consider an FPGA with the following characteristics

• Acceptable voltage range is from 2.65 to 2.75V

– Max current is 5A.

– What is the largest impedance we can see on the PDN and still have this work?

Given the previous table..

0.001

0.010

0.100

1.000

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Imp

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ce

Frequency

Decoupling Impedance vs Frequency

Z(pup)

Z(tant)

Z(1uF)

Z(0.1uF)

Z(0.01uF)

Z(pcb)

ZT

Z(LICA)

Power Integrity

Removing the PCB…

0.001

0.010

0.100

1.000

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Imp

ed

an

ce

Frequency

Decoupling Impedance vs Frequency

Z(pup)

Z(tant)

Z(1uF)

Z(0.1uF)

Z(0.01uF)

Z(pcb)

ZT

Z(LICA)

Power Integrity

But wait…

• VRM

– Voltage regulator module

• bulk bypass (tantalum) and decoupling capacitors (ceramic).

– These capacitors supply instantaneous current (at different frequencies) to the drivers until the VRM can respond.

• However sets of different capacitors cause problems!

http://www.pcbdesign007.com/pages/columns.cgi?artcatid=0&clmid=65&artid=85396&pg=3&_pf_=1

Power Integrity

Other power integrity issues

• Of course, one source of power integrity problems is coming from the processor

– Power supply just can’t keep up with processor varying (what we just did)

• But there are other problems.

– And these are issues introduced by the PCB designer.

• Don’t be that guy/gal.

Power Integrity

Connecting ground poorly

• One big issue is that people think of ground as, well, ground.– It isn’t.

– Only one point is “0V”. • Everything else has a higher voltage.

– Wires aren’t perfect.

• It’s really easy to make this mistake.– Classes like EECS 215 basically encourage it.

– Better to think of things as “return path” not ground.• And yes, you can make the same mistake with power, but people

do that a lot less often.– Partly because we often have different “Vcc” levels on the board.

– But mostly because we just think of power and ground differently.

Power Integrity

Consider the following

• Consider the figure on the right.– Why is the top picture “wrong”?

• Let’s consider the case of “A” being DC motor that runs at 120 Watts (12V 10A).

• B is processor drawing 100mA– Wire from A to PSU return is

15cm long, 400mils wide.

– What is the voltage at the “ground”?

0.1A

0.02Ω

10A

3.3V 12V

Top figure from “The Circuit Designer’s Companion”. If you are going to do PCB design much, buy and read this book.

Power Integrity

Review: Power integrity (1/2)

• Processors and other ICs have varying current demands– Sometimes at frequencies

much greater than the device itself runs at• Why?

– So the power/ground inputs need to be able to deal with that.• Basically we want those wires

to be ideal and just supply how ever much or little current we need.

– If the current can’t be supplied correctly, we’ll get voltage droops.

• How much power noise can we accept?– Depends on the part (read

the spec). • If it can run from 3.5V to 5.5V

we just need to insure it stays in that range.

– So we need to make sure that given the current, we don’t end up out of the voltage range.

• Basically need to insure that we don’t drop too much voltage over the wires that are supplying the power!

Power Integrity

Review: Power integrity (2/2)

* http://www.n4iqt.com/BillRiley/multi/esr-and-bypass-caps.pdf provides a very nice overview of the topic and how to address it.

• So we need the impedance of the wires to be low.– Because the ICs operate at a wide

variety of frequencies, we need to consider all of them.

– The wires themselves have a lot of inductance, so a lot of impedance at high frequencies.

• Need to counter this by adding capacitors.

• Problem is that the caps have parasitic inductance and resistance.– So they don’t help as well as you’d like– But more in parallel is good.– Each cap will help with different

frequency ranges.

• We also can get a small but low-parasitic cap out of the power/ground plane.

• Finally we should consider anti-resonance*.

Power Integrity

Power Integrity (PI) summary

• Power integrity is about keeping the Vcc/ground difference constant and at the value you want.

• Covered two issues:– Many devices that sink power do so in “pulses”

• Due to internal clocks and time-varying behavior• Need caps to keep value constant

– But parasitic ESR/ESL cause problems– So lots of them==good

» Reduce ESR/ESL» Increase capacitance.

• Anti-resonance can cause problems!– Need Spice or other tools to model.

» Will do a bit of this next time

– Also, need to watch return paths• Can easily bump up your ground level

– Cuts into your margin for the work above…

Power Integrity

Additional “reading”

• http://www.murata.com/en-us/products/emiconfun/capacitor/2013/02/14/en-20130214-p1

– Very nice coverage of ESR and impedance in a non-idea capacitor. Touches on the fact that ESR varies by frequency! Very readable and short!

• http://ksim.kemet.com/

– Nice spice models of real capacitors.

•http://doc.utwente.nl/64874/1/tiggelman.pdf

– A much more academic treatment of ESR.

• https://www.youtube.com/watch?v=sW0a9d_vWoc

– Mildly amusing and useful (who doesn’t like magic smoke?)

Up next

• Next week:– Batteries

– Linear Regulators

• Week after:– Fall break (HW due Wednesday after)

– Exam review

• Week after that– Milestone meetings

– Introduction to special purpose processors (mostly DSPs)