Lecture #2 1

EE251: Introduction to Microprocessors

• Thursday, August 29• Review: Flip-Flops and Sequential Circuits• Components of a Microcontroller• ARM Cortex M4 Register Model

• Read: Chapter 3 (3.3 is C and not required)• Labs: Started this week! Lab 1 due next week.

– Note, Lab 2 starts next week and will be due two weeks later (week of Sept. 10). Prework is due at beginning of your Lab 2, so get started on it!

• Homework: #1 Due Sept. 13, 4 p.m. Check web page.

Lecture #2 2

Important Resources for ECE251 Embedded Systems: Introduction to ARM Cortex-M

Microcontrollers, Jonathan Valvano, On reserve in Morgan

Embedded Systems: Real Time Interfacing to ARM Cortex-M Microcontrollers, Jonathan Valvano. On reserve in Morgan

The Definitive Guide to Arm Cortex-M3 and Cortex-M4 Processors, Joseph Yiu. See instructor.

ARM Microprocessor Systems, Tahir and Javed. See instructor.

Tiva TM4C123GH6PM Microcontroller Data Sheet (1409 pages)

Various other Reference Manuals, User Guides, and web page references that are often helpful: found on ECE251 main website.

Check the ECE251 website regularly to find more helpful resources for the course.

Lecture #1 3

Flip-FlopsA key memory device in microprocessors is the flip-flop.Remember: Flip-flops are __________. Latches are __________. Computers use __________ circuits => flip-flops.

For example, a J-K flip-flop is shown as:

When do the outputs of the flip-flop above change? __________________ How can you tell?

In microprocessors, flip-flops are typically grouped together with common control signals into registers.

K

Clk

J

Q’Q

Lecture #1 4

MemoryAnother common subsystem in microprocessors is MEMORY, with multiple address lines and multiple data lines:

The above has N address lines and M data lines. Thecapacity of this memory system is __________ bits.

Why the power of 2 for addresses, but not data?

a0

a1

aN-1

d0 d1 . . . dM-1

Read/Write′Clk

.

.

.

Lecture #1 5

Sequential Circuits

Sequential circuits are logic circuits with memory (state), including registers and/or memory cells

What kind of sequential circuit have I drawn? ______________________

Hint: What are the two types, and what is the difference between them?

In

Memory

Output

Sn+1SnNext StateLogic

OutputLogic

Clk

Lecture #1 6

Sequential Circuits continued

Another type of sequential circuit:

What kind of sequential circuit is this? ______________________Hint: Outputs do NOT depend on inputs.This is almost universally the kind of sequential circuits used in real computer systems. Why?

In

Memory

Output

Sn+1Sn

Next StateLogic

Clk

OutputLogic

Lecture #2 7

State Transition Diagrams

StateOutput

Input Next StateOutput

Moore

State

InputOutput Next State

Mealy

End of Review of ECE102.

Lecture #2 8

Possible TA Office HoursEmily: 1. Monday – 12:30-1:30 pm2. Tuesday – 3:30-4:30 pm3. Tuesday – 9:00-10:00 am4. Thursday – 3:30-4:30 pm

Li:1. Wednesday – 12:00-1:00 pm2. Thursday – 2:00-3:00 pm3. Thursday – 11:00-12:00 am

Jim:1. Wednesday – 4:00-5:00 pm2. Thursday – 9:30-10:30 am3. Thursday – 10:30-11:30 am

Lecture #2 9

New Content: Computer Block Diagrams

Instructions and data are stored in the same memory.

Von-Neumann Harvard – e.g. ARMInstructions and data are stored in separate memories.

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Features of the ARM Cortex M4 Microcontroller(Specifically the TM4C123GH6PM that we’ll be using)

- 32-bit CPU (32 bit wide registers and address path)- 80 MHz max internal clock- 4 GBytes memory space (232 = 22•230 = 4•230 = 4G where G = 230 = 1,073,741,824)- 32 KBytes of on-chip RAM (where K = 210 = 1,024)

- 2 KBytes of flash EEPROM memory- 256 KBytes of Flash memory- SysTick Real-Time Clock- Sophisticated timer functions that include: input capture, pulse output, …- Serial communication interfaces: SCI, SPI, CAN, …- 2 12-bit A/D converters with max sample rate of 1 million samples per second- and lots, lots more…

Don’t panic! This is just an overview. We havea whole semester to understand a subset of its functionality.

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TM4C123GH6MP Microcontroller Block Diagram

So, where is the CPU?

Lecture #2 12

TM4C123GH6MP Microcontroller Block Diagram

CPU

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Embedded System

- A product that uses one or more microcontrollers as controller(s). Also called an embedded product.

- End users are interested in the functionality of the product, not the microcontroller itself.

- Cell phones, home security systems, and modern automobiles are examples of embedded products. Others you know of?

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Samsung Gear Fit Fitness Tracker

STMicroelectronics STM32F439ZI 180 MHz, 32 bit ARM Cortex-M4 CPU

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The A6 processor is the first Apple System-on-Chip (SoC) to use a custom design, based off the ARMv7instruction set. It is a predecessor to the ARM Cortex-M4 we’ll be using.

This is an iPhone 4. What processor does the iPhone 8 use? Iphone X?

iPhone 4 Teardown

Lecture #2 16

Semiconductor Memory - Random access memory (RAM): same amount of time is

required to access any location on the same chip. Read/write.- Read-only memory (ROM): can only be read; cannot be

written to directly by the processor

Random Access Memory- Dynamic Random Access Memory (DRAM): periodic

refresh is required to maintain the contents of a DRAM chip- Static Random Access Memory (SRAM): no periodic

refresh is required. Always more predictable and usuallyfaster than DRAM.

- So what the heck is an SDRAM, used nowadays?

Read-Only Memory- Mask-programmed read-only memory (MROM):

programmed when being manufactured- Programmable read-only memory (PROM): the memory

chip can be programmed by the end user

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Erasable Programmable ROM (EPROM)1. Electrically programmable many times2. Erased by ultraviolet light (through a window)3. Erasable in bulk (whole chip in one erasure operation)

Electrically Erasable Programmable ROM (EEPROM)1. Electrically programmable many times2. Electrically erasable many times3. Can be erased one location, one row, or whole chip in one operation

Flash Memory1. Electrically programmable many times2. Electrically erasable many times3. Can only be erased in bulk

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Computer Software- Computer programs (programs) are known as software- A program is a sequence of machine instructions

Machine Instruction- A sequence of binary digits that can be executed by the processor- Hard to understand, program, and debug for human being- E.g. in the ARM Cortex M4, instruction 0010 0010 0110 0100 puts the

number 100 in register #2. How many bytes long is this instruction?- OK, the instruction is also 0x2264. Does that help much? What is 0x64

in base 10?So what might 0x22 be? That’s 0010 0010 or 00100 010. OK, 001002 is “move

data into a register” and 0102 is register #2.

Assembly Language- Defined by machine instructions- An assembly instruction is a mnemonic representation of a machine

instruction, e.g. ADD represents a register add (0001100…)- Assembly programs must be translated to binary before it can be executed:

Assembler does this translation:ADD R2 R1 R0 → 0001100 010 001 000 = 0x1888

- In this course we’ll be dealing with Assembly Language almost exclusively.

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High-level Language- Syntax of a high-level language is similar to English- A translator is required to translate the program written in a

high-level language -- done by a compiler- High-level languages allow the user to work on the program logic

at a more conceptual level (e.g. you don’t have to worry aboutwhat’s in register R2).

- Our textbook uses some C language examples, which are helpful ifyou understand C, but is not necessary to this course.

Source Code- A program written in assembly or high-level language

Object Code- The output of an assembler or compiler--machine instructions

and data in binary (ones and zeroes) form.

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So Why Use Assembly Language in 251? Writing software in a higher level language is more “efficient”

Employers want new engineers who are good with higher level language coding

BUT AT THE SAME TIME The goal of ECE251 is understanding how processors work,

not writing large programs to do complex tasks.

Assembly Language is a readable version of the instructions the processor understands.

Programming things like register bit manipulation is arguably more straightforward in assembly language than in a high level language (but we aren’t going to argue about it!).

Employers also usually prefer engineers who understand well the inner workings of the computers they are using.

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ARM Cortex-M4 Registers

This is important!Learn it!

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Memory Addressing- Memory consists of a sequence of directly addressable locations.

- A location is referred to as an information unit.

- A memory location can be used to store data and instructions.

- A memory location has two components: an address and its contents.

We will represent number bases with these prefixesBase

binary

decimal

hexadecimalor hex

Prefix Example

2_

$

2_10001010

12345678

0x5678

ContentsAddress

The components of a memory location

0x

Lecture #2 23

Data transfers between the CPU and the memory are done over the common buses: address bus and data bus.

Notations: [addr] represents the contents of a memory location,[register name] refers to the contents of the specified register.

E.g. [0x20] refers to the contents of memory location at address 0x20, i.e. at address 32.

E.g. [R1] refers to the contents of register R1; similarly with other registers.

Value → Address means that the data value “Value” is stored at memory or register address “Address”. E.g. 0x20 → R1 means that the value 0x20 is placed in register R1. What does 0xAB → 0x2000 mean?

Transferring Data between CPU and Memory

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Operation of a Computer (see Section 1.4 in text)

Computers execute programs instruction-by-instruction. Let’s look at the execution of instructions in detail:

0. Program counter register PC “points to” (i.e. contains the address of) the memory location containing the next instruction to be executed. This counter will be updated to “point to” the following instruction after execution of the current instruction.

1. Instruction Fetch: Using the current value of PC, read the next instruction to execute from memory. Store this data in the instruction register, IR. That is: [[PC]] → IRPC is the name of the register; [PC] is the address of the instruction to be executed;[[PC]] is the instruction itself, contained at the memory address [PC]. Note that IR is an internal register, not accessible with computer instructions.

2. Decode Instruction: Determine which instruction is to be executed using the contents of the IR.

3. Execute Instruction: Activate appropriate control lines in processor sequentially to perform the action specified by the Instruction at particular clock ticks. This is a classic Moore machine operation.

Let’s go over a simple example on the next slide.

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Instruction Execution ExampleLet’s execute the instruction ADD R4,R3,R0 and assume this instruction begins at address 0x1000. This instruction means: add contents of register R0 to the contents of register R3, and store the results into register R4. Here’s what happens:1. Fetch instruction (read) from memory addresses 0x1000 and 0x1001. The contents

of these are the computer’s bit pattern for ‘ADD R4,R3,R0’. Store these 16 bits in instruction register, IR.

2. Decode the instruction in IR. Determine that it is the ADD instruction.

3. Connect register R0 to input 1 of the ALU.

4. Connect register R3 to input 2 of the ALU.

5. Set controls to ALU to do a 32-bit add operation.

6. Store the output of the ALU into register R4 (i.e. connect R4 to output of ALU).

7. Increment the program counter and store that value back in the program counter: [PC] + 2 → PC. Why 2? Now [PC] = 0x1002, This operation can (does) actually occur after step 1, in parallel with steps 2-6. Why?

8. Go back to step 1, using the new value of PC. This can occur during steps 3-6. Why?

See a more complete example in Sections 1.4.2-1.4.3 in text.Understand this example!

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Questions? Next Lecture: Moving Data From Memory (load)

and To Memory (store) with ARM These are basic concepts we’ll use throughout

the semester. Understand them!

Read Chapter 5 in text (Load and Store) Lab 2 is next week. If you’re in a Monday lab,

attend a Tuesday or Wednesday lab.

Do lab prework beforehand. It is due at beginning of lab 2.