No lab next week
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EE141 1 EE141 EECS141 1 Lecture #7 EE141 EECS141 2 Lecture #7 No lab next week Midterm on Fr Febr 19 6:30-8pm in 2060 Valley LSB Review Session: TBA (most likely on Th)
Transcript of No lab next week
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EE141 EECS141 1 Lecture #7
EE141 EECS141 2 Lecture #7
No lab next week Midterm on Fr Febr 19 6:30-8pm in 2060 Valley
LSB Review Session: TBA (most likely on Th)
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EE141 EECS141 3 Lecture #7
Last lecture Optimizing complex logic
Today’s lecture Applying what we learned on memory
decoders Reading (Ch 6.2, 12.1,12.3)
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Measure everything in units of tinv (divide by tinv):
p – intrinsic delay (kγg) - gate parameter ≠ f(W) LE – logical effort (k) – gate parameter ≠ f(W) f – electrical effort (effective fanout)
Normalize everything to an inverter: LEinv =1, pinv = γ
tpgate = tinv (pγ + LE×f)
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EE141 EECS141 5 Lecture #7
Compute the path effort: PE = (ΠLE)BF Find the best number of stages N ~ log4PE Compute the effective fanout/stage EF = PE1/N
Sketch the path with this number of stages Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
EE141 EECS141 6 Lecture #7
LE=10/3 1 ΠLE = 10/3 P = 8 + 1
LE=2 5/3 ΠLE = 10/3 P = 4 + 2
LE=4/3 5/3 4/3 1 ΠLE = 80/27 P = 2 + 2 + 2 + 1
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EE141 EECS141 7 Lecture #7
Branching effort:
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5 15
15
90
90
LE = FO = PE = SE1 = SE2 = PE =
1 90/5 = 18 18 (wrong!) (15+15)/5 = 6 90/15 = 6 36, not 18!
Introduce new kind of effort to account for branching:
• Branching Effort:
• Path Branching Effort:
Con-path + Coff-path
Con-path b =
Π bi B = Now we can compute the path effort: • Path Effort: PE = ∏LE·FO·B
Branching Example 1
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EE141 EECS141 9 Lecture #7
Select gate sizes y and z to minimize delay from A to B
Logical Effort: LE =
Electrical Effort: FO =
Branching Effort: B =
Path Effort: PE =
Best Stage Effort: SE =
Delay: D =
(4/3)3
Cout/Cin = 9
2•3 = 6
∏LE·FO·B= 128
PE1/3 ≈ 5
3•5 + 3•2 = 21
Work backward for sizes:
5 z = 9C•(4/3) = 2.4C
5 y = 3z•(4/3) = 1.9C
Branching Example 2
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Compute the path effort: PE = (ΠLE)BF Find the best number of stages N ~ log4PE Compute the effective fanout/stage EF = PE1/N
Sketch the path with this number of stages Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
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EE141 EECS141 11 Lecture #7
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Physical Schematic
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All-inclusive model Capacitance-only
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Interconnect and its parasitics can affect all of the metrics we care about Cost, reliability, performance, power consumption
Parasitics associated with interconnect: Capacitance Resistance Inductance
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EE141 EECS141 15 Lecture #7
From Magen et al., “Interconnect Power Dissipation in a Microprocessor”
SLocal = STechnology
SGlobal = SDie
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Use Better Interconnect Materials e.g. copper, silicides
More Interconnect Layers reduce average wire-length
Selective Technology Scaling (More later)
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Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly
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• Analysis method: • Break the wire up into segments of length dx • Each segment has resistance (r dx) and capacitance (c dx)
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Model the wire with N equal-length segments:
For large values of N:
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