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EE241 - Spring 2006Advanced Digital Integrated Circuits

Lecture 22:Embedded Memory

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Some Info

Rest of the semester planWeek 14 (this week): memory

Week 15: Test and Arithmetic

Week 16: (1 lecture on May 8): Future perspectives

Project Presentations: Tuesday May 9 – Full afternoon

Take home final: May 12-15

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Semiconductor Memory Trends

From [Itoh01]

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Trends in Memory Cell Area

From [Itoh01]

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K. Itoh, Hitachi

Trends in RAM Developments (R&D)

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001

1980 1990 20001970

Mem

ory

Cap

acit

y/C

hip

(bi

ts)

16 G

256 K

1 G

64 M

4 M

16 K

1 K

ISSCC/VLSI CircuitsStand-alone RAMs

1832

72

DRAM

SRAM

19901970 1980 2000

Mem

ory

Cel

l Are

a (m

m2)

1

10,000

1,000

100

10

0.1

Full CMOS

Full CMOS

TFTload

Poly-Si load

Planar capacitor

3-D capacitor

ISSCC/VLSI CircuitsStand-alone RAMs

DRAM

SRAM

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Embedded Memory Background

Subsequent slides courtesy Randy McKee, TI

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Embedded Memory Alternatives

Courtesy Randy McKee, TI

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5

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Competitive Developments (late 2004)

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6

11(Zurcher, Motorola, 1995)

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7

13

14

8

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MRAM

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9

17

18

10

19

20

11

21

22

12

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Some stacked solutions (TI)

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SRAM

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90 nm SRAM cell sizes

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The art of making small cells

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15

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SRAM Yield Limitations

Read StabilityCell can flip due to increase in the “0” storage node above the trip voltage of the other inverter during a read.

Hold StabilityData retention current not able to compensate the leakage currents.

Access TimeTime required to produce a pre-specified ΔV between the bit lines is higher than the maximum tolerable limit.

Write Stability“1” Storage node may not be reduced below the trip point of the other inverter before WL is discharged.

Mukhopadhyay et al, 2004

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Read Stability

)(1)(2

)(2

)(1

LL

LL

LL

VFSVFS

cSVSVF

cVVF

−−=+−=−

+=

0)(2)(1 =

∂−∂−

∂∂

L

L

L

L

VSNMVF

VVF

Bhavnagarwala et al, 2001

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Hold Stability

Similar to Read Stability analysis without access transistor.

PR must provide enough leakage to compensate for leakage in NMOS pull-down and access transistors.

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Read Access

Mukhopadhyay et al, 2004

∫∫Δ−Δ−Δ−

==RVBLV

V RBL

RBLRBLVVV

V LBL

LBLLBLACCESS

DD

DD

MINRBLDD

DDI

dVCI

dVCT

,

,

,,

,

,,,

Must provide ΔV between the bit lines within maximum tolerable time limit.

Limited to floating bit-line implementation with voltage sensing amplifiers.

Sum BL currents and integrate.

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Write Stability

Mukhopadhyay et al, 2004

ility.for writab Need TRIPWRITE VV <

stability. for write )()(

)(

)()(WL

V

V RRoutRRin

RRRWRITE T

VIVIdVVC

TTRIP

DD

<−

= ∫

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35

36

19

37

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Some stacked solutions (TI)

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Flash Memory

Slides adapted from Ken Takeuchi, Toshiba

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Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n+ source n+ drainprogramming

Many other options …

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Basic Operations in a NOR Flash Memory―Erase

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Basic Operations in a NOR Flash Memory―Write

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Basic Operations in a NOR Flash Memory―Read

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History of Flash Memories

‘84 ‘85 ‘86 ‘87 ･･････‘91 ‘92 ‘93 … PRESENT

SanDisk-type

DiNOR-type

SanDisk-type

NOR-type

NAND-type

DiNOR-type

AND-type

SST-typeX

SST-type

X

File-Storage

Code-Storage

NOR-type

NAND-type

ACEE-type

AND-type

Split-gate-type

FLASH MEMORYInvention

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Flash Memory Comparison - Code vs File Storage -

Code Storage

File Storage

Applications Type of Flash memory Performance

Program storage for- Cellular Phone- DVD- Set TOP BoxBIOS for- PC and peripherals

Small form factor card for- Digital Still Camera- Silicon Audio- PDA ... etcMass storage as- Silicon Disk Drive

Important :

Acceptable :

• High speed random access• Byte programming

• Slow programming• Slow erasing

• High speed programming• High speed erasing• High speed serial read

• Slow random access

Important :

Acceptable :

NOR • Intel / Sharp• AMD / Fujitsu / Toshiba

DINOR • Mitsubishi

NAND • Toshiba / Samsung

AND • Hitachi

•SanDisk: NOR

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Requirements for File Storage Memory

Low Bit Cost <$.2/MByte

High Density >256MByte

High Speed Programming >6MByte/sec

and Erasing <3msec/block

High Speed Serial Read

Low Power Consumption

Good Program/Erase Endurance >1 million cycles

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Cell Array Comparison

Simplest wiringSmallest area

NOR SanDisk AND NAND

Erase gate(poly)

Unit Cell Unit Cell

Word line(poly) Word line(poly)

Source line(Diff. Layer)

Word line(poly)

Bit line(metal)

Source line(Diff. Layer)

Unit Cell

Contact

Source line(Diff. Layer)

Word line(poly)

Bit line /Source line(metal)

Unit Cell

Sub Bit line (Diff. Layer)

9F2 8F2 4F210F2

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Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

NAND Cell Array (Top view)

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NAND Cell Array (Cross sectional view)

Word line

Word line

Bit line

Select gate

A A’

A A’

Source line

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Cell Size Shrink by Self-Aligned STI

Current

２Ｆ

3Ｆ Floating Gate

Word Line

LOCOS_NAND : 6F2+αLOCOS_NAND : 6F2+α

２Ｆ

２Ｆ

STI_NAND : 4F2+αSTI_NAND : 4F2+α

３F２F

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NAND Cell Array (Cross sectional view)

Word line

Word line

STI

1st floating gate

2nd floating gate

B B’

B B’

Si

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+ Multi Level Cell

Floating Gate

LOCOS

Control Gate

3.5F

3F

2F

3F

NAND-type Cell(Contactless)

2F

2F

Self-AlignedSTI Cell

2F

2F

Self-Aligned STI Cell

Floating Gate

STI

Control Gate

Cell Size 10-11F2 6-7F2 4-5F2 2-2.5F2 Isolation LOCOS LOCOS SA-STI SA-STI

NOR-type Cell

NAND Cell Trend

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NAND Flash Cell Size Trend

Start of Mass Production

Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan-‘93 ‘94 ‘95 ‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02 ‘03 ‘04

0.1

10C

ell S

ize

( um

2 )

1

LOCOS SA-STI

MLC

0.01

Multi Level Cell

Floating Gate

LOCOSTunnel Oxide

Control GateWSiONO

Control Gate ONOFloating Gate

Tunnel Oxide STI

WSi

SA-STI

0.25um

0.175um

0.13um0.10um