1

EE241 - Spring 2006Advanced Digital Integrated Circuits

Lecture 23:Low Voltage Memory

2

2

3

Some stacked solutions (TI)

4

SRAM Yield Limitations

Read StabilityCell can flip due to increase in the “0” storage node above the trip voltage of the other inverter during a read.

Hold StabilityData retention current not able to compensate the leakage currents.

Access TimeTime required to produce a pre-specified ΔV between the bit lines is higher than the maximum tolerable limit.

Write Stability“1” Storage node may not be reduced below the trip point of the other inverter before WL is discharged.

Mukhopadhyay et al, 2004

3

5

Read Stability

)(1)(2

)(2

)(1

LL

LL

LL

VFSVFS

cSVSVF

cVVF

−−=+−=−

+=

0)(2)(1 =

∂−∂−

∂∂

L

L

L

L

VSNMVF

VVF

Bhavnagarwala et al, 2001

6

Hold Stability

Similar to Read Stability analysis without access transistor.

PR must provide enough leakage to compensate for leakage in NMOS pull-down and access transistors.

4

7

Read Access

Mukhopadhyay et al, 2004

∫∫Δ−Δ−Δ−

==RVBLV

V RBL

RBLRBLVVV

V LBL

LBLLBLACCESS

DD

DD

MINRBLDD

DDI

dVCI

dVCT

,

,

,,

,

,,,

Must provide ΔV between the bit lines within maximum tolerable time limit.

Limited to floating bit-line implementation with voltage sensing amplifiers.

Sum BL currents and integrate.

8

Write Stability

Mukhopadhyay et al, 2004

ility.for writab Need TRIPWRITE VV <

stability. for write )()(

)(

)()(WL

V

V RRoutRRin

RRRWRITE T

VIVIdVVC

TTRIP

DD

<−

= ∫

5

9

10

6

11

Low-Voltage Nano-Scale Embedded RAMsKiyoo Itoh, Hitachi Ltd.

1. Introduction2. General Trends in RAMs3. Challenges and Trends in LV RAMs

RAM Cells, Peripheral Circuits4. Future Prospects5. Conclusion

OUTLINE

7

K. Itoh, Hitachi Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003

Trends in Supply Voltage

Su

pply

Vol

tag

es V

CC, V

DD

(V)

2

5

10

20

1

VCC

VDD(int)DRAM

I/O

3.5 3 V3

WD

Peri. Cell

VCC (5 V)Chip

1970 1980 1990 2000

2

5

10

1SRAM

2.75 1.5 V2.1

Peri. Cell

VCC

VDD(int)

WD

VCC (2.5 V)

I/O

ISSCCVLSI Circuits

K. Itoh, Hitachi

Challenges to LV e-RAMs

1. RAM Cells•Maintain Signal Charge

–Small SER•Maintain Signal Voltage

& Reduce Noise–Stable & fast sensing–Wide voltage margin

•Reduce Cell Size–e-RAMs dominate SoCs

2. Peripheral Circuits •Reduce Leakage

–Small ISTB & IACT

•Reduce Speed Variation–Acceptable level

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001

e-RAM

RAM cellarray

DRAMSRAM

periph.

DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs

8

K. Itoh, Hitachi

Signal Charge QS of RAM CellsQS ≅ Soft-Error Qcrt . The larger the QS , the smaller the SER.

QS CSVDD/2 CSVDD , CS =(C1 + 2C2 )CS Intentionally added, large, C1, C2 ; parasitic, small,

needs to be gradually rapidly decrease with devicedecreased with device scaling (1/k).scaling to maintain a large SER is always larger than forsignal voltage. DRAM. For the same SER,

CS (SRAM) ≅ CS (DRAM)/2.

WLVDDDL

0Cs

"1"

"0"

DRAM SRAMVDD

DLC1

DL

C2WL

0VDD

K. Itoh, Hitachi

Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003E. Ibe, The Svedberg Laboratory Workshop on Applied Physics,Uppsala, May 3, 2001

Qs reduced with capacitydue to VDD & device scalingSmaller QS of SRAM cell

SER depends on QSDRAM; decreases with memorycapacity due to large intentionally-added CS & spatial scaling thatreduces charge collection.SRAM; increases with memorycapacity due to rapidly-decreasingparasitic CS despite spatial scaling.Solutions:•Increase in CS (SRAM cells)•Uses of triple well, redundancy,ECC etc.

SER

Cro

ss S

ecti

on/c

hip

(cm

2)

Memory Capacity (bits)100K 1M 10M 100M 1G

1E-5

1E-6

1E-7

1E-8

1E-9

1E-10

DRAM

SRAM

1

10

100

1000

Sig

nal

Ch

arge

, QS

(fC

)

Memory Capacity (bits)1G64M4M256K16K

4

DRAM

SRAM

Trench

Stack

Planar

12.56.95.1

Stand-aloneQS =CS VDD/2

ΔCS(α-SER: x10-3.5)

Soft Error of RAM Cells

9

K. Itoh, Hitachi

Error Checking & Correcting (ECC)

M. Horiguchi et al., IEEE J. SSC, 23, p.27, Feb.1988

ECC word = 128 data bits + 8 check bits, FIT = 10-9/hour

102 106 108104

SER without ECC (FIT)

SER

wit

h E

CC

(FI

T)

10-18

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

102

104

106

108

without ECC

periodic correction

(1 ECC word/7.8 μs)no corre

ction during 10-year period64 Mb

256 Mb

16 Mb

100

100

one upset/ 1 k hours

K. Itoh, Hitachi

Challenges to LV e-RAMs

1. RAM Cells•Maintain Signal Charge

–Small SER•Maintain Signal Voltage

& Reduce Noise–Stable & fast sensing–Wide voltage margin

•Reduce Cell Size–e-RAMs dominate SoCs

2. Peripheral Circuits •Reduce Leakage

–Small ISTB & IACT

•Reduce Speed Variation–Acceptable level

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001

e-RAM

RAM cellarray

DRAMSRAM

periph.

DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs

10

K. Itoh, Hitachi

Signal & Noise Issue of RAMsDRAM SRAM

Float. Signal sensitive to noisevS > (δVT + vN ),vS ≅ (VDD/2)CS /CD.vS; Large with small CS, if small

CD realized by short DL.δVT; Small if SA uses the largest

MOST possible (≥ 20F 2).vN; If reduced enough, sub-1-V

DRAMs realized.

Static Signal immune to noisevS ∝ VDD – (VT + δVT )VT; High (0.5 – 0.7 V) to reduce

leakage enough.δVT; Physically and statistically

large due to many cells withsmall MOSTs (2F 2) in a chip.

vS reduced with lowering VDD.Sub-1-V SRAMs difficult.

δVT : VT-mismatch between paired MOSTs

VDDDL

0Cs

"1"

"0"δVTvN

SA

CD

VDD –VT –δVT

VDD

iL

VT +δVT

DL DL

K. Itoh, Hitachi

• Cross-coupled MOSTsneed a high VT to ensure a small retention current through reducing iL.

• Such a high VT reduces DL-drive current of on-MOST with reduced gate-over drive, VDD – VT .

• δVT further reduces drive-current, preventing VDD -scaling.

High VT & δVT Issue for SRAM Cell

Average extrapolated VT (V) at 25 ºC -0.2 0 0.2 0.4 0.6 0.8 1.0

100 Lg =0.1 μmW (QT)=0.20 μm W (QD)=0.28 μm W (QL)=0.18 μm

Tj =125 °C100 °C

75 °C50 °C

25 °C

high speed(0.49)

low power(0.71)10 μA

0.1 μA

10-2

10-4

10-6

10-8

1-M

b ar

ray

rete

nti

on c

urr

ent

(A)

Extrapolated VT =VT (nA/μm)+0.3 V

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004

iL

VT +δVTVDD –VT –δVT

VDD

DL

11

K. Itoh, Hitachi

δVT increases with devicescaling.

δVT = √2 ΔVT

ΔVT : VT variation

δVT in SRAM cells is large, physically and statistically, due to many cells with small MOSTs in a chip, makingnano-scale SRAMs difficult to design. δVT & ΔVT have no room in time & area to be compensated for, unlike usual analog circuits.

Ever-Larger VT Mismatch, δVT

90 nm bulk

65 nm bulk

45 nm bulk

32 nm bulk

65 nm FD-SOI

45 nm FD-SOI

32 nm FD-SOI

Standard deviation (a.u.)210

σ (VT)σint

σext

σint

σext

σ (VT)

M.Yamaoka et al., Symp. VLSI Circuits 2004

σ(VT) = √σext 2 + σint 2

K. Itoh, Hitachi

Narrow VDD -Margin of SRAM Cellsdue to a high VT & large δVT

M.Yamaoka et al., Symp. VLSI Circuits 2004, R.Tsuchiya et al., IEDM2004 Dig. pp. 631-634

1.2

40

30

20

10

00.6 0.8 1.0

VDD (V)

130 nmbulk

90 nmbulk

65 nmbulk

0

SNM

(mV

)

VDDmin

VT (ext, 25°C ) = 0.4 Vintra-die 6σ (VT )

VDDmin(FD-SOI)

bulk

FD-SOIσ (VT )

VDDmin(bulk)

90 65 45 32

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1

2

3

Technology (nm)

VD

Dm

in@

12

5C

°(V

)

Sta

nda

rd d

evia

tion

σ(V

T)

(a.u

.)

0

VT (ext, 25°C) = 0.4Vinter-die 6σ (VT )

12

K. Itoh, Hitachi

Advantages of Double-Gate FD-SOI•Small ΔVT•Adjustable VT → multi-VT•Large VT change

(wide-range well-bias control)•Reduced SER•No body effect•Dynamic VT MOS circuits

(G-well connection)

wellcontact

well

G (Ni silicide)

thin BOX(< 10nm)

thin SOI (< 20 nm)

wellSTI

sub

STI STI

sub

D S

VT control dopant(1018/cm3)

M.Yamaoka et al., Symp. VLSI Circuits 2004, R.Tsuchiya et al., IEDM2004 Dig. pp. 631-634

90 nm bulk

65 nm bulk

45 nm bulk

32 nm bulk

65 nm FD-SOI

45 nm FD-SOI

32 nm FD-SOI

Standard deviation (a.u.)210

σ(VT)σintσext

σintσextσ(VT)

0.5

0.4

0.3

0.5

High dose

Low dose

VDD = 1.0 V

w/o

tSOI = 20 nmtBOX = 10 nm

0.2

0.1

0.0

-0.11.00.0-0.5-1.0

0.6

Well-bias voltage Vwell (V)

Thre

shol

d v

olta

ge

VT

(V)

K. Itoh, Hitachi

Dynamic-VT FD-SOI SRAM Cell

M.Yamaoka et al., SOI Conf. Dig. pp.109-111, Oct. 2004

DL DL

VDD +0.2V0VDD +0.2V

HP Cell

DL DL

VDD0VDD ST Cell

G-well connection 1.0

0.8

0

0.6

0.4

0.2

0 0.2 0.4 0.6 0.8 1.0

HPCellBulk Cell

ST Cell

Node voltage (V)

Nod

e vo

ltag

e (V

)

90 nmVT =0.4 V3σ(VT)

1.0

0.8

0

0.6

0.4

0.2

0 2 4 6 8 10Time (ns)

Vol

tag

e (V

)

ST Cell

Bulk Cell

HP CellWL

DL

128 cells/DL

13

K. Itoh, Hitachi

Sources of extrinsic δVT in the conventional cell:•Local size fluctuation •Pattern deformation after processing •Mask misalignmentSolutions:•The largest MOST possible •Lithographically symmetric cell

K. Osada et al., IEEE J. SSC, vol. 36, No. 11, pp. 1738-1744, Nov. 2001.M. Kanda et al., Symp. VLSI Tech. Dig. Tech. Papers, pp. 13-14, June 2003.F. Arnaud et al., Symp. VLSI Tech. Dig. Tech. Papers, pp. 65-66, June 2003.

Dotted area: after processingdiffused

poly gate

Conv. (2 cells)

QD QD

Proposed (2 cells)

QDQD

QD QD

Layout to reduce VT Mismatch, δVT

K. Itoh, Hitachi

Power-Supply Control Cellsdespite need for unscalable MOST or unscalable VDD

K. Itoh, ICICDT2005 Dig.

VDD +δVD (R) VDD−δVD (W) floating (W)

VDD (R)

WL WL

DL

VDD +δVD

DLVDD (0) 0 (VDD)

VDD

STBδVSACT

0

14

K. Itoh, Hitachi K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004

Raised-Supply Cell

• High VT (QD, QL) to reduce iL• δVD to offset a high VT & δVT• Low-VT (QT) to increase Icell ,

coupled with NW to cut iL (QT) Low leakage, high stability & lowpower with low-VDD DL.

SNM imbalanced by δVT

0.2 0.4 0.6 0.8 1.0 1.200

0.2

0.4

0.6

0.8

1.0

1.2

VL (V)

VR

(V)

VDD = 1 VδVD = 0.1 VδVT = 0.1 VVT (QTR) =VT (QDL)=VT (QLL) = 0.49 V

SNM

Lg = 0.1 μmW (QD) = 0.28 μm W (QT) = 0.20 μm W (QL) = 0.18 μm

VDD

VDD QTL-δVT QDR

-δVT

WL -δ

VDD +δVD

QTR

DLDL

Icell

VL VR

QLL QLR

QDL

VDD

K. Itoh, Hitachi

SNM

(mV

)

VT (QTR)(mV)

0

10

20

30

40

0

100

200

300

400

500

180 260 340 420 500

Icell (δVD = 0.2V)

SNM (δVD = 0.2V)

I cel

l(μ

A)

SNM (0)

Icell (0)

490

B

A

VT (QTR)(mV) 490

Possible with δVD = 0.2 V & VT (QTR) = 300 mV

0

10

20

30

40

I cel

l(μ

A)

0

100

200

300

400

500

180 260 340 420 500

SNM

(mV

)

Icell (δVD = 0.2V)

SNM (0)

Icell (0)

D

C

AB

SNM

(δVD = 0.2V)

SNM ≥ 100 mV, Icell ≥ 20 µA

Possible even with δVD = 0 &VT (QTR) = 490 mV

VDD = 1 V VDD = 0.8 V

High-Speed Cell (VT =0.49 V, δVT =0.1 V)

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004

15

K. Itoh, Hitachi

VT (QTR)(mV)

Impossible even with δVD = 0.2 V due to lack of Icell

400 480 560 640 720

Icell (δVD = 0.2V)

SNM (δVD = 0.2V)

SNM (0)Icell (0)

710

SNM

(mV

)

0

100

200

300

400

500

0

10

20

30

40

I cel

l(μ

A)

VDD = 1 V VDD = 0.8 VPossible with δVD = 0.2 V &VT (QTR) = 505 mV

400 480 560 640 720

SNM

(δVD = 0.2V)Icell(δVD = 0.2V)

SNM (0)

Icell (0)

VT (QTR)(mV)

0

100

200

300

400

500

SNM

(mV

)

0

10

20

30

40

I cel

l(μ

A)

710

SNM ≥ 100 mV, Icell ≥ 20 µA

Low-Power Cell (VT =0.71 V, δVT =0.1 V)

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004

K. Itoh, Hitachi

0.1

1.0

130 90 65 45Technology (nm)

Cel

l Siz

e (r

atio

)

(2.12 μm2)

0.54

0.24

0.17

0.12

0.2

0.3

0.40.5

Non-raised

Raised0.49

(only MOST sizes kept same)

0.30

Area Penalty of Raised-Supply Cell

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004

16

K. Itoh, Hitachi

Raised-Source Lowered-VDD CellAt active-standby transition

K. Osada et al. ISSCC2003 Dig. pp. 302-303

Electric-field relaxation90% reduction ingate leakage & GIDL

Sub-S backbias90% reduction insubthreshold leakage

G-S backbias100% reduction insubthreshold leakage

Standby

Active

DL DL0.5 V 1.0 VVSS

1.0 V0.0 V 1.5 V1.5 V

1.5 V

WL 0 V

0.5 V 1.5 V

K. Itoh, Hitachi

Measured Retention Current of Cell

K. Osada et al. ISSCC2003 Dig. pp. 302-303

Successful Application1.5-V 27-ns 6.42 x 8.76 mm2 16-Mbusing ECC with 3.2-ns/9.7% speed/area penalties.

(1) Leakage still large1.6 μA for 16 Mb despite high VT , thick tox, and S-driving.(2) Reduced QS in standby modeThe cell power-supply decreases by the raised source voltage.Further low-VDD operation may behazardous, even if ECC is used.

Limitations and Challenges

Conv.

Prop.

25ºC

Sub. + GIDL 48.5

PMOSNMOS NMOS

95 fA

PMOS

17 fA

Tunnel 46.5

3 14VT (extrap.) = 0.7 V(N), -1 V(P)tox (electrical) = 3.7 nm

NMOSConv.

102 fA

PMOS

1244 fA

Prop.

PMOSNMOS

90ºC

Sub. + GIDL 1182

Tunnel 62

81Subthreshold currentsensitive to temp.

17

K. Itoh, Hitachi

• Large conductance of PMOS loadmay prevent a successful write of opposite data.

• Reducing the conductance during write resolves the problem.

• It is realized by lowering or floating the power supply.

Eventually, read margin determines VDDmin of the cell, implying that a largevalue of (VT + δVT) is the obstacle tolow-voltage operations.

Power Controls for Wide Write-Margin

VDD (R)floating (W)

VDD +δVD (R)VDD −δVD (W)

VDD 00 VDD

VDD VDD

K. Itoh, ICICDT2005 Dig.

K. Itoh, Hitachi

Challenges to LV e-RAMs

1. RAM Cells•Maintain Signal Charge

–Small SER•Maintain Signal Voltage

& Reduce Noise–Stable & fast sensing–Wide voltage margin

•Reduce Cell Size–e-RAMs dominate SoCs

2. Peripheral Circuits•Reduce Leakage

–Small ISTB & IACT

•Reduce Speed Variation–Acceptable level

K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001

e-RAM

RAM cellarray

DRAMSRAM

periph.

DL

SRAMDRAM

WL VDD

0

"1"

"0"

DLWL

0 VDD

DL

Cs

18

K. Itoh, Hitachi

RAM Cells (DRAM)Short DL allows a small CS & simple CS-structure with small CD.Planar-CS cell might replace e-SRAM cells. vsig ≅ CS/CD ⋅VDD/2.In addition, short DL enables low-VDD fast operation.

proposed (ISSCC2005) conventional

Cells/DL 32 128CS 5 fF (Ta2O5; MIM) ≥ 15 fF (MIS)

Additional wire No local wire (M0)Thermal budget no impact on logic intolerable impactCell RC delay W storage cont. Non-metalized cell

Co-salicided S/DCell contact R 10 Ω 10 kΩ

M. Iida et al., ISSCC2005 Dig. p.460, M. Shirahata et al., ISSCC2005 Dig. p.462

M3

M2

DL (M1)

Logic DRAM

M1

DL(M0)

M3

M2

M1 DL

Logic DRAM

K. Itoh, Hitachi

-Vertical Cell Stacking Poly-Si Load PMOS-

H. Matsuoka et al., Symp. VLSI Tech. June 17 2004

Source

Drain

Gate

Channel

1.2096 μm2

(1.44 x 0.84) with 0.13 μm

• Size reduced to 0.6• Poly-Si PMOST

S = 75 mV/dec.IDS =30 μA/cell

Vertical PMOS

Cell Size Reduction (6-T SRAM Cell)

19

K. Itoh, Hitachi

-Vertical Cell Stacking TFT Load PMOS-

S.-M. Jung, et al., Symp. VLSI Tech. June 2004.H-jun An, et al., Symp. VLSI Circuits, June 2004.

single-crystalthin film transistor (TFT)

• Size reduced to 0.54• TFT PMOST

S =140 mV/dec.IDS = 2/3 of the bulk

• 1.3-V 49-ns 64 Mb

0.288 μm2

(0.56 x 0.51) with 80 nm

VSS DL VDD VSSDL

WL

TFT

Poly-Si TFT: VDD > 3 V, VT > 2.5 V(large S & poor Ion/Ioff )

Cell Size Reduction (6-T SRAM Cell)

K. Itoh, Hitachi

Stacked TFT SRAM Cells

S.-M. Jung, et al., Symp. VLSI Tech. June 2004, Y.H.Suh et al., ISSCC2005 Dig. p.476.

Cell Size Reduction (6-T SRAM Cell)

• Single-crystal TFTThe highest density cell(25F 2) comparable to DRAM cells.1.8-V 61.1-mm2 144-MHz256-Mb SRAM.

• Drawbacks as e-SRAMsSophisticated process, High-VDD operation due to TFT PMOST ofS =140 mV/dec.,IDS = 2/3 of the bulk.

Load p-TFTs & transfer n-TFTsdouble-stacked over bulk driver n-MOSTs in different levels of layers.

20

K. Itoh, Hitachi

Cell-Size Comparisons

3-T cells: Small, simple, and suitable forlow-VDD operations due to gain function.

Cel

l siz

e (r

atio

)20

01-T 1-T 4-T 6-T

15

5

(Sta

nd

-alo

ne

8F

2 )

1

20.5

3-T 3-T

3.65.6

6.7

SAC for stand-alone DRAMNo SAC for others

1.8

10

3 polySAC 3 poly

3

8

L.I.

3D

3D

14

3

K. Itoh, Hitachi

Dual VDD for RAMs withHigh VDD for CellsLow VDD for Periphery

Different Requirements:Cells; Low leakage/High stability

•High and unscalable VTDRAM; Longer tREF with largermemory to preserve the refresh busy rateSRAM; Const. IRET despite larger memory for low-power systems

•High VDD for large QS•Thick tOX for small iG

Periphery; Low power/High speed

•Low VT/Low VDD/Thin tOX

Future Prospects for RAMs

SRAM (bits)DRAM (bits)

0

64M64M 128M 256M 512M4M 8M 16M 32M

1G

Periphery(ITRS 2001)

0.5

Nec

essa

ry V

T(V

, 25°

C, e

xt.)

1

1.5cell

arrayperi. low cost

low power

high speed

DRAM cellSRAM cell

K. Itoh et al., CICC 2004 Dig. Tech. Papers, pp.339-344, Oct. 2004Y. Nakagome et al., IBM J. R&D, Vol.47, No.5/6, Sep./Nov. 2003

21

K. Itoh, Hitachi

6-T SRAM Cells: A high VT & large δVT of cells will prevent VDD -scaling, calling for alternatives if ultralowVDD needed. For relatively high VDD, it will continue tobe used. Challenges;•Enlarging MOST sizes to reduce δVT, but for small memories.

•New circuits & devices such as controls of cell supply, and FD-SOI. 3D SRAM cells for stand-alone SRAMs.

DRAM Cells: 1-T & 3-T cells would be candidates for low-VDD large memories. Challenges;•The simplest CS possible with logic processes •Half-VDD sensing with reducing noisesNon-Volatile RAMs: Strong candidates, if challenges (stability, competitive cell size, rapid-scaling ability) are accomplished.

Future Prospects for RAM Cells

K. Itoh, Hitachi

1. Eventually, subthreshold-currents of RAMs will be reduced enough even for active mode, as far as RAMs are concerned. Precise controls of internal supply-voltages will continue to be important.(New gate insulators are needed soon)

2. Speed variation issue of periphery will be serious.Compensations will be indispensable:For inter-die Δτ ; VBB control essential.For intra-die Δτ ; New MOSTs with a small ΔVT vital.

Circuit techniques unable to manageexcessive variations. FD-SOI?

Two approaches:High-VDD bulk-CMOS for low-cost RAMsLow-VDD FD-SOI for high-speed low-power RAMs

Future Prospects for Periphery

22

K. Itoh, Hitachi

Double-gate MOSFET• Back-gate biasing of a thin-body MOSFET remains effective for

dynamic control of Vt with transistor scaling, and can provide improved control of short-channel effects as well.

• Collaborate work with Sriram B., Radu Z., and Prof. T. J. King.

Drai

n

Sour

ce

Gate

Fin Height HFIN = W/2

Gate length = Lg

Fin Width = TSi

Drai

n

Gate1

Sour

ce

SwitchingGate

Gate2Vth Control

Fin Height HFIN = W

Gate length = Lg

Back-gated (BG) MOSFET• Independent front and back gates• One switching gate and Vth

control gate

Double-gated (DG) MOSFET

K. Itoh, Hitachi

Conventional 6T SRAM Cell

• Double-Gated (DG) FinFETArchitecture.– FinFET channel surface along (110) plane.– High Threshold devices used to suppress leakage.

• NMOS work-function used for PMOS devices.

• PMOS work-function used for NMOS devices.

– SNM during read ~ 210mV.

00.10.20.30.40.50.60.70.80.9

1

0 0.5 1

Vsn1 (V)

Vsn

2 (V

)

50HFIN (nm)

1016Channel

Doping, NBODY(cm-3)

1.0VDD (V)

20TSi (nm)

20Tox (Å)

35LSD (nm)

35LG (nm)

23

K. Itoh, Hitachi

6T SRAM Cell with Rotation

• Double-Gated (DG) FinFET Architecture with Rotation.– Channel surface along (110) plane for access and PMOS load devices.– Channel surface along (100) plane for NMOS pull-down devices to increase β-

ratio.– High Threshold devices used to suppress leakage.

• NMOS work-function used for PMOS devices.• PMOS work-function used for NMOS devices.

– SNM during read ~ 230mV.

6.6um X 8um

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.5 1

Vsn1 (V)

Vsn

2 (V

)

K. Itoh, Hitachi

6T SRAM Cell with Feed-back

• Double-Gated (DG) NMOS pull-down and PMOS load devices.• Back-Gated (BG) NMOS access devices to dynamically increase β-ratio.

– FinFET Channel surface along (110) plane.– High Threshold devices used to suppress leakage.

• NMOS work-function used for PMOS devices.• PMOS work-function used for NMOS devices.

– SNM during read ~ 300mV.– Area penalty ~ 19%– Motivation from Yamaoka, Hitachi, 2004

00.10.20.30.40.50.60.70.80.9

1

0 0.5 1Vsn1 (V)

Vsn

2 (V

)

24

K. Itoh, Hitachi

4T SRAM Cell Design

• Data retention leakage current usually need to be at least 1000xIleakage to compensate for the widely fluctuating leakage current.

• Data retention leakage current flows on both sides but only needs to flow in one side for data retention.

Yamaoka, Hitachi, 2004

K. Itoh, Hitachi

4T SRAM Cell with Feed-back

• Double-Gated (DG) NMOS pull-down devices.• Back-Gated (BG) PMOS access devices to dynamically increase

compensation current and β-ratio.– FinFET Channel surface along (110) plane.– NMOS work-function used for PMOS devices – high threshold.– NMOS work-function used for NMOS devices – nominal threshold.– SNM during read ~ 310mV.– Area savings ~ 36% compared to 6T BG and 24% compared to 6T DG.

25

K. Itoh, Hitachi

SRAM Layouts

6T DG

6T BG Access

6.6um X 8um

7.85um X 8um Complete Array

4T BG Access 5um X 8um6T Rotate NPD 6.6um X 8um

K. Itoh, Hitachi

26

K. Itoh, Hitachi