7/24/2019 EE2020 L0 Intro

1/13

Modified from original slides by Prof. XU Yong Ping 1

Massimo ALIOTO

Dept of Electrical and Computer EngineeringEmail: massimo.alioto@nus.edu.sg

EE2020 / EE2020E

Digital Fundamentals (1)(L0 - Introduction)

2

Instructors Massimo ALIOTO (Part 1)

Email: massimo.alioto@nus.edu.sg

Office: E4-05-24

Dingjuan CHUA (Part 2)

Email: elechuad@nus.edu.sg

Office: E4-03-10

Teaching Assistants

MrAHMAD Shahzor, elesha@nus.edu.sg MrChristopher Moy Shin Lee Lan Chong, llc@nus.edu.sg

7/24/2019 EE2020 L0 Intro

2/13

Contents Part 1

Number systems

Boolean Algebra and logic gates

Hardware Description Languages: Verilog

Gate-level design and minimization + Verilog

Combinational logic circuits and design + Verilog

Part 2 Sequential logic circuits + Verilog

Combining combinational/sequential building blocks + Verilog

Finite State Machines+ Verilog

Field Programmable Gate Arrays

Memory devices

3

Module introduction

First course on digital systems

Introduces fundamental digital logic, digital circuits, andprogrammable devices

The course also provides an overview of computersystems

This course provides students with an understanding ofthe building blocks of modern digital systems and methodsof designing, simulating and realizing such systems

The emphasis of this module is on understanding thefundamentals of digi tal design across di fferent levels ofabstraction using Hardware Description Languages

Developing valuable design skills for the design of digitalsystems through FPGAs and state-of-the-art CAD tools,as required by the job market (exciting projects)

4

Course Description

7/24/2019 EE2020 L0 Intro

3/13

Expected learning outcome (Part 1)

Be able to perform conversion between binary, octal, hexadecimaland decimal number systems, and solve simple problems;

Understand Boolean Algebra, and manipulate and simplifyBoolean functions using theorems and postulates;

Be able to design simple combinational logic circuits based onTruth table and Karnaugh Map

Be able to design complex combinational logic circuits usingHardware Description Languages (Verilog) and/or combinationalbuilding blocks/IPs

Be able to simulate complex combinational blocks and verify theirproper functionality through behavioural simulation

Be able to design combinational logic circuits for practicalproblems/applications

5

Expected Learning Outcomes

Expected learning outcome (Part-2)

Be able to describe simple sequential logic circuitsbased on state transition diagrams

Be able to design complex logic circuits usingHardware Description Languages (Verilog) and/orsequential/combinational building blocks/IPs

Be able to simulate complex blocks and verify theirproper functionality through behavioural simulation

Be able to design complex logic circuits for practicalproblems/applications

6

Expected Learning Outcomes

7/24/2019 EE2020 L0 Intro

4/13

Part-1

10 lectures (2+1 hours/week)

5 tutorial sessions starting in Week 2 (Check your group andvenue)

4 Laboratory sessions, starting in Week 3

Part-2 12 lectures (2+1 hours/week)

5 tutorial sessions (Check your group and venue)

5 Laboratory sessions, of which 4 are devoted to the final project(full system on FPGA), starting in Week 7

7

Module organization

8

Module Assessment

Part 1 (50%)

Project D1 (D1B&C): 30%

Mid-term quiz: 20%

Part 2 (50%)

Project D2 (D2A&B): 30%

Final quiz: 20%

No final exam

7/24/2019 EE2020 L0 Intro

5/13

9

EE2020 Part I Topics

Week Lectures Remark

Week 1 Introduction/ Number systems

Module introduction,Position numbersystems, number system conversion, signed

numbers. Arithmetic using signed numbers,

BCD, addition using BCD.

Week 2 Boolean Algebra/Verilog

Theorems, Boolean functions, truth table,

SOP/POS form, truth table to SOP or POS,

minterm/maxterm, canonical form. Gates &truth table, positive/negative logics and

conversion, mixed logic. Intro to Verilog

(modules, operators, Boolean expressions).

Week 3Gate-level design &

simplification/Verilog

Karnaugh map, gate-level simplificaton and

implementation. Modeling gates and

Boolean functions (dataflow).

Week 4Gate-level Design &

Minimization/VerilogCombination logic MSI and design using MS

Week 5Complex combinational

logic/Verilog

Adders, comparators, decoders/encoders,(de)multiplexers, tri-state logic. Modeling

combinational logic (behavioral, structural),

simulation, synthesis.

Week 6Logic IC families and intro to

sequential elementsLogic IC families, D, SR, JK, T flip-flops,resets, and their Verilog description

10

EE2020 Part II

MAJOR TOPICS DETAILS

Recess week

Counters and registersCustom Counters, Registers, FF Conversion, Design Method. Registers,flip-flop conversion, design methods.

Introduction to Finit e Stage MachinesSynchronous state machines. State machine structures : Mealy & Moore

types. Analysis of state machines. State transition diagrams and

synthesis. Top-Down design examples.

FSM DesignCombining FSMs with other architectural elements. Verilog description ofFSMs. Design examples.

Field Programmable Gate Arrays and

programmable devices

Description, internal architecture and notations of various PLDs:Programmable Array Logic (PAL), Programmable Logic Array (PLAs), and

Programmable Read Only Memory (PROM). Introduction to CPLDs,FPGA and design flow process.

Memory DevicesMemory devices: fundamental building blocks of computer systems.

RAMs, ROMs, Applications of Memory Devices. Design of MemoryModules.

7/24/2019 EE2020 L0 Intro

6/13

11

EE2020 CA Schedule (might change a bit):

Labs, Projects, Assignments & Quizzes

Week Lab (Part 1) Lab (Part 2) Quizzes

Week 3 L ab 1 Get ti ng t o K no w Yo ur FPGA I -

Week 4 Lab 2 Get ti ng to Know Your FPGA II

Week 5 Lab 3 Combinational Circuits in Verilog -

Week 6 Lab 4 Sequen ti al Ci rcui ts in Ver il og I

Recess Week No lab No lab mid-term quiz

Week 7Lab 5 Sequential Circuits

in Verilog II

Week 8 Project 4

Week 9 Project 5

Week 10 Project 6

Week 11 Project 7

Week 12 Project evaluation

Week 13 Final Quiz

Lab venue: Digital Electronics (E4-03-07)

12

EE2020 Tutorial Schedule (Part I)

For each tutorial, questions will be posted on IVLE the week before, the solutions will be

published at the end of the same week

Week Tutorials Assignment

WK1 No tutorial

WK2 Tutorial - 1

WK3 Tutorial - 2

WK4 Tutorial - 3

WK5 Tutorial - 4

WK6 Tutorial - 5

Recess Week

7/24/2019 EE2020 L0 Intro

7/13

Course materials IVLE (everything about the course)

Need help Discussion Forum under IVLE (preferred)

Tutors (tutorial questions)

TAs and GAs (labs and projects) during lab sessions

Face-to-face consultation with lecturer: by appointment, to be taken at the end of each lecture

then, the date/time of the appointment is publicized on IVLE, so that anystudent can join

Reference book (download from NUS library) D. Harris, S. Harris, Digital Design and Computer Architecture (1st ed.),

Morgan Kaufmann

13

Module information

14

Before Getting Started...

7/24/2019 EE2020 L0 Intro

8/13

15

Before Getting Started...

1. Analog vs. digital circuit

2. Why digital?

3. Why study this module?

16

Introduction

7/24/2019 EE2020 L0 Intro

9/13

17

Analog vs. Digital Circuit

Analog circuit deals with continuous signals

Digital circuit deals with signals having discrete

levels

t

V Analog signal

t

V Digital signals

18

Analog vs. Digital Circuit (cont.)

Analog circuit is more susceptible to noise

Digital circuit is a binary system which is much more

robust

A

Analog amplifier Inverter

Vin Vo Vin Vo

7/24/2019 EE2020 L0 Intro

10/13

19

Why digital?

Robustness (reliability)

Programmability

Scalability (in integrated circuit technology)

Cost

20

Technology Scaling

*Dennis Buss, Texas Instrument, USA

Semiconductor Technology Scaling

7/24/2019 EE2020 L0 Intro

11/13

21

Technology Scaling (cont.)

Number of transistors per chip

As more and more transistors can be integrated on a single chip,

- the functionality is increased

- Or for the same functionality, the chip area is reduced Cost per transistor is

reduced.

Moores

law

22

Technology Scaling (cont.)1971:

Intel 4-bit processor in 10 m PMOS

process with 2300 transistors

Initial clock speed of 108 kHz

10m pMOS technology

2013:

Intel Xeon E7-8870 processor (10 cores) 2.6

billion transistors IBM zEC12 5.5 GHz clock freq., MCM with 6

X 6 cores in 32 nm SOI, 6 X 300W power

(liquid cooling!), 2.75 billion transistors for

each core, single-thread high performance

Intel Core i7-4960X (6 cores)

in 22nm trigate CMOS

7/24/2019 EE2020 L0 Intro

12/13

23

Technology Scaling (cont.)

year

log

1971 2011

Dennardsscaling

2005

1 W

100-150 Wpower

power limitedregime

1947 Invention of transistor

1971 First microprocessor

1980s Personal computers

1990s World Wide Web, digital cameras

2000s Mobile phones, digital TVs, ipod

circa 2010 Smart phones, xPad, cloud computing

(accessible everywhere), social networking (constantlyconnected)

2013 and beyond Cloud computing, Internet of things, ultra-

low power high-performance mobile computing, ubiquitous

computing, immersive computing/augmented reality, gesture

recognition...24

Digital Revolution and Information Age

*Rapid development of digital computing and communication

technology brought about the digital revolution and information age

7/24/2019 EE2020 L0 Intro

13/13

The module is about the fundamentals of digitalsystems, which is important if you are interested in thedesign of digital circuits and systems, especially if youplan to specialize in the following areas:

Digital integrated circuits (very important)

Embedded systems (very important)

Its the first module about Hardware DescriptionLanguage (HDL), which is widely used for digitalsystem design and modeling

You will also learn analytical and problem solving skillsthrough the projects (practical design problems)

It also serves as prerequisite for other modules atsenior levels.

25

Why studying this module?