Lab 5: Simple Arithmetic Logic Unit

Deanna SessionsECEN 248-511

TA: Priya VenkatasDate: October 9, 2013

Objectives:This week’s lab involves designing and implementing a 4-bit ALU which can add, subtract, and AND bits. This lab involves delving into the world of Two’s Complement arithmetic and multiplexers to create this circuit which thus far is uncharted territory for this class. In order to properly understand how to build the 4-bit ALU we must first understand how adding and subtracting binary actually works through Two’s Complements and then we must learn how to use multiplexors (multiple inputs) to implement a circuit that uses the Two’s Complements to add and subtract.Design:Minimized Boolean Algebra, K-Map, and Truth Table for a 2:1 multiplexor. Table 5.1: Truth Table for 2:1 Multiplexor

S A B F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Table 5.2: K-Map for 2:1 Multiplexor

AB\S 0 100 0 001 0 111 1 110 1 0

F = S’ * A + S * B

Figure 5.1: Gate Level Schematic of a 2:1 MUX

Figure 5.2: 4-bit addition/subtraction circuit

Figure 5.3: 4-bit wide 2:1 MUX Schematic

Table 5.3: Operations of the MUX within the ALU

c0

c1 Op

0 0 Add0 1 Sub1 0 AND1 1 AND

Figure 5.4: ALU schematic

Figure 5.5: Physical ALU circuit

Results:The circuit worked the way that it was supposed to work after fighting with it for a while and finally finding out what wires had been improperly placed. It was a lot of trial and error, but it worked in the end and was able to switch between the AND block and the add/sub block. The final physical circuit is pictured on the previous page.

Conclusion:

This was by far the most challenging circuit that we had to build because of the intricacy of using every pin on each component and all of the wires going everywhere but I was able to get it working after much fighting with it. I learned that sometimes you just have to go for it and then take it apart if it doesn’t work out. I fought with it for a while and then finally just scrapped the entire circuit and decided to start from scratch after having difficulties previously. In these first 5 labs I have learned the importance of powering and grounding all of the necessary ICs before attaching other wires because it is very easy to forget this important step. On a more technical scale I learned how to properly use a MUX and how to design an addition/subtraction circuit. I also learned the importance of datasheets when it comes to setting up these circuits because the pins can get very confusing very quickly.

Post- Lab Deliverables:Table 5.6: Table with values from the breadboard:

Control C1

Control C0 A B Result S3 S2 S1 S0

Overflow

1 1 6 2 4 0 1 0 0 01 1 5 3 2 0 0 1 0 01 1 4 2 2 0 0 1 0 01 1 3 1 2 0 0 1 0 01 1 2 1 1 0 0 0 1 01 1 6 5 1 0 0 0 1 00 1 5 2 7 0 1 1 1 00 1 3 4 7 0 1 1 1 00 1 2 5 7 0 1 1 1 00 1 1 6 7 0 1 1 1 00 1 4 3 7 0 1 1 1 00 1 6 2 8 1 0 0 0 00 1 8 8 16 0 0 0 0 10 1 10 10 20 0 1 0 0 10 0 6 1 0 0 0 0 0 00 0 6 2 2 0 0 1 0 0

The maximum gate delay possible on my particular ALU is shown below with a time delay of 5 units.

Figure 5.6: ALU with maximum time delay shown

Figure 5.7: Constructing an 8:1 MUX from 4:1 and 2:1 multiplexors

Student Feedback:

2:1 MUX

4:1 MUX

4:1 MUX

1. I liked the challenge of this lab, but I didn’t like how confusing the Pre-Lab portion was. It was difficult to complete the Pre-Lab because a lot of what we were learning was very hands on and there was not a lot of material that we could find about it prior to the lab.

2. The lab itself was not unclear, but once again I think the Pre-Lab could have had a bit more guidance to it.

3. Change the Pre-Lab to have a bit more instruction as to what we are being asked. A lot of us had an issue with completing the tasks because we didn’t know what was being asked of us and didn’t know how to find the proper information.