ECEN 248 Lab 8 Report

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Lab 8: Introduction to Sequential Logic

Rebecca Sontheimer

ECEN 248-511TA: Mehnaz Rahman

Date: November 5, 2014



ObjectiveThe objective of this lab is to understand more about sequential logic. This

includes learning about latches and flip-flops. This lab also involves the concept of time

delays, which are a large part of designing intricate circuits. The concept of a

synchronous circuit has been talked about in previous labs, but we have not really cared

about time delay up until this point and now we will account for timing with a clocksignal.

DesignAttached are the six different source codes that were used during the lab with

comments notating what is occurring in each part of the code. Each source code is written

using behavior Verilog and is run using a given “test bench” code that is used to check

that the behavior of the circuit is correct and to create a diagram that displays the

waveforms of the described circuit. For the test bench code that I had to partially writemyself, I created a truth table in order aid me in my design.

ResultsThe waveforms that resulted from each source code are shown below. These

waveforms are created by running the given test bench code with the source code in order

to generate a visual representation of the timing within a certain circuit.

SR _Latch (2 ns)



SR_Latch (4ns)

D_Latch



D_Flip_Flop

D_Flip_Flop_Behavioral



D_Latch_Behavioral

2-Bit Adder



Synchronous Adder

ConclusionIn conclusion, this lab was successful. I learned a lot about sequential logic and

how to implement it using various Verilog techniques (dataflow, structural, behavioral). I

also learned about the importance of time delays. If a circuit is not designed to account

for time delays, serious issues could arise and affect the outcome of the circuit.Post-Lab Deliverables

1. All code is listed in the design section of this lab.2. Screenshots are provided in the results section of this lab.

3. Questions throughout lab:

a. Now, change the 2 unit delays in your code to 4 units and run the test

bench again. Explain the results of the simulation.Using the 4 ns delay caused the Q and notQ results to be delayed by 4ns

instead of 2 ns and the R, S, and En bits stayed the same as they were from

the 2 ns simulation. This makes sense because the inputs do not have thetime delay applied to them, the time delay comes through the circuit and

the outputs are the ones affected.b. Simulate your D flip-flop using the “d flip flop tb.v” file in the course

directory. Add the internal nets within your D flip-flop to the

waveform and examine the waveform after restarting the simulation.

Do the latches behave as expected? Why or why not?

The latches behave as expected when the internal nets have been added.

c. Compare the waveforms you captured from the behavioral Verilog

(d_latch_behavioral.v and d_flip_flop_behavioral.v) to those captured



from the structural Verilog. Are they different? If so, how?The main difference is the time it took to start receiving data for Q and

notQ. The behavioral Verilog was faster than the structural Verilog. Also,the D Latch had no time delay in the behavioral, but a significant delay in

the structural.

4.

The advantage to using the behavioral description is that it is concise and uses onestatement that then decides the output rather than having to go through eachspecific answer and check it. In structural and dataflow Verilog, efficiency is lost

because it has to read for each specific output rather than just paying attention to

the output behavior as a whole. I prefer behavioral Verilog when it comes to this because it works more efficiently.

5. The timescale that the circuit can be reduced to and still work is 20 ns and works

at a 50MHz clock rate. Increasing the width of the adder would cause the clock

rate to drop because it has to work with more inputs than previously, resulting in alonger time delay and causing a drop in the clock rate. To improve the clock rate

of the design, you could reduce the time delay in the circuit by reducing the

circuit to fewer gates or by using gates with less time delay.

Feedback1. I liked this lab because it was very informative and useful. I liked that the lab

manual was like a tutorial with step-by-step instructions. There was nothing that Idisliked.

2. All parts were very clear and informative.

3. No need to improve this lab.

ECEN 248 Lab 8 Report

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