RossLightfootECEN248504

Lab8Mehnaz4215

ObjectiveTheobjectiveofthisweekslabwastointroducesequentialcircuitsandstorage

elementssuchasflipflops.

DesignIncludedarethesourcecodesforthemodulescreatedinlab,commentedto

showwhateachcomponentdoes.//sr_latch`timescale1ns/1ps`default_nettypenone//definemodulesetupmodulesr_latch(Q,notQ,En,S,R)//output&inputs

outputwireQ,notQinputwireEn,S,R

//internalwires

wirenandSEN,nandREN

//gateswith4nsdelaynand#4nand0(Q,nandSEN,notQ)nand#4nand1(notQ,nandREN,Q)nand#4nand2(nandSEN,En,S)nand#4nand3(nandREN,En,R)

endmodule//d_latch`timescale1ns/1ps`default_nettypenone//definemodulesetupmoduled_latch(Q,notQ,En,D)//input&outputwires

inputwireD,EnoutputwireQ,notQ

//internalwireswirenandDEN,nandNotDEN,notD

//gateswith2nsdelaynot#2not0(notD,D)nand#2nand0(Q,nandDEN,notQ)nand#2nand1(notQ,nandNotDEN,Q)nand#2nand2(nandDEN,D,En)nand#2nand3(nandNotDEN,notD,En)

endmodule//d_flip_flop`timescale1ns/1ps`default_nettypenone//definemodulesetupmoduled_flip_flop(Q,notQ,Clk,D)//input&outputwires

outputwireQ,notQinputwireClk,D

//internalwireswirenotClk,notNotClkwireQ_mwirenotQ_m

//gateswith2nsdelay

not#2not0(notClk,Clk)not#2not1(notNotClk,notClk)

//instantiatethemasterslaved_latchmodules.

d_latchmaster(Q_m,notQ_m,notClk,D)d_latchslave(Q,notQ,notNotClk,Q_m)

endmodule//d_latch_behavioral`timescale1ns/1ps`default_nettypenone//definemodulesetupmoduled_latch_behavioral(

outputregQ,outputwirenotQ,inputwireD,En

)//WheneverThere'sEnableorData,ifenableishigh//thenQsetstodata,otherwisejustpreviousQ

always@(EnorD)if(En)

Q=Delse

Q=QassignnotQ=~Q

endmodule//d_flip_flop_behavioral`timescale1ns/1ps`default_nettypenone//definemodulesetupmoduled_flip_flop_behavioral(

outputregQ,outputwirenotQ,inputwireD,inputwireClk

)//Ontheclock'spositiveedgesetsQtoData

always@(posedgeClk)Q

outputreg[1:0]Sum_reginputwireClkinputwire[1:0]A,B

//internalnetsreg[1:0]A_reg,B_regwireCarrywire[1:0]Sum

//instantiate2_bitadder

adder_2bitAdd1(Carry,Sum,A_reg,B_reg)

//onclock'spositiveedgeAinternalsettoA,BinternasettoBalways@(posedgeClk)

beginA_reg

//sr_latch

//D_Latch

//D_Flip_Flop

//D_Latch_behavioral

//D_Flip_Flop_behavioral

//adder_2bit

//adder_synchronous

ConclusionThislabwaswasagoodwaytointroduceustosequentialcircuits.Welearneda

lotaboutimplementingthecircuitsthroughverilog,aswellashowtimedelayscanaffecttheoutcomeofsuchcircuits.

Questions1.(SeeDesign)2.(seeResults)3.LabQuestions

a.Now,changethe2unitdelaysinyourcodeto4unitsandrunthetestbenchagain.Explaintheresultsofthesimulation

ThedelaymadetheQandnotQsignalsdelay4nsinsteadof2,buttheinputsignalsstayedthesame.

b.SimulateyourDflipflopusingthedflipfloptb.vfileinthecoursedirectory.AddtheinternalnetswithinyourDflipfloptothewaveformandexaminethewaveformafterrestartingthesimulation.Dothelatchesbehaveasexpected?Whyorwhynot?

Yestheybehaveasexpected.c.Comparethewaveformsyoucapturedfromthebehavioral

VerilogtothosecapturedfromthestructuralVerilog.Aretheydifferent?Ifso,how?

TheQandnotQsignalswerefasterforthebehavioralcircuitsthanthestructuralcircuits.

4. Behavioralverilogallowsonetospecifyhowamodulebehavesthroughcommandsratherthanhavetofollowaspecificformlikestructuralverilog.Behavioralallowsyoutobypassmuchofthebasiclevelassignmentsandstuffrequiredinstructuralverilog.5. Thecircuitcanbereducedto20nsandstillpassthetests,@a50MHzclocksignal.Increasingthewidthoftheadderwouldmaketheclockratedropduetoincreasedinputs,increaseddelay.Improvingtheclockratewouldinvolvemakingthecircuitmoreefficientbyreducinggatesandcriticalpathstoaminimum.

Feedback1.Ilikedlearningthenewtricksofveriloglikethedelaycommandforthegates.TherewasntanypartofthelabIdisliked.2.Themanualwasclearandveryhelpful.

3.Thelabwasgood,nosuggestions.