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Lab 10: An Introduction to

High-Speed AdditionRebecca SontheimerECEN 248-511

TA: Mehnaz RahmanDate: November 19, 2014

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Objective

The purpose of this lab is to understand why certain circuits are used for certain purposes. We learn that a ripple carry adder is not sufficient enough for some high-speedcircuits. Therefore, in this lab we will experiment with a carry-lookahead addition for fast

addition in high-speed arithmetic units. This kind of circuit it minimizes the delay thatwould be encountered in the ripple carry. This will involve the implementation ofdataflow and structural Verilog.

Design

Attached are the source codes for all of the circuits.

Results

Below are the waveforms of the various experiments throughout the lab, whichare labeled accordingly.

Experiment 1 Propagation delay with markers

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Experiment 2 Test-Delay 16 (All tests passes)

Experiment 2 Test-Delay 15 (Failed tests)

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Conclusion

In conclusion, this lab was successful and all of the code worked properly. Thislab showed again how important delay is in a complex circuit. The problem with a ripplecarry adder is that its propagation delay is too slow for most digital electronics. I t is

basic and not practical. That is where the carry lookahead adder comes into play. Thistype of unit is a better technique for binary counters and can drive a synchronous circuitat a much faster speed.

Post-Lab Deliverables

1) Source code included in the design section.2) Screenshots included in results.3) Questions throughout lab manual:

a) Experiment 2: If your calculations in the prelab are correct and you correctlyadded delays to your sub-modules, you should find that the computed delay

matches the measure delay. Is this the case?i) Yes it is the case. I calculated delta-g to be 2 ns and that the coefficient was 8.This time delay of 16 ns was exactly what the time delay ended up being forthis circuit.

4) How does the gate-count of the 16-bit carry lookahead adder compare to that of aripple-carry adder of the same size?a) The 16-bit carry look-ahead adder has 82 gates in it and a 16-bit ripple carry

adder has about 80 gates (varying depending on the internal components of thefull-adders.) However, for roughly the same amount of gates the 16-bit carrylook-ahead adder as the ripple-carry adder, but the carry look-ahead works at asignificantly higher speed.

5)

How does the propagation delay of the 4-bit carry lookahead adder compare to that ofa ripple-carry adder of the same size. Similarly, how does the 16-bit carry lookaheadadder compare to that of a ripple carry adder of the same size.a) The 4-bit carry look-ahead adder the propagation delay is 3 g. The 4-bit ripple

carry adder has a delay of 9 g. For the 16-bit carry look-ahead adder there is adelay of 8 g and for a 16 bit ripple carry adder the delay is upwards of 33 g

because it has upwards of 80 gates lined up in series for the most part. The carrylook-ahead adder has a smaller delay in both instances because it works in a moreefficient manner than the ripple carry adder. This is due to the usage of different

block units strung together to achieve a common goal using parallel circuitryrather than a long string of full adders in series like the ripple carry adder.

Feedback

1. I liked this lab because it was very informative and useful. I liked that the labmanual was like a tutorial with step-by-step instructions. There was nothing that Idisliked.

2. All parts were very clear and informative.3. No need to improve this lab.