BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

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BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises
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Transcript of BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

Page 1: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab Lectures

Preparation for ECEn 320 Lab Exercises

Page 2: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Suggestions for a Productive Lab Experience

•Design– Start early, come to lab prepared.– Understand the assignment before you begin to code VHDL– Design from your drawings-- have your block diagram in front

of you when you write the VHDL– Use good VHDL coding practices. Make your VHDL code

legible.– Comment your code.

•Simulation– Debug using the simulator, not the board– When you ask a TA “What’s wrong with my design?” -- be

prepared to show him a simulation of the current design– Save your simulation stimulus, or use do files. You don’t have

to rebuild the simulation from scratch every time.•Working with the TAs

– Ask proper questions: “My design doesn’t work.” is not a question.

– Don’t expect them to hold your hands, or read to you.– Have the TAs sign your pass-off sheet when you have passed-

off.

Page 3: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 1 : Seven-Segment Display Driver

Displaying a hexadecimal number

Page 4: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Get to Know Your Spartan 3 Board

VGA

Serial

A1 Expansion Connector

PS2

A2 Expansion Connector

B1

Expansio

n

Connecto

rPower

Page 5: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Spartan 3 Board

Page 6: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 1 Specification

VGA

Serial

A1 Expansion Connector

PS2

A2 Expansion Connector

B1

Expansio

n

Connecto

rPower

Display value on 8 switches on the seven-segment display.

Leave top two digits blank.

Page 7: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

7-Segment Display

onSpartan 3

Board

Leave Blank 8-bit Switch Value, in Hexadecimal

Page 8: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Seven-Segment Display

•Seven “segment” input signals (A-G) plus a “decimal-point” input signal (DP) control which segments are lit.– Shared by all four digits

•Four “anode” control input signals control which digit is lit.

Seven-Segment Display Module

Board schematic of the seven-segment display circuit

Page 9: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Seven-Segment Display

•The four anode control inputs are time-multiplexed (asserted at different time intervals, taking turns) to display data on all four characters.

•Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low.

•Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display.

Page 10: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Seven-Segment Display Timing

Note:Anode and Segment

signals are all LOW asserted.Pattern repeats

Page 11: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Seven-Segment Decoder Logic

Note: Segment

signals are LOW asserted.

Switch value (4-bits)

Page 12: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

FPGA Pins - Seven Segment Display

Page 13: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Switches

•When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High.

•When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low.

•The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design. (We will do this in lab 3).

•A 4.7KΩ series resistor provides nominal input protection.

Page 14: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Switches

Page 15: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Clock and Reset Circuits• The board has a dedicated 50 MHz clock oscillator

source.• Use the 50 MHz clock frequency along with the

FPGA’s Digital Clock Managers (DCMs) to create the internal clock.

• The left-most button, BTN3, is the default User Reset pin.

• BTN3 electrically behaves identically to the other push buttons, however is used as a reset by convention.

Page 16: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Advantages of Using the DCM

•DCM = Digital Clock Manager. (Includes the DLL). The Spartan 3 includes four DCMs that you can use.

•Filters the input clock to provide a stable internal clock.

•Guarantees 50% duty cycle internal clock.

•Provides a signal “locked” that tells when clock is stable and operating.

•Can be used to provide other related clocks:– A clock at twice the input clock frequency.– Clocks at divided rates.

Page 17: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Clock and Reset Generator Circuit

clk_in

50 Mhz

Input Clock Divider

rst

24-bitCounter

(50 Mhz, 50% Duty Cycle)

BUFG

IBUFGclkfb

clkin clk0clkbuf

clk0

DLL

clk

clk

clkdiv

A clean clock is very important.

This circuit is the best way to generate a good clean clock in the FPGA.

Never gate the clock.

rst_inClkdiv(23 downto 0)

Reset Synchronizer

set set set set

locked

(internal reset)

Delay Lock Loop inDigital Clock Manager

FPGA Pins Internal

Signals

Page 18: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

System Level Block Diagram

Multiplexer

Seven-Segment Encoder

4 MS bits 4 LS bits

4 bits

ClockGenerator

Clock DivideCounter

clk

Clock Pin 50 MHz

Decoder

blank

digit select

(See question 3.)

Page 19: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 1 Procedure

•Design a circuit to display the 8-bit switch value on the two digits of the seven segment display.– Use the suggested clock/reset generator

circuit.

•Simulate your VHDL file with the Aldec tool.

•Synthesize your design and download your bit file to the board.

•Verify that your circuit works as predicted by simulation.

•Answer the questions.

Page 20: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 1 Questions1. The seven-segment display interface has 12 input pins: 7

segment pins, 1 DP pin, and 4 anode pins. Why does the display manufacturer time-multiplex the display, instead of providing segment and DP pins for each digit ? How many pins did they save ? How many pins would an 8-digit display require if you have anode pins, and how many pins are needed if you don’t have anode pins ?

2. The input frequency to the clock divider is 50 MHz. Make a table of the frequencies of each of the 24 clock divider output bits, clkdiv(23 downto 0) where clkdiv(0) is the LSB and clkdiv(23) is the MSB.

3. If you scan the digits too slow, they will appear to flicker. If you scan the digits too fast, they will be dim. What bits of the clock divider did you decode to drive the anodes of the seven-segment display ? What is the corresponding scanning frequency ? How did you decide what clock divider bits to use ?

4. When a switch is in the high position, what is the resistance between VCCO power and the FPGA input pin ? What is the resistance between Ground and the FPGA input pin when the switch is in the low position ?

5. The reset synchronizer circuit given here guarantees that the internal reset is on at least how many clock cycles ? Does the circuit guarantee that internal reset signal rises and falls synchronous to the clock ?

Page 21: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 1 Objectives

•Learn to use the Aldec simulation tool.•Learn to use the Xilinx synthesis and implementation tools.

•Design a working VHDL circuit.•Learn how to properly generate a clock and reset

•Learn how to properly divide a clock•Learn how to properly drive the seven-segment display.

•Learn how to download your design to the board.

Page 22: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2 : UART

Transmitting and Receiving Serial Data

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BYU ECEn 320

The ABC’s of Serial Ports•UART = Universal Asynchronous

Receiver/Transmitter•TX = Transmitter•RX = Receiver•TD = Transmit Data (Data output)•RD = Receive Data (Data input)•RTS = Request to Send (Flow control output)•CTS = Clear to Send (Flow control input)•Half Duplex – transmits one direction at a time

(mostly obsolete now)•Full Duplex – transmits both directions at the

same time•RTS/CTS Flow control for full duplex serial ports :

– RX assert RTS when it is ready to receive– TX waits for CTS before transmitting

Page 24: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Serial Port Devices

The following is a list of various hardware components that use Serial Ports :

•Mouse - One of the most commonly used devices for serial ports.

•Modem - Used commonly with older computers.

•Network - One of the original uses of the serial port, which allowed two computers to connect together and transfer large files between the two.

•Printer - Mostly used with older printers only.

•ASCII Terminal (TTY) - Like the Hyperterm interface.

Page 25: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Hooking Up Two Serial Ports

TD

RD

RTS

CTS

GND

TD

RD

RTS

CTS

GND

Full Duplex

Page 26: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

RTS

CTS

RXD

TXD

DTR

DSRDCD

RI

Serial Porton

Spartan 3 Board

Page 27: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Serial Communication Format•Data is transmitted sequentially, one bit at a time.•To inform the receiver that a new byte is arriving,

a “start bit” (a zero) is sent first. A start bit can start at any time.

•Then the data is transmitted, LSB (least significant bit) first, and MSB (most significant bit) last.

•At the end, one or two “stop bits” (ones) are transmitted.

•A frame consist of :– 1 start bit (a zero)– 7 or 8 data bits LSB (least significant bit) first– 1 optional parity bit– 1 or 2 stop bits (ones)

•Between transmissions, the transmitter transmits a high.

•The bit time is determined by the baud rate which is given in units of BPS (bits per second).

•Transmitter and receiver do not share a clock (hence the asynchronous nature).

Page 28: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Serial Frame

http://www.atmel.com/dyn/resources/prod_documents/DOC0941.PDF

http://www.wcscnet.com/Tutorials/SerialComm/Page1.htm

Page 29: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitting

Page 30: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Receiving

1.5 bit time

1.5 bit time

Page 31: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Receiver Sample Timing

1.5Bit

Time

1BitTi

me

Exact Baud Rate

Slightly Slower Baud Rate

Slightly Faster Baud Rate

Page 32: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 1UART Transmitter

Page 33: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 1 Specification

VGA

Serial

A1 Expansion Connector

PS2

A2 Expansion Connector

B1

Expansio

n

Connecto

rPower

Send ASCII value on 8 toggle switches to serial port for display on screen when

button 1 is pressed.

Page 34: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Top Level System Block Diagram

Clock/Reset Generator

Switch and Button InterfaceButton Debouncer

tx_test

txTransmitter

Two Entities:

tx_test - top level file to test the transmitter

tx - The transmitter itself, which is instantiated in the body of tx_test

You will need the transmitter (tx) for Part 3. of this lab.

Page 35: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter Tester (tx_test)Block Diagram

tx8

data_in

serial_out

clk (50 MHz)

rst

tx_complete

send_character

ctsn

Debounce Circuit

Clock/Reset Generator

(open, or LED)

button

switch(7 downto 0)

txd

clk_in

Page 36: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Clock and Reset Generator Circuit

clk_in50 Mhz

rst

(50 Mhz, 50% Duty Cycle)

BUFG

IBUFGclkfb

clkin clk0clkbuf

clk0

DLL

clk

clk

No external reset button, ‘rst’ is internally generated.

Reset Synchronizer

set set set set

locked

(internal reset)

Delay Lock Loop inDigital Clock Manager

FPGA Pins Internal

Signals

Page 37: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter (tx) Block Diagram

FSM

SerialGenerator

BitCounter

BitTimer

8data_in serial_out

clk

rst

clrTimer

tx_bit

bit7

clrCount

startBitstopBit

3 bit_sel

incCount

clk

rst

clk

rst

clk

rsttx_complete

send_character

ctsn

Page 38: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Bit Timer - Transmitter Clocking

•Everything is clocked on same global clock (clk)

•Global clock is 50MHz•The Bit Timer controls the timing of bits coming out of the serial port.

•Bit Timer needs to create timing pulse at rate of 19,200Hz– That is the baud rate of our serial port– Divide factor = 50,000,000/19,200 =

2604.1666…– We will use 2604 cycles/pulse

Page 39: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter Bit Timer•Is a counter

– Can be cleared, otherwise increments up to 2603 and rolls over

– Signal tx_bit is asserted when it reaches 2603

clktx_bit

state

serial_out

2604 cycles

“one bit”

Page 40: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Hints for Creating the Bit Timer

signal timer : std_logic_vector(11 downto 0);signal tx_bit : std_logic;

process(clk)begin -- create bit timer counter -- clrTimer and rst are synchronous clears -- wraps to 0 after counting to 2603 (A2B hex)end process;

-- combinational

tx_bit <= ‘1’ when timer = X”A2B” else ‘0’;

2603 (decimal) = A2B (hex) = 101000101011 (binary)

Page 41: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter Bit Counter•Is a counter

– cleared synchronously with clr_count– incremented with inc_count– counts from 0 to 7 and then wraps to 0

•It counts how many bits have been transmitted– The count is a 3-bit bit_sel output that

selects which data bit is to be sent next.

– bit7 tells FSM when its current count=7(Means the last bit is being transmitted)

Page 42: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Serial Generator•Outputs a ‘0’ when startBit is high•Outputs a ‘1’ when stopBit is high•Outputs selected data bit fromdata_in otherwise

•Output of combination logic should be registered using a flip-flop to ensure clean serial_out signal– The Flip-Flop will remove any transient glitchs.– IFL + register design (MUX + gates + FF)– Synthesizer will infer synchronous set/clear on

FF from startBit and stopBit if possible

CombinationalLogic

Page 43: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter FSM•FSM handshakes with outside world

send_character

tx_complete

data_in

Data transmission here…

serial_out …

Start bit Stop bit

Page 44: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter FSM•Controls start/stop bits to Serial Generator

•Controls clearing/increment of Bit Counter

•Controls clearing of Bit Timer

•Reacts to Bit Counter and Bit Timer

Page 45: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Transmitter FSM

RUN

START

RETRN

send_character • ctsn

tx_bit

send_character + ctsn

tx_bit

stopBittx_complete

IDLE

stopBitclrCountclrTimer

startBit

tx_bit

tx_bit • bit7 / incCount

tx_bit • bit7

send_character

send_character

STOP

stopBit

tx_bit

tx_bit

We will give you the state machine for this

lab, for the next lab you will design your own!

rst

Page 46: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Output Glitching•Signal serial_out should be clean (not

glitch)– If it is register output – it will be clean (in tx serial

generator)

•Signal tx_complete should also be clean– Run it through flip flop after it leaves FSM (in tx)

•Signal send_character should be clean– Filter the push button through a “button debouncer”

(in tx_test)

•What about other signals… ?– Since they drive other circuitry in the same clock

domain: don’t care

Page 47: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Button Debounce Circuit

DebounceLogic

A digital equivalent of a low pass filter

switch settle time

switch settle time

button settle time is typically

around 10 msec

button

input

output

Page 48: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Debounce Circuit

Tsample > Tsettle

D Qbouncy debounced

en

Timer/Clock Divider

Tsettle

Tsamplebouncy

debounced

clk

clk

en_sample

en_sample

Page 49: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

•Create file tx.vhd with all its ports and internal signals– Use port names from drawing – other circuitry expects these

names

•Design Bit Timer as a process in it– Simulate it– Then, simulate everything else with it having MUCH SMALLER

terminal count (how about 4 instead of 2604?)

•Add Bit Counter process– Simulate everything so far

•Add Serial Generator process– Simulate everything so far

•Add FSM processes– Simulate entire circuit

•Don’t forget to change timer terminal count back before synthesizing…

Suggested Incremental Design Process

Page 50: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Three Testing Options

•Add Aldec simulators to your inputs– Create a simulator for each input using “Add

Simulator” in Aldec– Like you learned in the tutorial

•Write a ‘do’ file– Create a file containing simulator commands such as

force statements using the simulator’s script language– Run this script to run your simulation– Dr. Nelson’s favorite method

•Write a test bench– Create a test bench entity (no inputs or outputs)– Write VHDL in the test bench architecture to drive

your unit-under-test (UUT)

UUT

TestBench

VHDL

Page 51: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 1 Procedure

• Code the transmitter (tx) from the specification (the lab notes) and block diagram.

• Simulate the transmitter• Build the hardware test

environment (tx_test) for the transmitter (tx)

• Synthesize, download, and test the system (tx_test) on the board

You Will:

Page 52: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 1 Objectives

• Design starting from a specification and block diagram

• Properly clock something at a fraction of the clock speed (tx_bit)

• Code a state machine, counter, and multiplexer in VHDL

• Instance one entity (tx) inside another (tx_test)

• Debug using simulation

You will learn how to . . .

Page 53: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2 Part 1 Questions

•At 19200 baud, how many characters per second can be transmitted? (For all questions, assume 8 data bits, no parity, and one stop bit.)

•At 19200 baud, what is the bit time (length of time each bit is transmitted)?

•What percent of transmission time is overhead (time of the start and stop bits divided by the total frame time)?

•Suppose a file of 10,000 bytes is to be sent over a line at 19200 bps. How much time will it take? (In seconds)

•For the bit and timer counters, why is it important for the clears to be synchronous clears (instead of asynchronous clears)?

Page 54: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Part 2 : UART Receiver

Page 55: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

For This Lab

•Design the receiver like the transmitter– Block Diagrams– FSM + counters– Need to count a half-bit position to get into

middle of bit

•You will need a shift register– Code as shown in VHDL class lecture notes

Page 56: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 2 Specification

VGA

Serial

A1 Expansion Connector

PS2

A2 Expansion Connector

B1

Expansio

n

Connecto

rPower

Keyboard character is displayed on seven segment display when key is pressed.

Page 57: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Receiver Bit Timer• Is a counter

– Can be cleared, otherwise increments up to 2603 and rolls over

– Signal rx_bit is asserted when it reaches 2603– Signal rx_half_bit is asserted when it reaches ???? (You

choose).clk

rx_bit

state

serial_in

2604 cycles

“one bit”

rx_half_bit

“start”

exactly 1.5 bit time = 3906 cycles

clrTimer

Page 58: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Break

•A long low time on the serial_in line.•If there is not a stop bit (high) where you expect one, your receiver should ignore the preceding byte and wait until the serial_in line goes high before proceeding.

Start bit Stop bitexpected

here

ignore char wait for high

Page 59: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 2 Objectives

• Design starting from a specification and block diagram

• Properly clock something at a fraction of the clock speed (tx_bit)

• Code a state machine, counter, and multiplexer in VHDL

• Instance one entity (tx) inside another (tx_test)

• Debug using simulation

You will learn how to . . .

Page 60: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2 Part 2 Questions

•At 19200 baud (ignoring rise and fall times) how much variation in the baud rate can be tolerated by the receiver?(X %, Y %)

•Why is it bad to use an output of an FSM to drive an asynchronous clear to a counter.

•Explain how glitches are created in combinational logic (such as the output forming logic of an FSM), and how a flip-flop can filter out these glitches.

Page 61: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Part 3 : Full UART

Page 62: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 3 Specification

VGA

Serial

A1 Expansion Connector

PS2

A2 Expansion Connector

B1

Expansio

n

Connecto

rPower

Keyboard character is displayed on screen when key is pressed.

Page 63: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

FIFO - First In First Out Buffer

•Store bytes (8-bit chunks) of data.•Bytes come out in the same order that they go in.

•Can store up to 16 bytes in the buffer.•Writing the FIFO puts a byte in the buffer.•Reading the FIFO takes a byte out of the buffer.

bbfifo_16x8

Page 64: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

bbfifo16x8Inputs and Outputs

Data_in

Write

Full

Half_Full

Data_out

Read

Data_present

Clk

Reset

txrx

bbfifo_16x8

This FIFO stores data that has been received,but has not yet been transmitted.

rxd

txd

Page 65: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

FIFO Inputs/Outputs• Clk (input)• Reset (input) An active HIGH input causes the 16-byte internal buffer to be

reset; hence, all data currently in the buffer is lost. The buffers are initialized to an empty state following power-up. Therefore, this signal is not used (and is therefore tied LOW) in most cases.

• Data_in(7-0) (input) This is the data input to the buffer, which should be stable during an active WRITE clock cycle.

• Full (output) This signal becomes active HIGH when the 16-byte buffer is full. For the writer, it means that WRITE should not be applied until a READ creates a space in the buffer (BUFFER_FULL returns LOW). Any attempt to write data to a full buffer are simply ignored.

• Half_full (output) This signal becomes active HIGH when the 16-byte buffer is half full.

• Write (input) An active HIGH input indicates that the data currently being applied to the DATA_IN[7:0] port is written to the buffer on the next rising clock edge. Note that write operations take place on every rising edge when this signal is active HIGH. Hence, this signal should be pulsed HIGH for one cycle only, unless new data is applied to DATA_IN[7:0] every clock cycle for a “burst write.”Note: The data is not stored if the BUFFER_FULL signal is active HIGH.

• Data_out(7-0) (output) This is the data output from the buffer. This data is valid when DATA_PRESENT is active HIGH, and is the current byte being read.

• Data_Present (output) This signal is active HIGH when the buffer contains one or more bytes of data. It also signifies that DATA_OUT[7:0] is valid data.

• Read (input) An active HIGH input indicates that the data currently being provided at the DATA_OUT[7:0] port has been read (or will be read on the next rising clock edge) and that the next available data can be made available. The READ input can be applied for consecutive clock cycles to perform a “burst” of data. An attempt to READ without DATA_PRESENT being asserted has no effect.

Page 66: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

FIFO Write

DATA_PRESENT

Page 67: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

FIFO Read

Single read Burst read of 5 bytes

Page 68: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Changes to the Transmitter FSM

•FSM handshakes with outside world (revised)

•This new handshake make the transmitter easier to adapt to the FIFO

send_character

tx_complete

data_in

Data transmission here…

serial_out …

Start bit Stop bit

single cycle pulse

Page 69: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 2, Part 3 Objectives

• Structurally design a higher level circuit, using blocks that have previously been developed.

• Be able to use an existing block developed by someone else, by reading a specification of its inputs, outputs, and timing.

• Pay attention to synthesizer warnings.

You will learn how to . . .

Page 70: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 3The Xilinx PicoBlaze

Microcontroller

Page 71: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

PicoBlaze Architecture Features• Program memory = 1024 18-bit instructions• Register file = 16 8-bit general-purpose

registers• Flags = Zero and Carry• Scratch-pad Memory = 64 8-bit locations• Call/Return Stack = 31 entries deep• I/O port = 8-bit data, 8-bit address• Timing = 2 clock cycles per

instruction• Interrupt Response = 5 clock cycles

Page 72: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Microcontroller Vs. LogicCoDesign Tradeoffs

Page 73: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

The PicoBlaze

Most of the following slide images were taken from

PicoBlaze User’s Manual – there is a link to that from Lab

3’s WWW page

Page 74: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

PicoBlaze + Program Memory

CLK

Page 75: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Reset

Clock

Page 76: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

VHDL - Declarations

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BYU ECEn 320

VHDL - Instantiations

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BYU ECEn 320

Instruction Set Summary

•Bitwise Logical: AND, OR, XOR, TEST•Arithmetic: ADD, SUB, COMPARE•Shift and Rotate: RL, RR, SLx, SRx, SRA

•Data Movement: LOAD, FETCH, STORE, IN, OUT

•Jump and Branch: JUMP, JUMP Z, JUMP NZ

•Subroutine: CALL, RETURN, RETURN Z, RETURN NZ

•Interrupt: ENABLE, DISABLE, RETURNI

Page 79: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Bitwise Logical Instructions

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BYU ECEn 320

Arithmetic Instructions

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BYU ECEn 320

Shift and Rotate Instructions

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BYU ECEn 320

Shift and Rotate Instructions

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BYU ECEn 320

Data Movement Instructions

(Constants)

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BYU ECEn 320

Data Movement Instructions

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BYU ECEn 320

Program Control Instructions

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BYU ECEn 320

Jump Instructions

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BYU ECEn 320

Call Instructions

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BYU ECEn 320

Interrupt Control Instructions

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BYU ECEn 320

Input Port

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BYU ECEn 320

Input Port Decoding

IN_PORT[7:0] OUT_PORT[7:0]OUT_PORT[7:0]

PORT_ID[7:0]

READ_STROBE

WRITE_STROBE

MUX selects which device’s signals are fed

into IN_PORT

Inpu

t D

evic

es

READ_STROBE can be used to indicate that something has been

read…

Page 91: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Use of READ_STROBE

•Some devices don’t care when you read them…– Switches– No need to even look at READ_STROBE

•Some devices do care when you read them…– FIFO– Use READ_STROBE to indicate when a data

value has been consumed so it can be removed

Page 92: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Faster Input Decoding

IN_PORT[7:0] OUT_PORT[7:0]OUT_PORT[7:0]

PORT_ID[7:0]

READ_STROBE

WRITE_STROBE

Since PORT_ID is valid for 2 cycles, can add

flip flop to reduce critical path…

Inpu

t D

evic

es D Q

Page 93: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Output Port

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BYU ECEn 320

Decode Pipelining Improves Performance

(optional)

(optional)

Page 95: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Assembler

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BYU ECEn 320

Assembler Directives

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BYU ECEn 320

A PicoBlaze Skeleton Program

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BYU ECEn 320

Lab 3 - Board Controller

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BYU ECEn 320

A Two-Part Lab

•Part 1 of the lab consists of adding devices and doing some simple programming

•Part 2 consists of extending hardware and doing a complete application

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BYU ECEn 320

Part 1 Description & Specification

•Spartan 3 board is connected to a serial channel on the computer, which is running a hyper-terminal program.

•When a character is typed on the keyboard, it is echoed back to the screen

•The ASCII value of the last character typed is displayed on the LEDs.

•The previous two characters are displayed on the seven segment display.

Next Prev PrevChar Char

EchoLastChar

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BYU ECEn 320

Part 2 Description

•Spartan 3 board is connected to a serial channel on the computer, which is running a hyper-terminal program.

•The 8-bit value on the 8 toggle-switches on the board is displayed as 2-hex digits on the terminal.

•A 4-hex digit value typed on row 3 of the screen is also displayed on the seven-segment display on the board.

•This value can then be incremented, decremented, and cleared using push-buttons.

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BYU ECEn 320

Screen Specification – Part 2

1. A title of your choice

2. The HEX value of the switches

3. The value shown on the 7-segment display.

a. Incremented with button 0

b. Decremented with button 1

c. Reset with button 3

Page 103: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Screen Specification

IncrementDecrementReset

Other button and LEDs are for your use (debugging)

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BYU ECEn 320

Lab 3 Hardware

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BYU ECEn 320

Block Diagram

FIFO

FIFO Tx

Rx

UART Status

Segment Reg

Switch Reg

Button Reg

LED Reg

0

1

2 (lo)3 (hi)

0

4

5

6

(Ports)

CodeBlock RAM

high

low

Page 106: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Segment Register – Part 1

•Two bytes, Read/Write•What ever is in segment register is displayed on seven-segment display

LED Register – Part 1

• 8-bits Read/Write• Used for debugging (you can display

anything you want on the LEDs)• Each bit of the register is tied to an LED

Page 107: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Switch Register - Part 2

•Need not be debounced•8-bits, Read only•The switch value goes to the port multiplexer

3.3V

0V

switch_reg(to port input multiplexer)

Page 108: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Button Register – Part 2

•Needs to be debounced•4 bits for 4 buttons, upper 4 bits are 0’s

•Read/Write•A bit is set when the button is pushed (rising edge of button)

•A bit is reset when a 1 is written to that bit (You only clear the buttons you caught-- makes sure no buttons are missed).input s0, button_reg ; read buttonsoutput s0, button_reg ; reset buttons that were caughttest s0, 01 ; test bit 0 (button 1)jump NZ, do_button1 ; jump if button1 was set

Page 109: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Button Register – Part 2

3.3V

0V

button_reg(to port_in multiplexer)

EdgeDetect

set

reset write_stro

be

DebounceLogic

port_out

port_id=5

button_regreset

set on button push

button

k

k

Bit in button register is set when the

button is pushed (rising edge of

button)

Reset when a ‘ 1 ’ is written to that bit in the button register

button

clk

Sync SR

Page 110: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Debounce Circuit

DebounceLogic

A digital equivalent of a low pass filter

switch settle time

switch settle time

switch settle time is typically

around 10 msec

input

output

Page 111: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Debounce Circuit

Tsample > Tsettle

D Qbouncy debounced

en

Timer/Clock Divider

Tsettle

Tsamplebouncy

debounced

clk

clk

en_sample

en_sample

EdgeDetect

Page 112: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Edge Detector

D Qin

clk

rising_edge

in

clk

rising_edge

Page 113: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Synchronous Set-Reset Flip Flop

Set Rst Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 ? 1 1 1 ?

D QC/LSet

Rst

Clk

D QSet

Rst

Clk

D QSet

Rst

Clk

Set Override Sync SR ff

Reset Override Sync SR ff

Q

Q

mem

rst

set

setandrst

Flip-Flop Excitation Table

Note: Use bitwise AND, OR, and NOT operators to do SR registers

Page 114: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 3 Software

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BYU ECEn 320

PicoBlaze Code Hints

compare s0, s1jump Z, label

compare s0, s1jump NZ, label

compare s0, s1jump NC, label

compare s0, s1jump C, label

10 if Jump ; ss

10 if Jump ; ss

10 if Jump ; ss

10 if Jump ; ss

call Z, labelcall NZ, labelcall NC, labelcall C, label

if Call ; if Call ; if Call ; if Call ;

return Zreturn NZreturn NCreturn C

if Return; if Return; if Return; if Return;

Arithmetic

Comparisons

Conditional Jumps, Calls, and Returns

Page 116: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

PicoBlaze Code Hintsload s0, constantoutput s0, reg1

input s0, reg1output s0, reg2

add s0, 01addcy s1, 00

sub s0, 01subcy s1, 00

Register Input/Out

put

constant reg1 ;

reg1 reg2 ;

1 s0][s1, s0] [s1, ;

1 s0][s1, s0] [s1, ;

Multi-byte Arithmeti

csr0 s0sr0 s0sr0 s0sr0 s0

sl0 s0sl0 s0sl0 s0sl0 s0

4 s0 s0 ;

4 s0 s0 ; Logical

Right and Left Shifts

Page 117: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Polling

The processor loops and repetitively checks each device to see if it has a request.

Check 1

Check 2

Check 3

ServiceDevice 1

ServiceDevice 2

ServiceDevice 3

Main polling

loop

Page 118: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

The Board Controller Program

CheckButtons

CheckUART

do_buttons

do_switch

do_cmd

Initialize

CheckSwitches

Main polling

loop

put_seg

put_hex

gotoXY

Global Variable:segpos

Support Routines

Converts a binary value to a hex character and prints it on the screen

Move the cursor on the screen to position row X, column YPrints the 4-hex digit value in segHi_reg and segLo_reg on the screen starting at row 3, col 1.

The current cursor col position on row 3Global Variable:

switch

The last value read from the switches

Provided for youYou need to write

Page 119: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Initialization Code

•Go to Home position and clear entire screen

•Print Title•Initialize segment position = ‘1’ (column 1)

•Print Switches•Initialize segment register (high and low) = 0000

•Print Segment Register•Put cursor at beginning of segment value on screen (row 3, column 1)

•Initialize LED Register to 00

Page 120: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

ANSI Terminal Commands

CommandCharacter Sequence

Up Arrow Esc [ A

Down Arrow Esc [ B

Right Arrow Esc [ C

Left Arrow Esc [ D

Go Home Esc [ H

Clear Screen Esc [ J

Go to row, column

Esc [ row ; column H

Note: Windows sends three bytes of zeros following all commands. They should be ignored.

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BYU ECEn 320

Subroutine do_button

•Read the button register•Write back same value to button register to clear the buttons

•Test for button 1 (increment)– Increment segment register– Transmit new segment register value to

terminal (call subroutine put_seg)

•Test for button 2 (decrement)– Decrement segment register– Transmit new segment register value to

terminal (call subroutine put_seg)

•Test for button 4 (reset)– Jump to start of program

Page 122: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Subroutine do_switch

•Read switch register•Move cursor to row ‘2’, column ‘1’ (call subroutine gotoXY)

•Save in last switch value (internal register)

•Convert upper 4-bits to hex character and send to transmitter (call subroutine put_hex)

•Convert lower 4-bits to hex character and send to transmitter (call subroutine put_hex)

•Move cursor to row ‘3’, column segpos (call subroutine gotoXY)

Page 123: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Subroutine do_cmd

•Read a character from serial port•If character is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,a,b,c,d,e, or f– Echo character back out transmitter– Convert character from ascii to 4-bit binary– Insert those 4-bits into the segment register

•segpos = ‘1’, Insert into upper 4 bits of high byte•segpos = ‘2’, Insert into lower 4-bits of high byte•segpos = ‘3’, Insert into upper 4-bits of low byte•segpos = ‘4’, Insert into lower 4-bits of low byte

– Move segpos to the next position. (‘4’ wraps back to ‘1’)

•If character is escape, handle arrow keys (optional)

•Ignore other characters

Page 124: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Subroutine put_hexConverts a binary value to a hex character and

prints it on the screen.•Convert 4-bit binary value to hexadecimal value•Send to UART transmitter

Subroutine gotoXYMove the cursor on the screen to position row X, column Y

• Send escape to UART transmitter• Send [ to UART transmitter• Send row to UART transmitter• Send ; to UART transmitter• Send column to UART transmitter• Send H to UART transmitter

Page 125: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Subroutine put_segPrints the 4-hex digit value in (segHi_reg, segLo_reg) on

the screen starting at row 3, column 1.

•Move cursor to row ‘3’, column ‘1’ (call subroutine gotoXY)

•Convert upper 4-bits of high byte of segment register to hex and transmit (call subroutine put_hex)

•Convert lower 4-bits of high byte of segment register to hex and transmit (call subroutine put_hex)

•Convert upper 4-bits of low byte of segment register to hex and transmit (call subroutine put_hex)

•Convert lower 4-bits of low byte of segment register to hex and transmit (call subroutine put_hex)

•Move cursor to row ‘3’, column segpos (call subroutine gotoXY)

Page 126: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 3 Procedure

•You are provided– A specification– Sample VHDL and code files showing how to

use a PicoBlaze.– PicoBlaze source VHDL files.

•You have to– Design the registers and decoding logic in

VHDL– Write PicoBlaze code to implement the

specification– Simulate your VHDL model– Test and demonstrate

Page 127: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 3 Objectives

In this lab you will learn how to :

•Design using a PicoBlaze soft processor

•Interface logic to the PicoBlaze•Program the PicoBlaze•Make simple codesign tradeoffs

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BYU ECEn 320

Lab 4 : Multiplication

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BYU ECEn 320

Table-Lookup Multipliers

•How big of a ROM does it take to multiply two n-bit numbers?

ROM

n-bit n-bit

2n-bit 4608K9

1024K8

224K7

48K6

10K5

2K4

3843

642

Size(bits)

222 : ROM of Size

2 :location per bits ofNumber

2 :locations address ofNumber

122

2

n

nn

nnn

n

A block RAM in

the Spartan 3 is 16-18K bits(depend

ingon how

youcode it)

Page 130: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

n ROM Size2 83 324 965 2566 6407 15368 35849 819210 18432

Lookup-Table Squarers

•How big of a ROM does it take to square an n-bit number?

ROM

n-bit

2n-bit

Improved

ROM

(n-1)-bit

(2n-2)-bit

lsb

0 lsb

n bits

A block RAM in

the Spartan 3 is 16-18K bits(depend

ingon how

youcode it)

2n-2 bits

Why 2n-2 output bits in improved ROM?

Number of locations: 2n

Bits/location = 2n-2Total ROM size = 2n x (2n-2) bits

Page 131: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Multiplying by Squaring

22

4

1yxyxxy

ROM

n-bit

2n-bit

lsb

0 lsb

+ -

ROM

n-bit

2n-bit

lsb

0 lsb

-

2n-bit

n-bitn-bit

x y

xy

(n+1) bits (n+1)-bits

64 Block RAMS vs.2 Block RAM + 3

Adders

(2n) bits (2n) bits

n Mul ROM Sqr ROM2 64 2 x 323 384 2 x 964 2K 2 x 2565 10K 2 x 6406 48K 2 x 15367 224K 2 x 35848 1024K 2 x 8K9 4608K 2 x 18K

+3 adders

Page 132: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

8-Bit x 8-Bit Multiply

22

4

1yxyxxy

ROM

9-bitsigned

16-bitpositive

+ -

ROM

-

16-bit Signed

8-bitsigned

8-bitsigned

x y

xy

9-bits 9-bits

16-bits 16-bits

9-bitsigned

16-bitpositive

2

4

1yx 2

4

1yx

yx yx

In your application, you will be multiplying two 8-bit signed numbers to get a 16-bit signed result.

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BYU ECEn 320

Squaring ROM

•Write code which will be inferred as a ROM (BlockRAM)– Input (address) is 9 bits wide– Output is 16 bits wide– Uses just half of the BlockRAM– It is big enough that writing a C or Java program to

generate design is a good idea– Must handle signed inputs…

•Same ROM is structurally placed twice in multiply.vhd file– Surrounding logic interfaces it to rest of system– Multiply two 8-bit values, return 16-bit result

Page 134: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Squaring ROM A A2 A2/4 ROM addr (A) ROM Output (A2/4)

0 0 0 0 0000 0000 0000 0000 0000 0000 1 1 0 0 0000 0001 0000 0000 0000 0000 2 4 1 0 0000 0010 0000 0000 0000 0001 3 9 2 0 0000 0011 0000 0000 0000 0010 4 16 4 0 0000 0100 0000 0000 0000 0100 ... ... ... 254 64516 16129 0 1111 1110 0011 1111 0000 0001 255 65025 16256 0 1111 1111 0011 1111 1000 0000-256 65536 16384 1 0000 0000 0100 0000 0000 0000-255 65025 16256 1 0000 0001 0011 1111 1000 0000-254 64516 16129 1 0000 0010 0011 1111 0000 0001 ... ... ... -4 16 4 1 1111 1100 0000 0000 0000 0100 -3 9 2 1 1111 1101 0000 0000 0000 0010 -2 4 1 1 1111 1110 0000 0000 0000 0001 -1 1 0 1 1111 1111 0000 0000 0000 0000

9-bits 16-bits

Page 135: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Squaring ROM

#include <stdio.h>

main() int i; for (i=0; i<256; i++) printf("%04x ", ((i*i)/4)&0xffff); if (i%16==15) printf("\n"); for (i=-256; i<0; i++) printf("%04x ", ((i*i)/4)&0xffff); if (i%16==-1) printf("\n"); return 0;

This ROM is large enough that a small C-program (or any other language) would probably be useful to generate the ROM contents.

Output is on next page.

You can use or modify this program to fit your needs.

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BYU ECEn 320

0000 0000 0001 0002 0004 0006 0009 000c 0010 0014 0019 001e 0024 002a 0031 00380040 0048 0051 005a 0064 006e 0079 0084 0090 009c 00a9 00b6 00c4 00d2 00e1 00f00100 0110 0121 0132 0144 0156 0169 017c 0190 01a4 01b9 01ce 01e4 01fa 0211 02280240 0258 0271 028a 02a4 02be 02d9 02f4 0310 032c 0349 0366 0384 03a2 03c1 03e00400 0420 0441 0462 0484 04a6 04c9 04ec 0510 0534 0559 057e 05a4 05ca 05f1 06180640 0668 0691 06ba 06e4 070e 0739 0764 0790 07bc 07e9 0816 0844 0872 08a1 08d00900 0930 0961 0992 09c4 09f6 0a29 0a5c 0a90 0ac4 0af9 0b2e 0b64 0b9a 0bd1 0c080c40 0c78 0cb1 0cea 0d24 0d5e 0d99 0dd4 0e10 0e4c 0e89 0ec6 0f04 0f42 0f81 0fc01000 1040 1081 10c2 1104 1146 1189 11cc 1210 1254 1299 12de 1324 136a 13b1 13f81440 1488 14d1 151a 1564 15ae 15f9 1644 1690 16dc 1729 1776 17c4 1812 1861 18b01900 1950 19a1 19f2 1a44 1a96 1ae9 1b3c 1b90 1be4 1c39 1c8e 1ce4 1d3a 1d91 1de81e40 1e98 1ef1 1f4a 1fa4 1ffe 2059 20b4 2110 216c 21c9 2226 2284 22e2 2341 23a02400 2460 24c1 2522 2584 25e6 2649 26ac 2710 2774 27d9 283e 28a4 290a 2971 29d82a40 2aa8 2b11 2b7a 2be4 2c4e 2cb9 2d24 2d90 2dfc 2e69 2ed6 2f44 2fb2 3021 30903100 3170 31e1 3252 32c4 3336 33a9 341c 3490 3504 3579 35ee 3664 36da 3751 37c83840 38b8 3931 39aa 3a24 3a9e 3b19 3b94 3c10 3c8c 3d09 3d86 3e04 3e82 3f01 3f804000 3f80 3f01 3e82 3e04 3d86 3d09 3c8c 3c10 3b94 3b19 3a9e 3a24 39aa 3931 38b83840 37c8 3751 36da 3664 35ee 3579 3504 3490 341c 33a9 3336 32c4 3252 31e1 31703100 3090 3021 2fb2 2f44 2ed6 2e69 2dfc 2d90 2d24 2cb9 2c4e 2be4 2b7a 2b11 2aa82a40 29d8 2971 290a 28a4 283e 27d9 2774 2710 26ac 2649 25e6 2584 2522 24c1 24602400 23a0 2341 22e2 2284 2226 21c9 216c 2110 20b4 2059 1ffe 1fa4 1f4a 1ef1 1e981e40 1de8 1d91 1d3a 1ce4 1c8e 1c39 1be4 1b90 1b3c 1ae9 1a96 1a44 19f2 19a1 19501900 18b0 1861 1812 17c4 1776 1729 16dc 1690 1644 15f9 15ae 1564 151a 14d1 14881440 13f8 13b1 136a 1324 12de 1299 1254 1210 11cc 1189 1146 1104 10c2 1081 10401000 0fc0 0f81 0f42 0f04 0ec6 0e89 0e4c 0e10 0dd4 0d99 0d5e 0d24 0cea 0cb1 0c780c40 0c08 0bd1 0b9a 0b64 0b2e 0af9 0ac4 0a90 0a5c 0a29 09f6 09c4 0992 0961 09300900 08d0 08a1 0872 0844 0816 07e9 07bc 0790 0764 0739 070e 06e4 06ba 0691 06680640 0618 05f1 05ca 05a4 057e 0559 0534 0510 04ec 04c9 04a6 0484 0462 0441 04200400 03e0 03c1 03a2 0384 0366 0349 032c 0310 02f4 02d9 02be 02a4 028a 0271 02580240 0228 0211 01fa 01e4 01ce 01b9 01a4 0190 017c 0169 0156 0144 0132 0121 01100100 00f0 00e1 00d2 00c4 00b6 00a9 009c 0090 0084 0079 006e 0064 005a 0051 00480040 0038 0031 002a 0024 001e 0019 0014 0010 000c 0009 0006 0004 0002 0001 0000

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BYU ECEn 320

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BYU ECEn 320

Multiplier.vhd

ROMMultiplier

8-bit

8-bit

8-bit

8-bit

Multiplier TimingStart Done

16-bit

Load

Page 139: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Block Diagram

FIFO

FIFO Tx

Rx

UART Status

Operand 1 Reg

Operand 2 Reg

Result Reg

LED Reg

0

1

2 (lo)3 (hi)

0

6

(Ports)

CodeBlock RAM

4 (lo)5 (hi)

2 (lo)3 (hi)

Multiplier

done

start

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Lab 4 Procedure

•You are provided– A specification– PicoBlaze code to help you simulate your

multiplier.– Final PicoBlaze code to test your multiplier

(you should not have to modify the code... unless you want to).

•You have to– Design a ROM-based multiplier (signed 8-bit x

8-bit = 16-bit).– Interface your multiplier to the PicoBlaze.– Simulate your design– Synthesize, download, and test

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Lab 5 - Real Time Clock Interface

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Specification

In this lab, you will build an alarm clock. The things your clock should able to perform are:

1: Continuously display the current time.2: Set the time on the clock3: Set the alarm time on the clock4: Set a non-volatile value (the clock chip has non- volatile memory on it).5: Get the non-volatile value from off the chip. 6: When the alarm goes off, something interesting should happen. You should be able to turn off the alarm.

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Objectives

We will be using aDallas SemiconductorDS1687-3Real Time Clock (RTC) chip.

The objectives of the lab are to learn how to:• Interface an FPGA to an external chip• Read data sheets• Design your own user interface• Handle interrupts

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BYU ECEn 320

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The Real-Time Clock Interface

RTC

ALE

RD

WR

CS

AD

Time-multiplexed Address/Data

8

Interface to RTC by reading and writing

internal registers

IRQ

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Address/Data Time-Multiplexing

Multiplexed buses save pins because address information and data information time-share the same signal paths.

The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle.

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AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) –

• Addresses must be valid prior to the latter portion of ALE, at which time the DS1685/DS1687 latches the address.

• In a write cycle, valid write data must be present and held stable during the latter portion of the WR pulse.

• In a read cycle, the DS1685/DS1687 outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions high.

RTC Pins

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ALE (RTC Address-Strobe Input; Active High) – A pulse on the address strobe pin serves to demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the DS1685/DS1687.

RD (RTC Read Input; Active Low) - RD identifies the time period when the DS1685/DS1687 drives the bus with RTC read data. The RD signal is an enable signal for the output buffers of the RTC.

WR (RTC Write Input; Active Low) -The WR signal is an active-low signal. The WR signal defines the time period during which data is written to the addressed register.

RTC Pins

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RTC Pins

IRQ (Interrupt-Request Output; Open Drain, Active Low) – The IRQ pin is an active-low output of the DS1685/DS1687 that can be connected to the interrupt input of a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active state.

When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ pin is an open-drain output and requires an external pullup resistor. The voltage on the pullup supply should be no greater than VCC + 0.2V.

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Unused RTC Input Pins

CS (RTC Chip-Select Input; Active Low) – The chip-select signal must be asserted low during a bus cycle for the RTC portion of the DS1685/DS1687 to be accessed. CS must be kept in the active state during RD and WR timing. We will just tie CS to ground.

KS (Kickstart Input; Active Low) – While VCC is applied, the KS pin can be used as an interrupt input. Tie to VCC.

RCLR (RAM Clear Input; Active Low) – This pin is internally pulled up. Do not use an external pullup resistor on this pin. Leave it open.

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RTC Read Cycle Timing

Address Read data

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RTC Write Cycle Timing

Address Write data

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We are using the DS1687-3

Part

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Reading/Writing Time

• The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm bytes are always accessible because they are double buffered.

•The time, calendar, and alarm are set or initialized by writing the appropriate register bytes.

•The contents of the time, calendar, and alarm registers can be either binary or binary coded decimal (BCD) format. The data format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and alarm registers must use the same data mode. The data mode cannot be changed without reinitializing the 10 data bytes.

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The Update ProblemAn Example

1. The current time is 5:59:59

2. You read the hours byte = 05

3. An update cycle occurs, and time changes to 6:00:00

4. You read the minutes byte = 00

5. You read the seconds byte = 00

6. You report the time as: 5:00:00 when the time is actually 6:00:00.

7. The time is wrong by an hour, something bad happens, and you get fired.

If a read or write of the time and calendar data occurs during an update, a problem exists where seconds,

minutes, hours, etc., might not correlate.

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Solution to the Update ProblemBefore reading or writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. The set bit should be cleared after reading or writing to allow the RTC to update the time and calendar bytes.

Register B: SET – When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner.

The RTC executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm, and elapsed time byte is frozen and does not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows the time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent.

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Another Solution to the Update Problem

Another method exists for accessing the RTC registers that avoids any possibility of accessing inconsistent time and calendar data.

It uses the UIP bit in Register A to determine if the update cycle is in progress. The UIP bit pulses once per second. After the UIP bit goes high, the update transfer occurs 244µs later. If a low is read on the UIP bit, the user has at least 244µs before the time/calendar data is changed. Therefore, the user should avoid routines that would cause the time needed to read valid time/calendar data to exceed 244µs.

244µs

1,000,000 µs = 1 sec

update

update

update

update

Register A: UIP bit

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The UIP Bit and the Set Bit

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Update/Alarm Notification•The RTC can be configured to send out a notification or interrupt when specific events occur within the chip.

•The events which can cause a notification are selected by configuring the control registers

•Notification is sent by the RTC pulling the IRQN signal to ‘0’.

•This signal should be ties (through an inverter) to the interrupt pin of the PicoBlaze.

•When asserted (and if interrupts are enabled in the PicoBlaze), it will cause the PicoBlaze to interrupt, and branch to the interrupt service routine (ISR).

•The IRQN signal is turned off by the ISR clearing the appropriate flags within the RTC chip.

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000

10 10/1

0/1

0/1 0/1

10 0 0 0 0

0

0

0/1

Read Only

Read Only

0000

ReadOnly

Read Only 0000

RTCIRQN

Control

Bank

AlarmFlag

UpdateFlag

The Update Flag is set after time is

updated.

The Alarm Flag is set when the alarm

time is reached.

Both are enabled (AEI, UIE) to cause

an interrupt.

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A,B,C,D REGS

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PicoBlaze Interface

Data

Control Register

CodeBlock RAM

RTC

ALE RD WR

Address

AD

EN_A

EN_D

CS

gnd

IRQInterruptPort_In

Port_Out

Page 165: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

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Driving the AD Multiplexed Bus-- in entity declaration

-- rtc pins ad : inout std_logic_vector(7 downto 0); ale : out std_logic; wrn : out std_logic; rdn : out std_logic; csn : out std_logic; irqn : in std_logic -- in architecture

-- PicoBlaze Interrupt interrupt <= not irqn; -- rtc interrupt

-- addr is the address register port-- data is the data register port-- drive tri-state outputs for ad bus ad <= addr when en_addr='1' else data when en_data='1' else "ZZZZZZZZ";

-- ad feeds directly into mux driving port_in

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Input Port Timing

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Output Port Timing

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20 ns

Real-Time Clock Interface (50 MHz)

Strobe

Port_in

Port_out

ALE

RD

WR

AD

Instruction

Port_id

1. 2. 3. 4. 5. 7. 8.6. 9.

1. 2. 3. 4. 5. 7. 8.6. 9.

Read Cycle Worksheet

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20 ns

Real-Time Clock Interface (50 MHz)

Strobe

Port_in

Port_out

Instruction

Port_id

1. 2. 3. 4. 5. 7. 8.6. 9.

1. 2. 3. 4. 5. 7. 8.6. 9.

Write Cycle Worksheet

ALE

RD

WR

AD

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PicoBlaze Procedural Interface

;------------------------------------ ; Write_RTC (write to an RTC chip register); Parameters :; s0 the byte value to be written; s1 the RTC register number to write; Note: Also document what other registers are destroyed;------------------------------------

;------------------------------------ ; Read_RTC (read from an RTC chip register); Parameters :; s0 returns the byte value that was read; s1 the RTC register number to read; Note: Also document what other registers are destroyed;------------------------------------

Page 171: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

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Chip Pinout

3V

float

float

float

float

3V

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RTC Board Interface

The RTC board is connected to the Spartan-3 board through the B connector.

RTC Pin Name RTC pin B connector pin Spartan-3 Pin

AD0 4 20 M6

AD1 5 22 C15

AD2 6 24 D15

AD3 7 26 E15

AD4 8 28 F15

AD6 9 30 G16

AD6 10 32 H16

AD7 11 34 K16

CSN 13 16 R7

ALE 14 14 T7

WRN 15 12 R10

RDN 17 10 P10

IRQN 19 8 N11

SQW 23 6 T3

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Debug your RTC interface

by looking at the interface signals

on the Logic Analyzer

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Schematic of RTC Board

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Lab 5 Procedure

•You start with– Your lab 3 design

•You have toWeek 1– Read the RTC Data Sheet and answer the questions– Co-design your RTC / PicoBlaze interface

• (Hardware) Port register design and VHDL code• (Software) PicoBlaze code for Write_RTC and Read_RTC

– Simulate one RTC read cycle and one RTC write cycle– Design your user interface

Week 2– Write your user interface (PicoBlaze code)– Demonstrate your project

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Lab 5 Objectives

In this lab, you will learn how to:

•Interface to an Address/Data multiplexed bus

•Interface an FPGA to an external chip•Read data sheets•Design your own user interface•Interface to a device that produces interrupts

•Write an service interrupt routine•Control interrupts using enable and disable interrupt commands

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RTC Data Sheet Questions1. What is the difference between the DS1685 and the DS1687? (Page 1, Features; Page 3, Description last paragraph)

2. Why is the register set so complicated? (Page 1, Features (compability); Page 3, Description first paragraph; Page 19, paragraph 1 )

3. What is the difference between the DS1687-3 and the DS1687-5, and why do we use the -3 part? (Page 2)

4. At what time does the RTC latch the address from the AD pins? (Page 4, AD0-AD7, ALE)

5. At what time does the RTC latch the write data from the AD pins? (Page 4, AD0-AD7, WR)

6. How are the RTC buffer enables controlled? (Page 4, RD)

7. Why does the IRQn pin require an external pullup? (Page 5, IRQn)

8. How many registers contain time, calendar, and alarm data (but not control/status)? (Page 9. RTC Address Map; Page 10)

9. How is time set? (Page 10)

10. How is the decimal number 36 represented in 8-bit binary? How is it represented in 8-bit BCD? (general knowledge)

11. What does the DM bit do? (Page 10, second and third paragraphs; Page 13, DM)

12. Why are time, calendar, and alarm bytes always accessible? (Page 10, third paragraph)

13. What is the update problem? (Page 10, third paragraph)

14. In what bank do registers A, B, C, and D reside? (Page 12, first paragraph)

15. What bit values must be in bits DV2 and DV1 of the A registers, in order for the oscillator to be on, and allow the RTC to keep time? (Page 12)

16. What does bit DV0 of the A register do? (Page 12)

17. What three interrupts are enabled by bit PIE, AIE, and UIE in the B register? (Page 13)

18. How does the SET bit solve the update problem? (Page 10, paragraphs 2 and 3; Page 13, SET; Page 18, paragraph 1)

19. What is another side effect of turning on the SET bit in register B? (Page 12, UIE)

20. What is the relationship between the IRQF bit in register C and the IRQn pin of the RTC? (Page 14, IRQF; Page 16, top paragraph)

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RTC Data Sheet Questions, cont.d

21. How many different interrupt sources are in the RTC? (Page 14, IRQF; Page 15, Interrupt Control, Page 16, top paragraph)

22. How are the PF, AF, and UF, interrupt flags cleared? (Page 14, PF, AF, UF)

23. What sets the AF flag? (Page 14, AF)

24. What sets the UF flag? (Page 14, UF)

25. Under what conditions do the AF flags and the UF flags cause and interrupt? (Page 13, AIE, UIE; Page 14 AF, UF)

26. What does the acronym NV mean? (general knowledge)

27. Where are the interrupt enables for wake-up, kickstart, and RAM clear located? (Page 15)

28. How frequently do update cycles occur? (Page 18, paragraph 1)

[We do not use any of the extended functions, and you can safely skip pages 18-22, 26 of the data sheet.]

29. How do we disable the extend functions and keep them from interrupting? (Page 25)

30. What are the minimum and maximum supply voltages for a -3 part? (Page 27)

[Caution: when reading the DC and AC specifications, be sure to use the tables for the 3 volt parts on pages 29 and 30, don't use the tables for the 5 volt parts]

31. If the PicoBlaze operates at 50 MHz, what is the period of one PicoBlaze instruction? (PicoBlaze manual)

32. What is the minimum cycle time, t(CYC), of the RTC? (Page 30) How many instruction periods (rounded up) is this?

33. What is the minimum setup time, t(ASL), of address to ALE falling? (Page 30) If you drive the address with one instruction, and then cause ALE to fall the very next instruction, is this timing parameter met?

34. What is the minimum pulse width, PW(ASH), of ALE? (Page 30) How many instruction periods is this?

35. What is the minimum time, t(ASED), between when ALE falls and either WRn falls or RDn falls? (Page 30) What is the minimum number of instruction periods needed to meet this specification?

[Note: not all AC specifications have be covered in these questions. Your circuit will need to respect ALL of the specified timing restrictions.]

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InterruptsLab 5, Part 2

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Motivation• People like to hook up devices to

computers– Keyboards, networks, clocks, etc.– Particularly true in embedded systems

• External devices may require attention from processor at unpredictable times– CPU doesn’t know when you’re about to hit a key

• Accessing I/O devices can take a long time– Disk reads/writes have ~10ms latency– Would like processor to be able to do something

else while waiting

• Need way for the processor to determine that external devices need attention

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Alternative 1: Polling•The processor loops and repetitively checks each device to see if it has a request– Consumes CPU time even if no requests are

pending– Generally better average response time than

interrupts– How does software know when and how

often to poll?

Check 1

Check 2

Check 3

ServiceDevice 1

ServiceDevice 2

ServiceDevice 3

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Alternative 2: Interrupts• Give each device a wire (interrupt line) that it

can use to signal the processor– When interrupt is signaled, processor interrupts normal

activities to execute a routine called an interrupt service routing (or interrupt handler) to deal with the interrupt

– No CPU overhead when no requests pending

Device

Device

Device

Device

CPU

Interrupt

Interrupt

Interrupt

Interrupt

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Polling vs. Interrupts“Polling is like picking up the phone every few seconds

to see if you have a call-- Interrupts are like waiting for the phone to ring”

•Interrupts are better if the processor has other work to do and the time to respond to events isn’t absolutely critical

•Polling can be better if the processor has to respond to an event ASAP

Performance of interrupt hardware is a critical factor on processors for embedded systems.

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Hardware Response to Interrupt

•Interrupt Response Procedure– Complete current instruction– Preserve current context

•For PicoBlaze, the context is the PC, Zero flag, and Carry Flag

– Activate Interrupt Service Routine•Look up service routine address in interrupt vector

table according to interrupt number•For PicoBlaze, there is only one address: 0x3FF

•Return from Interrupt– Restore context– Return to original program

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Interrupt Control Instructions

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Interrupt Instruction Flow

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Interrupt Timing

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Critical Regions

•Hardware Interrupts can happen at any time •The currently running program should have no

idea that it was interrupted and an ISR executed. (Interrupts should leave the processor state unchanged.)

• If a section of code should not be interrupted for any reason, it is called a critical region, and you must disable interrupts temporarily.

•You may have many critical regions in your code.

start: enable interrupt ; be sure to enable at the beginning

; code here can be interrupted

disable interrupt ; start critical region

; critical region, code here cannot be interrupted

enable interrupt ; end critical region

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Writing an Interrupt Service Routine (ISR)

• Save ALL registers that you modify• Service the hardware that caused the

interrupt– Read/write data to/from the device that signaled the

interrupt (Ex: get character typed on a keyboard)

• Clear the interrupt– Tell device that you serviced it so it won’t interrupt

again

• Restore saved registers w/original values• RETURNI : Restore Flags & return

– RETURNI ENABLE : Re-enable the interrupt (most common)

– RETURNI DISABLE : Leave interrupts disabled

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Example ISR Codertc_isr: ; RTC interrupt service routine

store s0, 00 ; save all registers that you will use store s1, 01 ; and etc. (Don’t forget about subroutine’s regs)

load s1, 0C ; load RTC register C address in s1 call read_RTC ; read register C into s0, clears reg C ; clearing reg C should also clear the interrupt

test s0, alarmFlag ; was it an alarm? call NZ, handleAlarm ; if so, do what you need, then return ; note handleAlarm cannot alter s0

test s0, updateFlag ; was it an update? call NZ, handleUpdate ; if so, do what you need, then return

fetch s0, 00 ; restore all registers that you saved fetch s1, 01 ; and etc.

returni enable ; return from interrupt, re-enable interrupts

ADDRESS 3ff ; PicoBlaze calls here when interrupt rec’d jump rtc_isr ; Jump to the RTC interrupt service routine

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Lab 6 - SDRAM Controller

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SDRAM

•256-Mbyte SDRAM•3.3 V, LVTTL•Synchronous interface

– All signals are registered on rising edge of CLK– Pipelined internally for high speed data rate

•Read and Write commands are burst oriented

•ACTIVE command– Select bank and row

•READ or WRITE command– Select the starting column of a burst access of 1,

2, 4, or 8 locations

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DRAM Basics• Basic DRAM cell has:

– Transistor T switch element– Capacitor C storage element

• Data is stored as a voltage on the capacitor C– Vcc = 1– Gnd = 0

• To read:– Precharge BL and BL* to

Vcc/2– Open T allowing C and Cd to

charge share (destructive)– Compare Vd (on BL) to Vcc/2

(on BL*) with sense amplifier– Write value back to storage

capacitor C (restore)

• To write:– Put voltage on BL, Vcc=1,

Gnd=0– Open T allowing C be

(re)charged to the voltage on BL

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Refresh and Precharge•The charge on storage capacitor C slowly leaks away and voltage on capacitor changes.

•The charge on the capacitor must be refreshed periodically, to keep data from being lost.

•DRAMs refresh an entire row in one operation.

•It is important that the voltages stored capacitively on the bit lines be kept at Vcc/2.

•Forcing bit lines to Vcc/2 is called precharging.•Before reading or writing a bit cell, the bit lines must be precharged.

•DRAMs precharge an entire bank in on operation.

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Pipelining - The advantage of SDRAM

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32 Meg x 8-bit SDRAM

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32-Megabit x 8-bit SDRAM Addressing

9 8 7 6 5 4 3 2 1 0AP

22212019181716151413121110 9 8 7 6 5 4 3 2 1 02423

22 21 20 19 18 17 16 15 14 13 12 11 10

24 23Bank BA1-BA0

Row A12-A0

Column A9-A0

256-Mbit/8-bit = 228/23 = 225 --- 25 Address bits

Auto Precharge

Unused

Bank

Row

Column

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SDRAM Clock Pins•Clock: CLK is driven by the system clock. All

SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

•Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

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SDRAM Address and Data Pins

•Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied.

•Address Inputs: A0-A12 are sampled during the ACTIVE command (row address A0-A12) and READ/WRITE command (column-address A0-A9, with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

•Data Input/Output: DQ7-DQ0 Bidirectional data bus.

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SDRAM Command Pins•Chip Select: CS# enables (registered LOW) and

disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

•Row Select: RAS# Command input•Column Select: CAS# Command input•Write Enable: WE# Command Input• Input/Output Mask: DQM is an input mask

signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle.

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SDRAM Commands

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The Mode Register

•WB - Write Burst Mode (0 - burst access 1 - single access )

•Op Mode ( always 00 )•CAS Latency ( 010 - 2 cycles, or 011 - 3 cycles )•BT - Burst Type ( 0 - Sequential, 1 - interleaved )•Burst Length ( 000 - 1 location, 001 - 2 locations,

010 - 4 locations, 011 - 8 locations, 111 - full page)•See page 13 of data sheet for field definitions

Page 203: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

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CAS Latency

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Single Reads

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Burst Reads

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Read DataFIFO

State Machine (50 MHz)

CodeBlock RAM

SDRAM

CS,

RAS CAS

Address_low

DQ

SEL

EN

Address_high

Mu

xMode

Write DataFIFO

A

RD WR WE

DQM

Command

StatusSystemBlock

Diagram

16x8

16x8

8

8

9

9

A

B

C

SDRAM Controller

BA1,BA0

startedSet start

CKE

Page 207: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Addressing

9 8 7 6 5 4 3 2 1 0AP

22212019181716151413121110 9 8 7 6 5 4 3 2 1 02423

22 21 20 19 18 17 16 15 14 13 12 11 10

24 23Bank BA1-BA0

Row A12-A0

Column A9-A0

Auto Precharge

Unused

Bank

Row

Column

Tied Constant 0

address_low register

address_high register

Page 208: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Command, Status, and Mode Registers

•Command Register

•Write to port 8•Bits

– 0 Read Op– 1 Write Op– 2 Load Mode

Op– 3-7 Unused

•Status Register•Read from port 8•Bits

– 0 Write FIFO empty– 1 Write FIFO full– 2 Read FIFO empty– 3 Read FIFO full– 4-5 Unused– 6 SDRAM Idle– 7 Command

started• Cleared when

command register is written

• Set when State Machine starts operation

•Mode Register•Write to port C•Bits

– 0-2 Burst Length– 3 BT Burst Type– 4-6 Unused– 7 WB Write Burst

Mode

•Constant Fields– CAS Latency =

“010”– Op Mode = “00”– BA1-BA0 = Bank

“00”

Only one operation will be requested

at a time.

Page 209: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Command Started - Handshake Bit

1. Command, Mode, and Address

Registers are written by PicoBlaze

2. Command Started is cleared by PicoBlaze

4. Command Started is set by the

State Machine .

PicoBlazeWaits until the commands started bit is high. Then it

writes the command, address, and mode registers and clears

the command started bit.

State MachineWaits until the command

started bit is low. Then it uses the command, address, and mode registers and sets the

command started bit.

Command, Address, & Mode Registers

CommandStarted

3. Command, Mode, and Address

Registers are used by State

Machine

1. Command, Mode, and Address

Registers are written by PicoBlaze

2. Command Started is cleared by PicoBlaze

3. Command, Mode, and Address

Registers are used by State

Machine

Page 210: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Example Code

load s0, burst_4output s0, mode_regload s0, load_mode_opoutput s0, command_reg

load s0, 60 ; 4560output s0, addr_lo_regload s0, 45output s0, addr_hi_reg

fetch s0, (s1)output s0, write_fifoadd s1, 01fetch s0, (s1)output s0, write_fifoadd s1, 01fetch s0, (s1)output s0, write_fifoadd s1, 01fetch s0, (s1)output s3, write_fifoload s0, write_opoutput s0, command_reg

load s0, burst_4output s0, mode_regload s0, load_mode_opoutput s0, command_reg

load s0, 60 ; 4560output s0, addr_lo_regload s0, 45output s0, addr_hi_reg

load s0, read_opoutput s0, command_reg

; wait for read fifo

input s0, read_fifostore s0, (s1)add s1, 01input s0, read_fifostore s0, (s1)add s1, 01input s0, read_fifostore s0, (s1)add s1, 01input s0, read_fifostore s0, (s1)add s1, 01

Writing Reading

; registersconstant command_reg, 08constant status_reg, 08constant write_fifo, 09constant read_fifo, 09constant addr_lo_reg, 0Aconstant addr_hi_reg, 0Bconstant mode_reg, 0C

; commandsconstant read_op, 01constant write_op, 02constant load_mode_op, 04

; modesconstant burst_4, 82

Constants

Page 211: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Outline of SDRAM ControllerState Machine

Init Idle

SetMode

Re-fresh

Active

Active

Read

Write

Pre-charge

An external counter/timer will be needed to do initialization and refreshing.Using fixed delay lines in outputs may simplify the state machine.

Page 212: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Schematic of SDRAM Board

Page 213: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Test Bench Block Diagram

top_tb

top mt48lc32m8a2

clk_insclk

sclk_fb

dq

a, ba

cke, csn, rasn, casn,wen,dqm

process

dq

addr, ba

clk

cke, cs_n, ras_n, cas_n,we_n,dqm

processswitches, buttons, etc.

Page 214: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 6 Procedure

•You start with– Your lab 3 design.

•You have toWeek 1– Read the data sheet and answer the questions– Design your SDRAM Controller State Machine

Week 2– Write the VHDL for the new ports and your state

machine– Simulate in a test bench with the SDRAM VHDL model

(provided)

Week 3– Add circuitry to ensure timing constraints are met.– Demonstrate your project with the test PicoBlaze code

(code.vhd) given to you.

Page 215: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Lab 6 Objectives

In this lab, you will learn how to:

•Interface an FPGA to an external SDRAM chip

•Read a complex data sheet•Use FIFOs in pipelined interfaces•Use a handshake•Solve timing problems

Page 216: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

SDRAM Data Sheet Questions1. (Pages 1, 14) There are 2 speed grades, –7E

and –75. If you were designing for a clock frequency of 133MHz, what must you do differently if you used the slower –75 part instead of the faster –7E part?

2. (Pages 12,13,15,40) How do you set the CAS latency?

3. (Page 4) What voltage does this SDRAM require?

4. (Page 4) What are the advantages of SDRAM over standard DRAM?

5. (Pages 9,16,22) What does the DQM pin do?

6. (Page 12) What is a burst access?

7. (Pages 12,7) How is the x8 SDRAM organized internally? _____banks, _____rows, _____columns, _____bits per column.

8. (Pages 12,16,18) What does the ACTIVE command do? Be specific about the address bits.

Page 217: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

SDRAM Data Sheet Questions9. (Pages 12,16,19-24) What does the READ

command do? Be specific about the address bits.

10. (Page 12) Prior to being initialized, the SDRAM must be issued COMMAND INHIBIT or NOP commands for a certain amount of time after the clock is stable. How much time is this, and how many cycles is this at 50 MHz?

11. (Pages 12,15) How can one program a PRECHARGE command to precharge all of the banks with a single command?

12. (Pages 12,13) What burst length options are available?

13. (Pages 12,13) What is the difference between sequential and interleaved burst accesses? (a generalized, short answer)

14. (Pages 12,16,38) After programming the mode register with the LOAD MODE REGISTER command, how much time, and how many cycles at 50 MHz, must you wait? (round up cycles)

15. (Pages 12,13,14) What CAS latency options are available?

16. (Pages 16,23,24,27) What does the PRECHARGE command do?

Page 218: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

SDRAM Data Sheet Questions17. (Page 47,37) How much time, and how many

cycles at 50 MHz, after an ACTIVE command can you issue a PRECHARGE command? (-75 part, round-up cycles)

18. (Page 52,37) How much time, and how many cycles at 50 MHz, after a WRITE command can you issue a PRECHARGE command? (-75 part, round-up cycles)

19. (Pages 16,37) After a PRECHARGE or AUTO PRECHARGE command, how much time, and how many cycles at 50 MHz, must you wait before issuing an ACTIVE command? (-75 part, round-up cycles)

20. (Pages 16,45,46) How does the AUTO PRECHARGE command differ from the PRECHARGE command?

21. (Pages 32,33) What does a PRECHARGE command do if the bank is inactive (idle)?

22. (Page 17) What does the AUTO REFRESH command do?

23. (Page 17) At 50 MHz, how many cycles maximum, on average, should there be between consecutive AUTO REFRESH commands? (round-down)

24. (Pages 17,37) The entire SDRAM must be refreshed in how much time?

Page 219: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

SDRAM Data Sheet Questions25. (Page 37) How much time, and how

many cycles at 50 MHz, after an AUTO REFRESH command must you wait before issuing another command? (–75 part, round-up cycles)

26. (Page 32) Can AUTO REFRESH be issued while a row is active?

27. (Page 17) What does the SELF REFRESH command do?

28. (Page 17) How do you exit self-refresh mode?

29. (Pages 18,37,47,52) After an ACTIVE command is issued, how much time, and how many cycles at 50 MHz, must you wait before issuing a READ or WRITE command? (-75 part, round-up cycles)

30. (Pages 18,37) After an ACTIVE command is issued, how much time, and how many cycles at 50 MHz, must you wait before a subsequent ACTIVE command be issued to a different row in the same bank? (-75 part, round-up cycles)

31. (Pages 18,37) After an ACTIVE command is issued, how much time, and how many cycles at 50 MHz, must you wait before a subsequent ACTIVE command be issued to a different row in the different bank? (-75 part, round-up cycles)

Page 220: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

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Lab 6SDRAM Controller

Week 3Synchronizing External Clocks

Page 221: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Synchronizing the External Clock

•Problem:– There is skew between the on-chip clock and

the clock that goes to the SDRAM.– Setup and Hold times might not be met at the

SDRAM.

•Solution– Dual DLLs synchronize the external clock to the

internal clock.– Entire board now behaves as one large globally

synchronous system

•A clock demo has been prepared to show you how to do this.

Page 222: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Clock Demo

CLK_IN

SCLK_FB

SCLK

LOCKED

CLK

CLK

RSTCOUNTER

COUNT

SCLKCLK_IN

SCLK_FB

clock.vhd50 MHzClock

Generator

Delay

clock_tb.vhd

Dual DLLs

resetcircuit

4-bit counter

Page 223: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Dual DLLs ( part of clock.vhd )

EXTDLL

EXTCLK0

LOCKED

INTDLL

RST BUFG

IBUFG

LOCKED

RST

To reset circuitry

To off-chipcircuits

To on-chipcircuits

CLKIN

CLKFB

CLKIN

CLKFB

IBUFFrom

off-chipcircuits

OBUFCLK_IN

SCLK_FB

SCLK

CLK0

CLKBUF

FBBUF

EXTLOCK

INTRST

LOCKED

CLK

Page 224: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Simulation of Dual DLL1 2

1. clk_in and sclk_fb are not aligned.2. DLL advances sclk so clk_in and

sclk_fb are aligned.3. External DLL locks, starts internal

DLL.4. clk_in is aligned with both clk and

sclk_fb.5. Internal DLL locks.6. Reset falls, count starts counting.

3 4 5 6

Page 225: BYU ECEn 320 Lab Lectures Preparation for ECEn 320 Lab Exercises.

BYU ECEn 320

Instancing Library Componentslibrary ieee;

use ieee.std_logic_1164.ALL;use ieee.numeric_std.ALL;

library UNISIM;use UNISIM.Vcomponents.ALL;

Provides component definitions.Also provides simulationcapability for your design that is ignored in synthesis… component IBUFG

port ( I : in std_logic; O : out std_logic); end component; component BUFG port ( I : in std_logic; O : out std_logic); end component;

component CLKDLL port ( clkin : in std_logic; clkfb : in std_logic; rst : in std_logic; clk0 : out std_logic; clkdv : out std_logic; locked : out std_logic );

These and hundreds of othercomponents are defined for youin UNISIM.Vcomponents