Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 1

Question Bank

UNIT I

1. Explain the CMOS inverter transfer characteristics highlighting the regions of operation

of the MOS transistors. (DEC 08/JAN 09,JUN-JUL 09,MAY-JUN 10,JUN-JUL 2011)

2. Describe with neat diagrams, the P well fabrication process

(DEC JAN 09, MAY-JUN 10,JUN-JUL 11)

3. Explain the action of enhancement mode transistor for different values of Vgs and Vds

(JUN- JUNL 09)

4. How is a NMOS transistor fabricated? Explain with neat sketches.

(JUN-JUL09,JUN 12)

5. What is a tristate inverter? Explain

(JUN-JUL 09)

6. Distingush between enhancement and depletion mode transistors.

(DEC-JAN 10)

7. Explain with diagrams, the main steps in twin tub process.

(DEC-JAN 10)

8. Compare CMOS and Bipolar technologies.

(DEC-JAN 10,MAY JUN 10)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 2

UNIT 2

1. Discuss the effect of channel modulation on the performance of an nMOS transistor

(DEC JAN 09)

2. List the color, stick encoding, mask layout encoding and CIF layers for the following

layers used in VLSI technology:

i) n diffusion ii) polysilicon iii) Metal1 iv) Impact

(DEC JAN 09)

3. Write the stick diagram for a parity generator using nMOS logic.

(DEC JAN 09)

4. Write the layout for the logic expression Y= A+BC using CMOS logic

(DEC JAN 09)

5. Discuss the limits of scaling on

i) Supply voltage due to noise ii) sub threshold current iii) interconnects.

(DEC JAN 09)

6. Explain the transmission gate operation.

(MAY JUN10)

7. Draw lambda based design rules for double metal CMOS process for layers and

transistors.

(MAY JUN 10)

8. Draw the circuit and stick diagram for NAND gate .

(MAY JUN 10)

9. With a neat diagram, explain lambda rules for contact cuts and vias.

(DEC 08)

10. Draw the stick diagram for the NMOS implementation of the Boolean expression

Y'=AB+C.

(DEC 08)

11. What is noise margin? Obtain the values of VIL,VIH, VOL,and VOH .

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 3

( JUN-JUL 09)

12. Draw the schematic and stick diagram of CMOS 2 input NAND.

(JUN-JUL 09)

13. Implement the pass transistor logic circuit for the expression Y= A+BC

(DEC 10)

UNIT III

1. Realize a 2 input NAND gate for a clocked CMOS logic and also for CMOS domino

logic

(DEC JAN 09, JUN JUL 11,DEC 11)

2. Explain different types of pseudo – NMOS logic

(MAY JUN 10, DEC10)

3. Explain CMOS domino logic and derive the evaluation voltage equation

(MAY JUN 10)

4. Explain 2 inputs X-NOR gate in pass transistor logic

(MAY JUN 10)

5. Discuss the merits and demerits of the following CMOS logic structures with a two input

NAND gate realization as an example.

i) Complementary CMOS logic ii) PseudoNMOS logic iii) Dynamic CMOS logic

(DEC08, JUN JUL 11, JUN12)

6. Explain the operation of CMOS Transmission gate

(DEC 08)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 4

UNIT IV

1. Narrate the steps involved in calculating the sheet resistance of:

i) transistor channels ii) nMOS inverter iii) CMOS inverter

(DEC JAN 09)

2. Derive expressions for rise time and fall time for 1:1 CMOS inverter

3. Define sheet resistance and standard unit of capacitance Cg

( JUN JUL09)

4. Obtain the expression for total delay for N stages of nmos and cmos inverters in terms of

width factor

(JUN JUL 09)

UNIT V

1. Describe switch and CMOS logic implementtaion for two input X-Or gate

(DEC 08, MAY JUN 10)

2. Design a parity generator with the following specifications and draw the stick diagram

for one basic cell.

(DEC 08, JUN JUL 09, JUN JUL 11)

3. Discuss the architectural issues to be followed in the design of a VLSI subsystem

(DEC JAN 09)

4. Design 4:1 MUX using transmission gates

(DEC JAN 09,JUN 12, JUN JUL 09, MAY JUN 10)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 5

5. Explain the 4X4 cross bar switch operation. Mention the salient features of subsystem

design process.

( MAY JUN 10,JUN JUL 11)

6. What are the properties of NMOs and PMOs switches?

( JUN JUL 09)

7. Design bus arbitration logic for n line bus.

(DEC 11)

8. What are the scaling factors for Gate capacitance, Max frequency, current density, power

speed product?

(JUN JUL 09)

UNIT VI

1. Discuss the timing constraints for both flipflops and latches

(DEC JAN 09)

2. Discuss Baugh- Worley method used for two’s complement multiplication

(DEC JAN 09)

3. Explain the design steps for a 4 bit adder.

4. How can 4 bit ALU architecture be used to implement an adder

(MAY JUN 10, JUN JUL 09)

5. Draw the basic form of two phase clock generator and explain.

(JUN JUL 09)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 6

UNIT VII

1. Explain the dynamic 2 bit shift register circuit using NMOS and CMOS logic

(DEC08)

2. Discuss the various system timing constraints.

(DEC08)

3. Explain the transistor Dynamic RAM cell

(DEC08)

4. Explain the working of 3TD RAM cell

(DEC JAN 09)

5. Explain the read and write operations in dynamic memory cell

(MAY JUN 10)

6. What is structured design process? Explain.

(JUN JUL 09)

7. What are the system timing considerations?

(JUN JUL 09)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 7

UNIT VIII

1. Write short note on Level sensitive scan.

(DEC 08)

2. Narrate the meaning of controllability and observability in VLSI chip testing

(Dec Jan 09)

3. Explain different types of I/O pads.

(May JUN 10)

4. Write a note on testability and testing

(May JUN 10)

5. Explain the ground rubs for a system design.

(May JUN 10)