CMOS VLSIDesign

Circuits & Layout

Slide 2CMOS VLSI Design

Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams

Slide 3CMOS VLSI Design

A Brief History 1958: First integrated circuit

– Flip-flop using two transistors– Built by Jack Kilby at Texas Instruments

2003– Intel Pentium 4 processor (55 million transistors)– 512 Mbit DRAM (> 0.5 billion transistors)

53% compound annual growth rate over 45 years– No other technology has grown so fast so long

Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society

Slide 4CMOS VLSI Design

Annual Sales 1018 transistors manufactured in 2003

– 100 million for every human on the planet

0

50

100

150

200

1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

Global S

emiconductor B

illings(B

illions of US

$)

Slide 5CMOS VLSI Design

Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large,

expensive, power-hungry, unreliable 1947: first point contact transistor

– John Bardeen and Walter Brattain at Bell Labs– Read Crystal Fire

by Riordan, Hoddeson

Slide 6CMOS VLSI Design

Transistor Types Bipolar transistors

– npn or pnp silicon structure– Small current into very thin base layer controls

large currents between emitter and collector– Base currents limit integration density

Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current

between source and drain– Low power allows very high integration

Slide 7CMOS VLSI Design

1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

MOS Integrated Circuits

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

Slide 8CMOS VLSI Design

Moore’s Law 1965: Gordon Moore plotted transistor on each chip

– Fit straight line on semilog scale– Transistor counts have doubled every 26 months

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium IIIPentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1970 1975 1980 1985 1990 1995 2000

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates

Slide 9CMOS VLSI Design

Corollaries Many other factors grow exponentially

– Ex: clock frequency, processor performance

Year

1

10

100

1,000

10,000

1970 1975 1980 1985 1990 1995 2000 2005

4004

8008

8080

8086

80286

Intel386

Intel486

Pentium

Pentium Pro/II/III

Pentium 4

Clock S

peed (MH

z)

Slide 10CMOS VLSI Design

CMOS Gate Design Activity:

– Sketch a 4-input CMOS NAND gate

Slide 11CMOS VLSI Design

CMOS Gate Design Activity:

– Sketch a 4-input CMOS NOR gate

A

B

C

DY

Slide 12CMOS VLSI Design

Complementary CMOS Complementary CMOS logic gates

– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X

Slide 13CMOS VLSI Design

Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2

Slide 14CMOS VLSI Design

Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate

– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS

Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel

A

B

Y

Slide 15CMOS VLSI Design

Compound Gates Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)

pMOS network

nMOS network

Slide 16CMOS VLSI Design

Example: O3AI Y A B C D

Slide 17CMOS VLSI Design

Example: O3AI Y A B C D

A B

Y

C

D

DC

B

A

Slide 18CMOS VLSI Design

Signal Strength Strength of signal

– How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0

nMOS pass strong 0– But degraded or weak 1

pMOS pass strong 1– But degraded or weak 0

Thus nMOS are best for pull-down network

Slide 19CMOS VLSI Design

Pass Transistors Transistors can be used as switches

g

s d

g

s d

Slide 20CMOS VLSI Design

Pass Transistors Transistors can be used as switches

g

s d

g = 0

s d

g = 1

s d

0 strong 0

Input Output

1 degraded 1

g

s d

g = 0

s d

g = 1

s d

0 degraded 0

Input Output

strong 1

g = 1

g = 1

g = 0

g = 0

Slide 21CMOS VLSI Design

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

Slide 22CMOS VLSI Design

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

g = 0, gb = 1

a b

g = 1, gb = 0

a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a b

g

gb

a b

g

gb

a b

g

gb

g = 1, gb = 0

g = 1, gb = 0

Slide 23CMOS VLSI Design

Tristates Tristate buffer produces Z when not enabled

EN A Y

0 0

0 1

1 0

1 1

A Y

EN

A Y

EN

EN

Slide 24CMOS VLSI Design

Tristates Tristate buffer produces Z when not enabled

EN A Y

0 0 Z

0 1 Z

1 0 0

1 1 1

A Y

EN

A Y

EN

EN

Slide 25CMOS VLSI Design

Nonrestoring Tristate Transmission gate acts as tristate buffer

– Only two transistors– But nonrestoring, i.e., the output Y is not driven

by Vdd or GND• Noise on A is passed on to Y

A Y

EN

EN

Slide 26CMOS VLSI Design

Tristate Inverter Tristate inverter produces restored output

– Violates conduction complement rule– Because we want a Z output

A

YEN

EN

Slide 27CMOS VLSI Design

Tristate Inverter Tristate inverter produces restored output

– Violates conduction complement rule– Because we want a Z output

A

YEN

A

Y

EN = 0Y = 'Z'

Y

EN = 1Y = A

A

EN

Slide 28CMOS VLSI Design

Multiplexers 2:1 multiplexer chooses between two inputs

S D1 D0 Y

0 X 0

0 X 1

1 0 X

1 1 X

0

1

S

D0

D1Y

Slide 29CMOS VLSI Design

Multiplexers 2:1 multiplexer chooses between two inputs

S D1 D0 Y

0 X 0 0

0 X 1 1

1 0 X 0

1 1 X 1

0

1

S

D0

D1Y

Slide 30CMOS VLSI Design

Gate-Level Mux Design How many transistors are needed?

1 0 (too many transistors)Y SD SD

Slide 31CMOS VLSI Design

Gate-Level Mux Design How many transistors are needed? 20

1 0 (too many transistors)Y SD SD

44

D1

D0S Y

4

2

2

2 Y2

D1

D0S

Slide 32CMOS VLSI Design

Transmission Gate Mux Nonrestoring mux uses two transmission gates

Slide 33CMOS VLSI Design

Transmission Gate Mux Nonrestoring mux uses two transmission gates

– Only 4 transistorsS

S

D0

D1

YS

Slide 34CMOS VLSI Design

Inverting Mux Inverting multiplexer

– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing

Noninverting multiplexer adds an inverter

S

D0 D1

Y

S

D0

D1Y

0

1S

Y

D0

D1

S

S

S

S

S

S

Slide 35CMOS VLSI Design

D Latch When CLK = 1, latch is transparent

– D flows through to Q like a buffer When CLK = 0, the latch is opaque

– Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch

CLK

D Q

Latc

h D

CLK

Q

Slide 36CMOS VLSI Design

D Latch Design Multiplexer chooses D or old Q

1

0

D

CLK

QCLK

CLKCLK

CLK

DQ Q

Q

Slide 37CMOS VLSI Design

D Latch Operation

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q

Slide 38CMOS VLSI Design

D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave

flip-flop

Flo

p

CLK

D Q

D

CLK

Q

Slide 39CMOS VLSI Design

D Flip-flop Design Built from master and slave D latches

QM

CLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latc

h

Latc

h

D QQM

CLK

CLK

Slide 40CMOS VLSI Design

D Flip-flop Operation

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q

Slide 41CMOS VLSI Design

Race Condition Back-to-back flops can malfunction from clock skew

– Second flip-flop • fires late (if no clock skew, CLK1 and CLK2

should arrive at the the same time)• sees first flip-flop change and captures its result

– Called hold-time failure or race condition

CLK1

D Q1

Flo

p

Flo

p

CLK2

Q2

CLK1

CLK2

Q1

Q2

Slide 42CMOS VLSI Design

Nonoverlapping Clocks Nonoverlapping clocks can prevent races

– As long as nonoverlap exceeds clock skew– Industry manages skew more carefully instead

1

11

1

2

22

2

2

1

QMQD

Slide 43CMOS VLSI Design

Gate Layout Layout can be very time consuming

– Design gates to fit together nicely– Build a library of standard cells

Standard cell design methodology

– VDD and GND should abut (standard height) and often called supply rails

– Adjacent gates should satisfy design rules– nMOS at bottom and pMOS at top– All gates include well and substrate contacts

Slide 44CMOS VLSI Design

Example: Inverter

Slide 45CMOS VLSI Design

Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top

Metal1 GND rail at bottom 32 by 40

Slide 46CMOS VLSI Design

Stick Diagrams Stick diagrams help plan layout quickly

– Need not be to scale– Draw with color pencils or dry-erase markers

Slide 47CMOS VLSI Design

Wiring Tracks A wiring track is the space required for a wire

– 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track

Slide 48CMOS VLSI Design

Well spacing Wells must surround transistors by 6

– Implies 12 between opposite transistor flavors– Leaves room for one wire track

Slide 49CMOS VLSI Design

Area Estimation Estimate area by counting wiring tracks

– Multiply by 8 to express in

Slide 50CMOS VLSI Design

Example: O3AI Sketch a stick diagram for O3AI and estimate area

– Y A B C D

Slide 51CMOS VLSI Design

Example: O3AI Sketch a stick diagram for O3AI and estimate area

– Y A B C D

Slide 52CMOS VLSI Design

Example: O3AI Sketch a stick diagram for O3AI and estimate area

– Y A B C D

Slide 53CMOS VLSI Design

HW#2Due: September 11 class timeNo late homework acceptedExercises: 1.8, 1.9, 1.11, 1.12, 1.18