ECE 342 Solid State Devices Circuits 4. CMOSjsa.ece.illinois.edu/hcmut/ece342/notes/Lect_04.pdfECE...

ECE 342 – Jose Schutt‐Aine

ECE 342Solid‐State Devices & Circuits

4. CMOS

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]

1


Digital Circuits

VIH: Input voltage at high state VIHminVIL: Input voltage at low state VILmaxVOH: Output voltage at high state VOHminVOL: Output voltage at low state VOLmin

Currents into input

IIH IIHmaxIIL IILmax

IOH IOHmaxIOL IOLmax

Likewise for current we can define

Currents into output

2

ECE 342 – Jose Schutt‐Aine 3

NMHNML

Voltage Transfer Characteristics (VTC)The static operation of a logic circuit is determined by its VTC

• In low state: noise margin is NML

• In high state: noise margin is NMH

L IL OLNM V V

H OH IHNM V V VIL and VIH are the points where the slope of the VTC=-1

• An ideal VTC will maximize noise margins

/ 2 L H DDNM NM VOptimum:


Switching Time & Propagation Delay

input

output

4


tr=rise time (from 10% to 90%)tf=fall time (from 90% to 10%)tpLH=low-to-high propagation delaytpHL=high-to-low propagation delay

Inverter propagation delay: 12p pLH pHLt t t

Switching Time & Propagation Delay

5


For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for Vth, VIL, VIH, VOH, NML, NMH. Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply?

3.0 ; 0.0OH DD OLV V V V V

Ideal 3V logic implies:

/ 2 3.0 / 2 1.5 ;th DDV V V

/ 2 1.5 ; / 2 1.5IL DD IH DDV V V V V V

VTC and Noise Margins


3.0 1.5 1.5H OH IHNM V V V

1.5 0.0 1.5L IL OLNM V V V

The gain in the transition region is:

/ 3.0 0.0 / 1.5 1.5OH OL IH ILV V V V

3 / 0 /V V

VTC and Noise Margins

Inverting transfer characteristics


When inverter threshold is at VDD/2, the noise margin NMH and NML are equalized

3 28 3H L DD thNM NM V V

Noise margins are typically around 0.4 VDD; close to half power-supply voltage CMOS ideal from noise-immunity standpoint

: noise margin for high inputNML: noise margin for low inputVth: threshold voltage

CMOS Noise Margins

8


Switching Circuit

9


Nonideal Switch

1sc

lowsc L

RV VR R

1

sohigh

so L

RV VR R

10


IV Characteristics of Switches

Ideal switch Non-ideal switch

11


Complementary Switches

1sc

lowsc so

RV VR R

1

sohigh

so sc

RV VR R

12


Problem

CC Sout

L S

V RVR R

6: 10 10 5S outOpen R V V

A switch has an open (off) resistance of 10M and close (on) resistance of 100 .Calculate the two voltage levels of Vout for the circuit shown. Assume RL=5 k

22 5 10: 10 0.098

5000 100S outShort R V V

13


Problem

100 , 10S SR on R off M

If two switches are used as shown, calculate the two output voltage levels. Assume switches are complementary

2

1 2

CC Sout

S S

V RVR R

State 1: S1 off, S2 on RS1=10 M, RS2=100

6

5 100 5 010 10 100outV V V

State 2: S1 on, S2 off RS1=100 , RS2=10 M

6 7

6 7

5 10 10 5 10 510 10 100 10 100outV V

14


MOSFET Switch

NMOS PMOS

• Characteristics of MOS Switch – MOS approximates switch better than BJT in off state– Resistance in on state can vary from 100 to 1 k

15


NMOS Switch

16


CMOS Switch

CMOS switch is called an inverter

17

The body of each device is connected to its source NO BODY EFFECT


CMOS Switch – Off State

• OFF State (Vin: low)– nMOS transistor is off– Path from Vout to V1 is through PMOS Vout: high

18


CMOS Switch – Input Low

19


CMOS Switch – Input LowNMOS

GSN TNV V OFF

rdsn high

PMOS

'

1dsp

p DD TPp

rWk V VL

rdsp is low

20


CMOS Switch – On State

• ON State (Vin: high)– pMOS transistor is off– Path from Vout to ground is through nMOSVout: low

21


CMOS Switch – Input High

22


PMOS

GSP TPV V OFF

rdsp high

CMOS Switch – Input HighNMOS

'

1dsn

n DD TNn

rWk V VL

rdsn is low

23


CMOS Inverter

'

1dsn

N DD Tn

rWk V VL

'

1dsp

P DD Tp

rWk V VL

Short switching transient current low power

24


Load driving capability of CMOS is high. Transistors can sink or source large load currents that can be used to charge and discharge load capacitances.

CMOS Inverter

Advantages of CMOS inverter Output voltage levels are 0 and VDDsignal swing is

maximum possible Static power dissipation is zero Low resistance paths to VDD and ground when needed High output driving capability increased speed Input resistance is infinite high fan-out


CMOS Inverter VTC

QP and QN are matched


Derivation Assume that transistors are matched Vertical segment of VTC is when both QN and QP are saturated No channel length modulation effect = 0 Vertical segment occurs at vi=VDD/2 VIL: maximum permitted logic-0 level of input (slope=-1) VIH: minimum permitted logic-1 level of input (slope=-1)

CMOS Inverter VTC

To determine VIH, assume QN in triode region and QP in saturation region

221 12 2I t o o DD I tv V v v V v V

Next, we differentiate both sides relative to vi

o oI t o o DD I t

I I

dv dvv V v v V v Vdv dv


CMOS Inverter VTC

Substitute vi=VIH and dvo/dvi = -1

2DD

o IHVv V

After substitutions, we get

1 5 28IH DD tV V V

Same analysis can be repeated for VIL to get

1 3 28IL DD tV V V


CMOS Inverter Noise Margins

1 5 28IH DD tV V V

1 3 28IL DD tV V V

1 3 28H DD tNM V V

1 3 28L DD tNM V V Symmetry in VTC equal

noise margins


Matched CMOS Inverter VTC

n

p np

W WL L

CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors

Symmetrical transfer characteristics is obtained via matching equal current driving capabilities in both directions (pull-up and pull-down)

30


VTC and Noise Margins - ProblemAn inverter is designed with equal-sized NMOS and PMOS transistors and fabricated in a 0.8-micron CMOS technology for which kn’ = 120 A/V2, kp’ = 60 A/V2, Vtn =|Vtp|=0.7 V, VDD= 3V, Ln=Lp = 0.8 m, Wn = Wp = 1.2 m, find VIL, VIH and the noise margins.

2' 2 '1 12 2n I t o o p DD I t

n p

W Wk V V V V k V V VL L

Equal sizes NMOS and PMOS, but kn’=2kp’

Vt = 0.7V

For VIH: QN in triode and QP in saturation


224 2I t o o DD I tV V V V V V V

Differentiating both sides relative to VI results in:

: 4 4 4 2 ( 1)o oI t o o DD I t

I I I

V VV V V V V V VV V V

Substitute the values together with:

and 1oI IH

I

VV VV

VTC and Noise Margins – Problem (cont’)

(1)


4 0.7 1 4 4 2 3 0.7IH o o IHV V V V

8 7.4 1.33 1.236

oIH o

VV V

22From (1) : 4 0.7 2 3 0.7IH o o IHV V V V

224 0.7 2 2.3IH o o IHV V V V

2solving (2) & (3) : 1.55 4.97 1.14 0o oV V

0.22oV V 1.52IHV V


(2)

(3)


2 2' '1 12 2n I t p DD I t DD o DD o

n p

W Wk V V k V V V V V V VL L

For VIL: QN is in saturation and QP in triode

2 210.7 3 0.7 3 32I I o oV V V V

2 210.7 2.3 3 32I I o oV V V V

2 0.7 2.3 3 3o oI I o o

I I I

V VV V V VV V V


(1)


and 1oI IL

I

VV VV

2 1.4 2.3 3 3IL IL o oV V V V

2 1.153IL oV V

2 21From (1) : 0.7 2.3 3 32IL IL o oV V V V

2 210.66 1.85 3.45 0.66 3 32o o o oV V V V



2.96oV V 0.81ILV V

Noise Margins:

3 1.52 1.48HNM V

0.81 0 0.81LNM V


Since QN and QP are not matched, the VTC is not symmetric


CMOS Dynamic Operation

Exact analysis is too tedious Replace all the capacitances in the circuit by a single

equivalent capacitance C connected between the output node of the inverter and ground

Analyze capacitively loaded inverter to determine propagation delay


CMOS – Dynamic Operation

1 2 1 2 3 42 2gd gd db db g g wC C C C C C C C


CMOS – Dynamic Operation


CMOS Dynamic Operation

Need interval tPHL during which vo reduces from VDD to VDD/2

/ 2av PHL DD DDI t C V V

Which gives

Iav is given by2

DDPHL

av

CVtI

12av DN DNI i E i M


CMOS Dynamic Operationwhere

2'12DN n DD tn

n

Wi E k V VL

and

' /n

PHLn DDn

Ctk W L V

2

' 12 2 2DD DD

DN n DD tnn

W V Vi M k V VL

this gives


CMOS Dynamic OperationWhere a is given by

2

2

374

n

tn tn

DD DD

V VV V

Likewise, tPLH is given by

' /p

PLHp DDp

Ct

k W L V

with 2

237

4

ptp tp

DD DD

V VV V


CMOS Dynamic OperationWhere a is given by

12P PHL PLHt t t

Components can be equalized by matching transistors tP is proportional to C reduce capacitance Larger VDD means lower tp Conflicting requirements exist


CMOS – Propagation Delay


CMOS – Propagation Delay

Capacitance C is the sum of:– Internal capacitances of QN and QP– Interconnect wire capacitance– Input of the other logic gate

'

1.6/PHL

n DDn

Ctk W L V

To lower propagation delay– Minimize C– Increase process transconductance k’– Increase W/L– Increase VDD


A CMOS inverter for which kn=10 kp=100 A/V2 and Vt =0.5 V is connected as shown to a sinusoidal signal source having a Thevenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 k. What signal voltage appears at node Awith vI = +1.5 V and vI = -1.5 V?

CMOS Inverter Problem


For vI = 1.5 V, the NMOS operates in the triode region while the PMOS is off.

6

1 1 10100 10 1.5 0.5DSn

n I t

r kk v V

3 4

4 5

100 10 10 9.0910 10Av mV

CMOS Inverter Problem (cont’)


For vI = -1.5 V, the PMOS operates with

5

61 1 10

100 10 1.5 0.510

DSPp I t

rk v V

3 5

5 5

100 10 10 5010 10Av mV

CMOS Inverter Problem (cont’)


Propagation Delay - ExampleFind the propagation delay for a minimum-size inverter for which kn’=3kp’=180 A/V2 and (W/L)n = (W/L)p=0.75 m/0.5 m, VDD = 3.3 V, Vtn = -Vtp = 0.7 V, and the capacitance is roughly 2fF/mm of device width plus 1 fF/device. What does tpbecome if the design is changed to a matched one? Use the method of average current.

2 237 7 3 0.7 0.72 2 1.734 4 3.3 3.3

tn tnn

DD DD

V VV V

Solution

'6

1.73 2 0.75 10.75/ 180 10 3.30.5

nPHL

n DDn

fF fFCtk W L V

13.38


4.85PHLt ps

Since , then 1.73tn tp n pV V

We also have , hencen p

W WL L

'

' 4.85 3 14.55nPLH PHL

n

kt t psk

1 1 4.85 14.55 9.72 2P PHL PLHt t t ps

Propagation Delay - Example


If both devices are matched, then

' 'p nk k

PLH PHLt t

and

1 4.852p PHL PLH PHLt t t t ps

Propagation Delay - Example


CMOS – Dynamic Power Dissipation

In every cycle– QN dissipate ½ CVDD

2 of energy– QP dissipate ½ CVDD

2 of energy – Total energy dissipation is CVDD

2

If inverter is switched at f cycles per second, dynamic power dissipation is: 2

D DDP fCV


Power Dissipation - Example

In this problem, we estimate the inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Let Vtn=-Vtp=0.5 V, VDD = 1.8V, and kn=kp=450A/V2. Let the input rising and falling edges be linear ramps with the 0-to-VDD and VDD-to-0 transitions taking 1 ns each. Find Ipeak.13.44


To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from Vt to VDD-Vt, and the height equal to Ipeak. Also, determine the power dissipation that results when the inverter is switched at 100 MHz.



212 2

DDPeak n ox tn

n

W VI C VL

2

2

1 1.8450 0.5 362 2Peak

AI AV



The time when the input reaches Vt is:

0.5 1 ns 0.28 ns1.8

The time when the input reaches VDD - Vt is:

1.8 0.5 1 ns 0.72 ns1.8

The base of the triangle is

0.72 0.28 0.44 ns widet



1 1 36 1.8 0.44 ns2 2Peak DDE I V t A

14.3E femtoJoules

6 15100 10 14.3 10 1.43P f E W


ECE 342 Solid State Devices Circuits 4. CMOSjsa.ece.illinois.edu/hcmut/ece342/notes/Lect_04.pdfECE...

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