ECE 546 Lecture 21 in Digital Circuits - University Of Illinoisemlab.uiuc.edu/ece546/Lect_21.pdf ·...

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ECE 546 – Jose SchuttAine 1 Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois [email protected] ECE 546 Lecture 21 Noise in Digital Circuits

Transcript of ECE 546 Lecture 21 in Digital Circuits - University Of Illinoisemlab.uiuc.edu/ece546/Lect_21.pdf ·...

Page 1: ECE 546 Lecture 21 in Digital Circuits - University Of Illinoisemlab.uiuc.edu/ece546/Lect_21.pdf ·  · 2018-03-14ECE 546 Lecture ‐21 Noise in ... ECE 546 –Jose Schutt‐Aine

ECE 546 – Jose Schutt‐Aine 1

Spring 2018

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]

ECE 546 Lecture ‐ 21

Noise in Digital Circuits

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av

C VtI

Circuit Delay

To optimize circuit performance, the goal is to reduce the capacitive loading C and potential swing V while keeping the average current drive Iav high

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•When scaling is applied (scaling factor S >1)

All horizontal and vertical dimensions of transistors are scaled down

Substrate doping is increased by S

All voltages are reduced by 1/S

Scaling of Transistors

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2

2DS ox GS TWI C V V

L

21/ 11 1/1/DS

SI S SS S

g oxC WLC

1 1 1gC S

S S S

g

av

C VI

1/ 1/ 11/S S

S S

P IV

2

1 1 1S S S

Scaling of Transistors

Drain Current Time Delay

Capacitance Power

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Dimensions (W, L, tgox, Xj) 1/SSubstrate doping (NSUB) SVoltages (VDD, VTN, VTP) 1/SCurrent per device (IDS) 1/SGate capacitance (Cg=ox WL/tgox) 1/STransistor on-resistance 1Intrinsic gate delay(=RtrCg) 1/SPower-dissipation per gate (P=IV) 1/S2

Power-delay product per gate (P ) 1/S3

Area per device (A=WL) 1/S2

Power-dissipation density (P/A) 1

S: Scaling factor for device dimensions.

Ideal Scaling of Transistors

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Optimal Chip Size• Delay Factor

– On-chip delay is usually kept much smaller than chip-to-chip delay– Choose chip delay to be 10% of chip-to-chip delay

• Optimal– If the chips are made larger, the system will become slower– If the chips are made smaller, the complexity of the package will

increase

/ 20.16 ln pack package Lo o

chipchip chip o

C A CR CAR C C

: chipA Area of chip

: packageA Area of package

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Scaling of Interconnection Capacitance

• Wiring Capacitance vs Device Capacitance– Wiring capacitance becomes more important– Transistor input capacitance decreases with reduced size– Capacitance of chip-to-chip wire is an order of magnitude larger than

on-chip capacitance

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50% ( )tr int gateT R C C

1 1( )

tr

gox DD T

R W C V VL

1/n n p pgate ox

gox

W L W LC S

t

inxt intint ox C

ox

W lC St

Scaling of Interconnection Capacitance

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Thickness (Hint) 1/S 1/ S1/2 1/ S1/2 1/SHWidth (Wint) 1/S 1/S 1/ S1/2 1/SwSeparation (Wsp) 1/S 1/S 1/ S1/2 1/SspInsulator thickness 1/S 1/ S1/2 1/S1/2 1/SoxLength (lloc) 1/S 1/S 1/S 1/SResistance (Rint) S S1/2 1 SwSH/SCapacitance to subst 1/S 1/ S3/2 1/S Sox/SSwCapacitance between lines 1/S 1/ S1/2 1/S Sox/SSHRC delay (T) 1 1/ S1/2 1/S SwSH/S2

Voltage drop (IR) 1 1/ S1/2 1/S SwSH/S2

Current density (J) S S1/2 1 SwSH/S

Parameter Ideal Quasi-Ideal Constant-R Generalized

S: Scaling factor for device dimensions.

Scaling of Local Interconnections

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Thickness (Hint) 1/S 1 SC 1/SHWidth (Wint) 1/S 1 SC 1/SwSeparation (Wsp) 1/S 1 1/S1/2 1/SspInsulator thickness (tox) 1/S 1 SC 1/SoxLength (lint) SC SC SC SCResistance (Rint) S2SC SC 1/SC SwSHSCCapacitance (Cint) SC SC SC ~SCRC delay (T) S2SC

2 SC2 1 SwSHSC

2

Ideal Constant Constant Generalized Parameter Scaling Dimension Delay Scaling

S: Scaling factor for device dimensions.SC: Scaling factor for chip size

Scaling of Global Interconnections

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Total chip current S2Sc2 S2Sc

2

Conductor thickness 1/S SSheet resistance (Rint ) S 1/SNumber of power planes 1 SNumber of power connections 1 SSC

2

Effective resistance S 1/S3SC2

IR voltage drop S3SC2 1/S

Signal-to-noise ratio 1/S4SC2 1

Ideal ImprovedParameter scaling Scaling

S: Scaling factor for device dimensions.SC: Scaling factor for chip size

Scaling of IR Voltage Drops

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• Severity is reduced by– Off-chip wires have larger inductance– Their current demand does not increase as fast– Their large size allow easy decoupling– In general off-chip transients are slower– TAB and flip-chip technology can improve

Effect of Scaling on Signal-to-Noise Ratio

Signal-to-noise (S/N) ratio is reduced by:

This is an alarming ratio

4 3CS S

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• Crosstalk Between Capacitive Lines– Primarily on chip– Major effect is increase in delay

• Crosstalk Between Transmission Lines– Distributed and wave effects– Approximate as near and far end crosstalks

• Signal return Crosstalk– Imperfect ground reference– Unbalanced currents

Different Types of Crosstalk

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Coupling to Floating Line

– Important when high-swing signal passes near a low-swing pre-charged signal (e.g. RAM)

Cc

O C

CkC C

kc is capacitive coupling coefficient

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Coupling to Driven Line

– Transient decays with a time constant ( )xc o C oR C C

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• Signals on adjacent layers should be routed in perpendicular directions

• Avoid floating signals

• Make rise time as large as possible

• Crosstalk can be made common mode by routing true and complement lines close to each other

• Provide shielding by placing conductors tied to GND and reference

Capacitive Crosstalk Countermeasures

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IC package modeled as lumped 5 nH inductor will house 128 full swing (3.3V) outputs into 50- lines with 1 ns rise time

– How many return pins are needed if drop across returns must be less than 300 mV?

– How many pins if rise time is reduced to 3 ns?

t

V

Example

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– When rise time is 3 nsL InV t

46.9n

At least 46 pins

Solution

3.3128 128 8.4450

VI AR

300 300 0.355I IL V mV L nHt t

0.355 140.8L nH nn 141 pins

Assume current ramp same as voltage ramp

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Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March 1998

Vertical parallel-plate capacitance 0.05 fF/m2

Vertical parallel-plate capacitance (min width) 0.03 fF/mVertical fringing capacitance (each side) 0.01 fF/mHorizontal coupling capacitance (each side) 0.03

IC Wiring

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Metal 5

Metal 4

Metal 3Metal 2

Metal 1

Substrate

Vertical parallel-plate capacitance 0.05 fF/m2

Vertical parallel-plate capacitance (min width) 0.03 fF/mVertical fringing capacitance (each side) 0.01 fF/mHorizontal coupling capacitance (each side) 0.03

Integrated Circuit Wiring

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• Crosstalk current due to mutual capacitance will split into 2 parts and flow toward both ends of victim line

• Crosstalk current due to mutual inductance will flow from the far end toward the near end of victim line

Near‐ and Far‐End Crosstalks

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Transmission-Line - Crosstalk

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• Crosstalk seen on the victim line at the end closest to the driver

• Assumes that load is terminated with characteristic impedance of single isolated line

• Sum of contributions to reverse traveling wave that arrives at point x during period equal to time of flight

Near End Crosstalk

( ) ( )near m near mI I L I C

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• Approximate quantity

• Assumes that load is terminated with characteristic impedance of single isolated line

• Sum of contributions to reverse traveling wave that arrives at point x during period equal to time of flight

Near End Crosstalk

4

cx lxrx

k kk

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• Crosstalk seen on the victim line at the end farthest away from the driver

• Assumes that load is terminated with characteristic impedance of single isolated line

Far End Crosstalk

( ) ( )far far m mI I C I L

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• Approximate quantity

• Assumes that load is terminated with characteristic impedance of single isolated line

• Time derivative of signal on line A scaled by forward-coupling coefficient and coupling time

Far End Crosstalk

4cx lx

fxk kk

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2 X LC

Digital Crosstalk ‐ Case 1

X LC

( )4

M MV input L CAL C

( )

2M MV input X LC L CB

T L Cr

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2 X LC

Digital Crosstalk ‐ Case 2

V(far)

0

DTr

X LC

( )4

M MV input L CAL C

( )M M

V input X LC L CD Tr L C

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2 X LC

Digital Crosstalk ‐ Case 3

Tr

V(far)

0 TrB

D

X LC

3 X LC

( )2

M MV input L CAL C

4

M MV L CD

L C

( )2

M MV input X LC L CB Tr L C

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• If the rise or fall time is short compared to the delay of the line, the near-end crosstalk noise is independent of the rise time.

• If the rise or fall time is long compared to the delay of the line, the near-end crosstalk noise is dependent on the rise time

• The far-end crosstalk is always dependent on the rise or fall time

Crosstalk Facts

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• Assume that the transmission lines are terminated

• The near-end crosstalk will begin at t=0 and have a duration of 2 tD.

• The far-end crosstalk will occur at time t=tD and have a duration approximately equal to the signal rise or fall time

Crosstalk Facts

Dt X LC

X is the length of the lines

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9.869 2.103( / .)

2.103 9.869L nH in

2.051 0.239( / .)

0.239 2.051C pF in

Example ‐ Determine Near‐ and Far‐End Crosstalk

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Solution

12 12

11 11

( ) 1 2.103 nH 0.239 pF(1) 0.082 V4 4 9.869 nH 2.051 pF

V input L CVL C

12 12

11 11

( )V(2)=-

2

V input X LC L CT L Cr

1 2 (9.869 nH)(2.051 pF) 2.103 nH 0.239 pFV(2)=- 0.137 V2(100 ps) 9.869 nH 2.051 pF

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• High-swing signals should not be routed on lines immediately

• Match klx and kcx to eliminate far end crosstalk

• If kfx is nonzero, avoid long parallel lines

• Terminate with Zs

• Make rise time as long as possible

TL Crosstalk Countermeasures

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• Signal launched on a transmission line can be affected by previous signals as result of reflections

• ISI can be a major concern especially if the signal delay is smaller than twice the time of flight

• ISI can have devastating effects

• Noise must be allowed to settled before next signal is sent

Intersymbol Interference (ISI)

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Volts

Time

Waveform beginning transition from low to highwith unsettled noise on the bus

Different starting point due to ISI

Receiver switching threshold

Timing differencedue to ISI

Ideal waveform beginning transistionfrom low to high with no noise on the bus

Intersymbol Interference

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-2

-1

0

1

2

3

4200 MHz switching on above bus

400 MHz switching on above bus

Ideal 400 MHz waveformTime

Probe pointZo = 65 ohms30 ohms

V

Intersymbol Interference and Signal Integrity

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• Minimize reflections on the bus by avoiding impedance discontinuities

• Minimize stub lengths and large parasitics from package sockets or connectors

• Keep interconnects as short as possible (minimize delay)

• Minimize crosstalk effects

Minimizing ISI