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EC6302 DIGITAL ELECTRONICS L T P C3 0 0 3

OBJECTIVES:

To introduce basic postulates of Boolean algebra and shows the correlation between Boolean

expressions

To introduce the methods for simplifying Boolean expressions

To outline the formal procedures for the analysis and design of combinational circuits

and sequential circuits

To introduce the concept of memories and programmable logic devices.

To illustrate the concept of synchronous and asynchronous sequential circuits

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9Minimi!"i#n T$%&ni'($): Boolean postulates and laws De-organ!s Theorem - "rinciple ofDuality - Boolean expression - inimi#ation of Boolean expressions interm axterm -$um of "roducts %$&"' "roduct of $ums %"&$' (arnaugh map inimi#ation Don!t careconditions )uine - c *lus+ey method of minimi#ation.L#*i% G!"$): ,D &/ &T ,D &/ 0xclusive&/ and 0xclusive&/1mplementations of 2ogic 3unctions using gates ,D&/ implementations ulti levelgate implementations- ulti output gate implementations. TT2 and *&$ 2ogic and theircharacteristics Tristate gates

UNIT II COMBINATIONAL CIRCUITS 9Design procedure 4alf adder 3ull ,dder 4alf subtractor 3ull subtractor "arallel binaryadder parallel binary $ubtractor 3ast ,dder - *arry 2oo+ ,head adder $erial ,dder5$ubtractor - B*D adder Binary ultiplier Binary Divider - ultiplexer5 Demultiplexer decoder - encoder parity chec+er parity generators code converters agnitude*omparator.

UNIT III SEQUENTIAL CIRCUITS 92atches 3lip-flops - $/ 6( D T and aster-$lave *haracteristic table and equation

,pplication table 0dge triggering 2evel Triggering /eali#ation of one flip flop using otherflip flops serial adder5subtractor- ,synchronous /ipple or serial counter ,synchronous

7p5Down counter - $ynchronous counters $ynchronous 7p5Down counters "rogrammablecounters Design of $ynchronous counters: state diagram- $tate table $tate minimi#ation $tate assignment 0xcitation table and maps-*ircuit implementation - odulon counter/egisters shift registers - 7niversal shift registers $hift register counters /ing counter $hift counters - $equence generators.

UNIT IV MEMOR+ DEVICES 9*lassification of memories /& - /& organi#ation - "/& 0"/& 00"/& 0,"/& /, /, organi#ation 8rite operation /ead operation emory cycle -Timing wave forms emory decoding memory expansion $tatic /, *ell- Bipolar /,cell &$30T /, cell Dynamic /, cell "rogrammable 2ogic Devices "rogrammable2ogic ,rray %"2,' - "rogrammable ,rray 2ogic %",2' 3ield "rogrammable 9ate ,rrays

%3"9,' - 1mplementation of combinational logic circuits using /& "2, ",2

UNIT V S+NCHRONOUS AND AS+NCHRONOUS SEQUENTIAL CIRCUITS 9S,n%&-#n#() S$'($n"i!. Ci-%(i"): 9eneral odel *lassification Design 7se of

,lgorithmic $tate achine ,nalysis of $ynchronous $equential *ircuitsA),n%&-#n#() S$'($n"i!. Ci-%(i"): Design of fundamental mode and pulse mode circuits 1ncompletely specified $tate achines "roblems in ,synchronous *ircuits Design of 4a#ard3ree $witching circuits. Design of *ombinational and $equential circuits using 0/12&9.

TOTAL: / PERIODS

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