Dynamic Data Stability in Low-power SRAM Design

Mohammad Sharifkhani, Shah M. Jahinuzzaman and Manoj Sachdev

Electrical & Computer Engineering

University of Waterloo, Waterloo, ON, Canada

2

Background

• Static Noise Margin (SNM) is based on – static criteria– worst case static noise

Static Criteria for Data Stability

[Hill, 1968]

Worst Case Static Noise Source

[Lohstroh, 1983][Seevinck, 1986]

Static Noise Margin(SNM)

3 DC solutions

Vn

VAVB

Vn

VA

VB

I +

I +

3

• Analysis of non-linear system by state-space– differential equations– discontinuity of MOS I/V

characteristics: use of subthreshold operation for continuity

• Different sets of eq. for accessed and non-accessed modes

BLBL

VH

VGND (VL)

Cg

Cg

Cgd

Cdg

Cgs

Capacitances affected by change in cell VGND voltage

VH

VL

VL

VH

M1 M2

M3 M4

M5 M6

WL

Leaking transistor in retention mode

WL

A

B

VDD VDD

VSSVSS

VS

S

VS

S

3 1

4 2

B

A

dVC I IdtdV

C I Idt

3

1

2

4

(1 )

(1 )

(1 )

(1 )

H B Tp H A

t t

B L Tn A L

t t

A L Tn B L

t t

A L Tp H B

t t

V V V V V

nV nVop

V V V V V

nV nVon

V V V V V

nV nVon

V V V V V

nV nVop

I I e e

I I e e

I I e e

I I e e

SRAM Cell: Non-linear System

4

• Non-linear system– multiple stable or DC points

• region of convergence– time domain solutions relies on initial conditions

• trajectories

• While non-accessed – 2 Uniformly Asymptotic Stable (UAS) points– 1 saddle point

State-space Analysis of Cell

• No discontinuity in state variable V – finite admittance of

access transistors

5

• Shadow of the ball on 2D state space: trajectory

• 3 stable points• Final DC solution

depends on initial location of the ball

VB

VA

S1

SM

Ball

Shadow of the ball: representing the state of the cell

S0

SM

Analogy with Saddle

6

• Data unstablity: state of cell moves away from the RoC of the original UAS point determined in non-accessed mode– occurs if the accessed cell has only one UAS

point that resides out of the original RoC

S0

SM

VA

VB

S1

RoC of S1

RoC of S0

X

X

M

DC Curve non-accessed

DC Curve accessed

DC Stable point accessed

DC Stable point non-accessed

Taccess

Tnon-access

Trajectory during the access and non-access time

Data Unstability in SRAM Cell

7

• State of cell never leaves the RoC of original logic state– existence of a periodic solution for the PTV-NL cell

within each RoC of UAS point

• Worst case scenario: infinite access transactions

RoC of Φ0

in hyper-plane t0

S0

S1

SM

S0a

S1a

SMa

Cell A

M

Cell B

Region of attraction of periodic solution ΦM(t)

in hyper-plane t0

Φ0(t)

Φ1(t)

ΦM(t)

DC transfer functions for a non accessed cell

DC transfer functions for an accessed cell

A UAS point

The periodic solution of the system in the corresponding region of attraction

v1

v2

v1

v2

S0

S1

SM

Φ0(t)

Φ1(t)

ΦM(t)

RoC of Φ1

in hyper-plane t0

RoC of Φ0

in hyper-plane t0Ta

Tr

Ta

Tr

tt0

2-dimensional SS in hyper-plane t0

RoC of Φ1

in hyper-plane t0

Dynamic Data Stability Criteria

8

• The periodic solutions are convergent – don’t have to solve the PTV-NL for all initial

conditions (despite being a nonlinear system)– the solution will attract the trajectory, if exists– the initial condition should be in the RoC of

periodic solution

• Proof: beyond the scope of this presentation

Properties of Trajectories

9

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.880

100

120

140

160

180

200

220

SN

MD

(m

V)

Ta = 0.5 ns

Ta = 1 ns

Ta = 2 ns

Conv (SNM)

VL (V)

VH=1.2V VWL=1.2V

• SNM redefined as SNMD: same noise sources, but dynamic criteria

• In subthreshold region, lower cell access time results in higher SNMD

Static Noise Margin using Dynamic Criteria

10

• Segmented Virtual Grounding (SVGND) scheme is proposed– low-leakage– low-write power

• higher write NM– low excess power on non-selected BL– minor speed trade-off– four distinct operational modes

1. Retention 2. Read3. Accessed retention 4. Write

Application in Low-power SRAM

11

• Array is in hibernation

VH – VL = 0.4V

• No multiple VTs!

• Body effect minimizes leakage

• Potential issue: data stability– weak drive transistors

BL

BL

WL

VH

SVG(Nominal voltage:VL)

WL

VSS

VSS

VDD

VSS

VSS

VDD

AB

M1

M4 M3

M5

M6M2

VH

VHVH

VH

VSSVSS

VL

VL

Retention Mode

12

Simulation & Measurement Results

• Measurement results– Leakage current

reduces significantly

• Stability simulation results– SNM (220mV)

• Sub-threshold operation (~22pA/Cell)

0.0

100.0p

200.0p

300.0p

400.0p

500.0p

600.0p

700.0p

0.0 0.2 0.4 0.6 0.8 1.0 1.20.0

0.2

0.4

0.6

Leak

age

curr

ent/c

ell(A

)

Voltage drop over the cell (V)

SN

M(V

)

13

• Multiple words/row• Only selected word

enters this mode– SVG becomes VSS– bitline discharges via

access & driver transistors

• Good data stability– voltage across cell ≈ VH

– VB-VA > VH-VL

Read Mode

14

• Non-selected words (BLs) on selected row enters this mode– high VWL

– no SVG variation– no bitline discharge

• Minimum access leakage• Issue: data stability

– Vwl= VH+Vtha-VΔ

– VΔ> 200mV

– recovery after access

Accessed Retention Mode

15

• Low BL voltage swing– VWR Sufficiently below VH-VΔ

– VWR= VL

– BL swing, VBL ≈ 400 mV

• Low power consumption

– Pwrite ∝ VH. VBL

– no SVG variation

Write Mode

16

SVGND Architecture• Constitute the OP modes

• Small area overhead

• Column based– Sharing SVG

• Nominal VL , access Vcvg

• SS / WL : simultaneous– Connection to CVG

– Sharing CVG• High metal layer (low cap)

• Nominal VL , read VSS

SAC

olum

n D

ecod

er

Col

umn

Virt

ual

Gro

und

(CV

G)

Se

gmen

t 0S

egm

ent 1

Se

gmen

t M

Se

gmen

t Se

lect

0 (

SS

0)

SS1

SSM

BLBL

WL1

WL2

WLN

VL

VL

VL

VL

READ

SV

GS

VG

SV

GS

VG

0

SV

GM

SW

SW

C

VH

SV

G

VH

SV

G

CELL N

VH

SV

G

VL

CV

G (

Hig

h m

etal

laye

r, n

omin

al

volta

ge V

L ex

cpet

for

read

ope

ratio

n)

SS

Segment VG switch(SW)

CELL 2

CELL 1

WL2

WL1

WLN

BL

BL

17

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

SS0

SS1

Seg

men

t

Seg

men

t

Seg

men

tSSi

Pos

t Dec

oder

Pre

-dec

oder

1P

re-d

ecod

er 2

Pos

t Dec

oder

Pos

t Dec

oder

Row Address

Row decoder

Column Decoder

SA SA

Column Address READ

M

CV

GC

VG

CV

G

CV

G

CV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

GS

VG

SV

G

CV

G

CV

GC

VG

CV

GSA

Col

umn

D

ecod

er

Col

umn

Virt

ual

Gro

und

(CV

G)

Seg

men

t 0S

egm

ent

1S

egm

ent M

Seg

men

t Sel

ect 0

(SS 0

)

SS1

SSM

BLBL

WL1

WL2

WLN

VL

VL

VL

VL

READ

SV

GS

VG

SV

GS

VG

0

SV

GM

SW

SW

C

VH

SV

G

VH

SV

G

CELL N

VH

SV

G

VL

CV

G (H

igh

met

al la

yer,

nom

inal

vo

ltage

VL

exc

pet f

or re

ad o

pera

tion)

SS

Segment VG switch(SW)

CELL 2

CELL 1

WL2

WL1

WLN

BL

BL

WL1

SVGND Architecture

18

SVGND Architecture• Post Dec: AND• No additional HW

for SS• CVG and BL

voltage variation: – Only to-be-read

columns

– Others: AR-mode

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

Seg

men

tS

egm

ent

BLBL

SS0

SS1

Seg

men

t

Seg

men

t

Seg

men

t

SSi

Pos

t Dec

oder

Pre

-dec

oder

1P

re-d

ecod

er 2

Pos

t Dec

oder

Pos

t Dec

oder

Row Address

Row decoder

Column Decoder

SA SA

Column Address READ

M

CV

GC

VG

CV

G

CV

G

CV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

G

SV

GS

VG

SV

G

CV

G

CV

GC

VG

CV

G

19Size of per bit array (Rows x Columns/wordsize)

0

200

400

600

800

1000

1200

1400fJ

/Writ

e/bi

t

SACSVGNDHBLSACONV

256x4 256x8 512x8 512x16128x4

Comparison: Write

20

BLRBLR

WL

QRQR

BLA

BLA

QA QA

BLW

BLW

WL

QWQW

BLA

BLA

QA QA

Cell Accessed for Read

Adjacent Cell on the same row

Cell Accessed for Write

Adjacent Cell on the same row

>200mV

>130mV 400mV

Read Operation Write Operation

Simulated Waveforms

21

Silicon Implementation

• Array size: 2048x20bit

• 130nm CMOS

• 4 arrays– Each 150um x 410um

• 8% area overhead

• Fclk>50MHz

Cell

SVG Switch

150um

410u

m

22

SVGND Meas. Results

• Normalized voltage & freq.

• Less area overhead compared to JSSC’04(11%) and ISSCC’06(66%) and JSSC’05(18%)

• Ability to accommodate Multiple words/row 0

50100

150200

250300

89

1011

1213

0.5

1

1.5

2

2.5

3

3.5

x 10 -11

Word size (bits)Address size (bits)

Writ

e E

nerg

y (J

/Ope

ratio

n)

SVGND

Conv.

Hitachi*, JSSC’06

Samsung, JSSC’05

MIT*, ISSCC’06

Fujitsu, JSSC’04

4

* only relative energy saving compared to the conventional scheme is reported