DRV8303 Three-Phase Gate Driver With Dual-Current Shunt ... · PWM DRV8303 6 to 60 V MCU N-Channel...

DRV8303PWM

6 to 60 V

MC

U

N-C

hann

el

MO

SF

ET

s

Gate Drive

Sense

3-Phase Brushless Pre-Driver

Dual Shunt Amps

SPI

nFAULT

nOCTW

Diff Amps

M

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

ReferenceDesign

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8303SLOS846C –SEPTEMBER 2013–REVISED DECEMBER 2016

DRV8303 Three-Phase Gate Driver With Dual-Current Shunt Amplifiers

1

1 Features1• 6-V to 60-V Operating Supply Voltage Range• 1.7-A Source and 2.3-A Sink Gate Drive Current

Capability• Slew Rate Control for EMI Reduction• Bootstrap Gate Driver With 100% Duty Cycle

Support• 6 or 3 PWM Input Modes• Dual Integrated Current-Shunt Amplifiers With

Adjustable Gain and Offset• 3.3-V and 5-V Interface Support• Serial Peripheral Interface (SPI)• Protection Features:

– Programmable Dead Time Control (DTC)– Programmable Overcurrent Protection (OCP)– PVDD and GVDD Undervoltage Lockout

(UVLO)– GVDD Overvoltage Lockout (OVLO)– Overtemperature Warning/Shutdown

(OTW/OTS)– Reported through nFAULT, nOCTW, and SPI

Registers

2 Applications• 3-Phase BLDC and PMSM Motors• CPAP and Pump• E-Bikes• Power Tools• Robotics and RC Toys• Industrial Automation

3 DescriptionThe DRV8303 is a gate driver IC for three-phasemotor-drive applications. The device provides threehalf bridge drivers, each capable of driving two N-channel MOSFETs. The device supports up to 1.7-Asource and 2.3-A peak current capability. TheDRV8303 can operate off of a single power supplywith a wide range from 6-V to 60-V. It uses abootstrap gate-driver architecture with trickle chargecircuitry to support 100% duty cycle. The DRV8303uses automatic hand shaking when the high-side orlow-side MOSFET is switching to prevent currentshoot through. Integrated VDS sensing of the high-side and low-side MOSFETs is used to protect theexternal power stage against overcurrent conditions.

The DRV8303 includes two current-shunt amplifiersfor accurate current measurement. The amplifierssupport bi-directional current sensing and provide andadjustable output offset up to 3 V.

The serial peripheral interface (SPI) provides detailedfault reporting and flexible parameter settings such asgain options for the current-shunt amplifiers and slew-rate control of the gate drivers.

Device Information(1)PART NUMBER PACKAGE BODY SIZE (NOM)

DRV8303 TSSOP (48) 12.50 mm × 6.10 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Schematic

http://www.ti.com/product/drv8303?qgpn=drv8303http://www.ti.com/product/DRV8303?dcmp=dsproject&hqs=pfhttp://www.ti.com/product/DRV8303?dcmp=dsproject&hqs=sandbuysamplebuyhttp://www.ti.com/product/DRV8303?dcmp=dsproject&hqs=tddoctype2http://www.ti.com/product/DRV8303?dcmp=dsproject&hqs=swdesKithttp://www.ti.com/product/DRV8303?dcmp=dsproject&hqs=supportcommunityhttp://www.ti.com/tool/tida-00436?dcmp=dsproject&hqs=rd

2

DRV8303SLOS846C –SEPTEMBER 2013–REVISED DECEMBER 2016 www.ti.com

Product Folder Links: DRV8303

Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 56.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 66.4 Thermal Information .................................................. 66.5 Electrical Characteristics........................................... 66.6 Current Shunt Amplifier Characteristics.................... 86.7 SPI Characteristics (Slave Mode Only)..................... 86.8 Gate Timing and Protection Switching

Characteristics ........................................................... 96.9 Typical Characteristics ............................................ 10

7 Detailed Description ............................................ 117.1 Overview ................................................................. 117.2 Functional Block Diagram ....................................... 127.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 177.5 Programming........................................................... 197.6 Register Maps ......................................................... 20

8 Application and Implementation ........................ 228.1 Application Information............................................ 228.2 Typical Application ................................................. 23

9 Power Supply Recommendations ...................... 269.1 Bulk Capacitance .................................................... 26

10 Layout................................................................... 2710.1 Layout Guidelines ................................................. 2710.2 Layout Example .................................................... 28

11 Device and Documentation Support ................. 2911.1 Documentation Support ........................................ 2911.2 Receiving Notification of Documentation Updates 2911.3 Community Resources.......................................... 2911.4 Trademarks ........................................................... 2911.5 Electrostatic Discharge Caution............................ 2911.6 Glossary ................................................................ 29

12 Mechanical, Packaging, and OrderableInformation ........................................................... 29

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2015) to Revision C Page

• Added the maximum voltage difference and maximum voltage parameters for the BST_X, GH_X, SL_X, and SH_Xpins in the Absolute Maximum Ratings table ......................................................................................................................... 5

• Added the Documentation support and Receiving Notification of Documentation Updates sections ................................. 29

Changes from Revision A (October 2013) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Updated title............................................................................................................................................................................ 1• VPVDD absolute max voltage rating reduced from 70 V to 65 V ............................................................................................. 5• Clarification made on how the OCP status bits report in Overcurrent Protection (OCP) and Reporting ............................ 15• Update to PVDD undervoltage protection in Undervoltage Protection (UVLO) describing specific transient brownout

issue. .................................................................................................................................................................................... 16• Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse lengths. ................ 17• Added gate driver power-up sequencing errata .................................................................................................................. 22

http://www.ti.com/product/drv8303?qgpn=drv8303http://www.ti.comhttp://www.ti.com/product/drv8303?qgpn=drv8303http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS846C&partnum=DRV8303

GN

D (

49)

- P

WR

_PA

D

8

1

2

3

4

5

6

7

9

10

11

12

13

14

22

15

16

17

18

19

20

21

23

24

41

48

47

46

45

44

43

42

40

39

38

37

36

35

27

34

33

32

31

30

29

28

26

25

nOCTWnFAULT

DTCnSCS

SDI

DC_CAL

SDOSCLK

GVDDCP1CP2

EN_GATEINH_AINL_AINH_BINL_BINH_CINL_CDVDD

REFSO1SO2

AVDDAGND

GNDGNDGNDVDD_SPIBST_A

GL_A

GH_ASH_A

SL_ABST_BGH_BSH_BGL_BSL_BBST_CGH_CSH_CGL_CSL_CSN1SP1SN2SP2PVDD

3

DRV8303www.ti.com SLOS846C –SEPTEMBER 2013–REVISED DECEMBER 2016


Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

DCA Package48-Pin TSSOP Pad Down

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNO. NAME

1 nOCTW O Overcurrent and overtemperature warning indicator. This output is open drain with external pullupresistor required. Programmable output mode through SPI registers.2 nFAULT O Fault report indicator. This output is open drain with external pullup resistor required.3 DTC I Dead-time adjustment with external resistor to GND4 nSCS I SPI chip select5 SDI I SPI input6 SDO O SPI output7 SCLK I SPI clock signal

8 DC_CAL I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offsetcalibration can be done through external microcontroller.9 GVDD P Internal gate driver voltage regulator. GVDD cap should connect to GND10 CP1 P Charge pump pin 1, ceramic cap should be used between CP1 and CP211 CP2 P Charge pump pin 2, ceramic cap should be used between CP1 and CP212 EN_GATE I Enable gate driver and current shunt amplifiers.13 INH_A I PWM Input signal (high side), half-bridge A14 INL_A I PWM Input signal (low side), half-bridge A15 INH_B I PWM Input signal (high side), half-bridge B16 INL_B I PWM Input signal (low side), half-bridge B17 INH_C I PWM Input signal (high side), half-bridge C18 INL_C I PWM Input signal (low side), half-bridge C


4




Pin Functions (continued)PIN

I/O DESCRIPTIONNO. NAME

19 DVDD P Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified todrive external circuitry.

20 REF I Reference voltage to set output of shunt amplifiers with a bias voltage which equals to half of thevoltage set on this pin. Connect to ADC reference in microcontroller.21 SO1 O Output of current amplifier 122 SO2 O Output of current amplifier 2

23 AVDD P Internal 6-V supply voltage, AVDD capacitor should always be installed and connected to AGND. This isan output, but not specified to drive external circuitry.24 AGND P Analog ground pin

25 PVDD P Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD cap shouldconnect to GND

26 SP2 I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to groundside of the sense resistor for the best common mode rejection.27 SN2 I Input of current amplifier 2 (connecting to negative input of amplifier).

28 SP1 I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to groundside of the sense resistor for the best common mode rejection.29 SN1 I Input of current amplifier 1 (connecting to negative input of amplifier).

30 SL_C I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin andSH_C.31 GL_C O Gate drive output for Low-Side MOSFET, half-bridge C

32 SH_C I High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin andPVDD.33 GH_C O Gate drive output for High-Side MOSFET, half-bridge C34 BST_C P Bootstrap capacitor pin for half-bridge C

35 SL_B I Low-Side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin andSH_B.36 GL_B O Gate drive output for Low-Side MOSFET, half-bridge B

37 SH_B I High-Side MOSFET source connection, half-bridge B. High-side VDS measured between this pin andPVDD.38 GH_B O Gate drive output for High-Side MOSFET, half-bridge B39 BST_B P Bootstrap cap pin for half-bridge B

40 SL_A I Low-Side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin andSH_A.41 GL_A O Gate drive output for Low-Side MOSFET, half-bridge A

42 SH_A I High-Side MOSFET source connection, half-bridge A. High-side VDS measured between this pin andPVDD.43 GH_A O Gate drive output for High-Side MOSFET, half-bridge A44 BST_A P Bootstrap capacitor pin for half-bridge A45 VDD_SPI I SPI supply pin to support 3.3V or 5V logic. Connect to either 3.3V or 5V.469

GNDO

GND pin. The exposed power pad must be electrically connected to ground plane through soldering toPCB for proper operation and connected to bottom side of PCB through vias for better thermalspreading.

4748

49 GND(PWR_PAD)


5




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

VPVDDSupply voltage Relative to PGND –0.3 65 VMaximum supply-voltage ramp rate Voltage rising up to PVDDMAX 1 V/µs

VPGND Maximum voltage between PGND and GND –0.3 0.3 VVOPA_IN Voltage for SPx and SNx pins –0.6 0.6 V

VLOGICInput voltage for logic and digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C,EN_GATE, SCLK, SDI, SCS, DC_CAL) –0.3 7 V

VGVDD Maximum voltage for GVDD pin 13.2 VVAVDD Maximum voltage for AVDD pin 8 VVDVDD Maximum voltage for DVDD pin 3.6 VVVDD_SPI Maximum voltage for VDD_SPI pin 7 V

VSDO Maximum voltage for SDO pinVDD_SPI

+0.3 V

VREF Maximum reference voltage for current amplifier 7 VVBST_MAX Maximum voltage for BST_X Pin –0.3 80 VVBST_DIFF Maximum voltage difference for (BST_X-SH_X) and (BST_X-GH_X) –0.3 14.5 VVGH_MAX Maximum voltage for GH_X pin –0.3 80 VVGH_DIF Maximum voltage difference for (GH_X-SH_X) –0.3 14.5 VVGL_MAX Maximum voltage for GL_X pin –0.3 13.2 VVGL_DIF Maximum voltage difference for (GL_X-SL_X) –0.3 13.2 VVSH_MAX Maximum voltage for SH_X pin –2 PVDD + 2 VVSL_MAX Maximum voltage for SL_X pin –0.6 0.6 V

IIN_MAXMaximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B,INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC) –1 1 mA

ISINK_MAX Maximum sinking current for open-drain pins (nFAULT and nOCTW pins) 7 mAIREF Maximum current for REF pin 100 µATstg Storage temperature –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500


6




6.3 Recommended Operating ConditionsOver operating free-air temperature range (unless otherwise noted).

MIN NOM MAX UNITVPVDD DC supply voltage PVDD for normal operation Relative to PGND 6 60 VIDIN_EN Input current of digital pins when EN_GATE is high 100 µAIDIN_DIS Input current of digital pins when EN_GATE is low 1 µACO_OPA Maximum output capacitance on outputs of shunt amplifier 20 pF

RDTCDead time control resistor. Time range is 50 ns (–GND) to 500 ns (150 kΩ) with a linearapproximation. 0 150 kΩ

IFAULT nFAULT pin sink current. Open drain V = 0.4 V 2 mAIOCTW nOCTW pin sink current. Open drain V = 0.4 V 2 mAVREF External voltage reference voltage for current shunt amplifiers 2 6 V

fgate Operating switching frequency of gate driverQg(TOT) = 25 nC or total 30-mA gatedrive average current 200 kHz

Igate Total average gate drive current 30 mATA Ambient temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)DRV8303

UNITDCA (TSSOP)48 PINS

RθJA Junction-to-ambient thermal resistance 30.3 °C/WRθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/WRθJB Junction-to-board thermal resistance 17.5 °C/WψJT Junction-to-top characterization parameter 0.9 °C/WψJB Junction-to-board characterization parameter 7.2 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W

6.5 Electrical CharacteristicsPVDD = 6 V to 60 V, TC = 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS MIN TYP MAX UNITINPUT PINS: INH_X, INL_X, SCS, SDI, SCLK, EN_GATE, DC_CALVIH High input threshold 2 VVIL Low input threshold 0.8 VRPULL_DOWN – INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTSREN_GATE Internal pulldown resistor for EN_GATE 100 kΩ

RINH_XInternal pulldown resistor for high sidePWMs (INH_A, INH_B, and INH_C) EN_GATE high 100 kΩ

RINH_XInternal pulldown resistor for low side PWMs(INL_A, INL_B, and INL_C) EN_GATE high 100 kΩ

RSCS Internal pulldown resistor for nSCS EN_GATE high 100 kΩRSDI Internal pulldown resistor for SDI EN_GATE high 100 kΩRDC_CAL Internal pulldown resistor for DC_CAL EN_GATE high 100 kΩRSCLK Internal pulldown resistor for SCLK EN_GATE high 100 kΩOUTPUT PINS: nFAULT AND nOCTWVOL Low-output threshold IO = 2 mA 0.4 V

VOH High-output thresholdExternal 47-kΩ pullup resistor connectedto 3-5.5 V 2.4 V

http://www.ti.com/product/drv8303?qgpn=drv8303http://www.ti.comhttp://www.ti.com/product/drv8303?qgpn=drv8303http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS846C&partnum=DRV8303http://www.ti.com/lit/pdf/spra953

7




Electrical Characteristics (continued)PVDD = 6 V to 60 V, TC = 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) Reduced AVDD voltage range results in limitations on settings for overcurrent protection. See Table 12.

IOHLeakage current on open drain pins whenlogic high (nFAULT and nOCTW) 1 µA

GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C

VGX_NORM Gate driver Vgs voltage

PVDD = 8V to 60 V, Igate = 30 mA,CCP = 22 nF

9.5 11.5V

PVDD = 8 V to 60 V, Igate = 30 mA,CCP = 220 nF

9.5 11.5

VGX_MIN Gate driver Vgs voltage


8.8V


8.3

Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 1.7 AIosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 AIoso2 Source current setting 2, peak Vgs of FET equals to 2 V. REG 0x02 0.7 AIosi2 Sink current setting 2, peak Vgs of FET equals to 8 V. REG 0x02 1 AIoso3 Source current setting 3, peak Vgs of FET equals to 2 V. REG 0x02 0.25 AIosi3 Sink current setting 3, peak Vgs of FET equals to 8 V. REG 0x02 0.5 A

Rgate_offGate output impedance during standbymode when EN_GATE low (pins GH_x,GL_x)

1.6 2.4 kΩ

SUPPLY CURRENTSIPVDD_STB PVDD supply current, standby EN_GATE is low. PVDD = 8 V 20 50 µA

IPVDD_OP PVDD supply current, operatingEN_GATE is high, no load on gate driveoutput, switching at 10 kHz,100-nC gate charge

15 mA

IPVDD_HIZ PVDD supply current, Hi-Z EN_GATE is high, gate not switching 2 5 10 mAINTERNAL REGULATOR VOLTAGE

AVDD AVDD voltagePVDD = 8 V to 60 V 6 6.5 7

VPVDD = 6 V to 8 V 5.5 6

DVDD DVDD voltage 3 3.3 3.6 VVOLTAGE PROTECTIONVPVDD_UV Undervoltage protection limit, PVDD 6 VVGVDD_UV Undervoltage protection limit, GVDD 7.5 VVGVDD_OV Overvoltage protection limit, GVDD 16 VCURRENT PROTECTION, (VDS SENSING)

VDS_OC Drain-source voltage protection limitPVDD = 8 V to 60 V 0.125 2.4

VPVDD = 6 V to 8 V (1) 0.125 1.491

TOC OC sensing response time 1.5 µs

TOC_PULSEnOCTW pin reporting pulse stretch length forOC event 64 µs

TEMPERATURE PROTECTION

OTW_CLR Junction temperature for resetting overtemperature warning 115 °C

OTW_SET/OTSD_CLR

Junction temperature for over temperaturewarning and resetting over temperature shutdown

130 °C

OTSD_SET Junction temperature for over temperatureshut down 150 °C


8




6.6 Current Shunt Amplifier CharacteristicsOver operating free-air temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITG1 Gain option 1 Tc = –40°C to 125°C 9.5 10 10.5 V/VG2 Gain option 2 Tc = –40°C to 125°C 18 20 21 V/VG3 Gain Option 3 Tc = –40°C to 125°C 38 40 42 V/VG4 Gain Option 4 Tc = –40°C to 125°C 75 80 85 V/VTsettling Settling time to 1% Tc = 0 to 60°C, G = 10, Vstep = 2 V 300 nsTsettling Settling time to 1% Tc = 0 to 60°C, G = 20, Vstep = 2 V 600 nsTsettling Settling time to 1% Tc = 0 to 60°C, G = 40, Vstep = 2 V 1.2 µsTsettling Settling time to 1% Tc = 0 to 60°C, G = 80, Vstep = 2 V 2.4 µsVswing Output swing linear range 0.3 5.7 V

Slew Rate G = 10 10 V/µsDC_offset Offset error RTI G = 10 with input shorted 4 mVDrift_offset Offset drift RTI 10 µV/CIbias Input bias current 100 µAVin_com Common input mode range –0.15 0.15 VVin_dif Differential input range –0.3 0.3 V

Vo_bias Output bias With zero input current, VREF up to6 V –0.5% 0.5×Vref 0.5% V

CMRR_OV Overall CMRR with gain resistormismatch CMRR at DC, gain = 10 70 85 dB

6.7 SPI Characteristics (Slave Mode Only)MIN NOM MAX UNIT

tSPI_READYSPI ready after EN_GATE transitionsto HIGH PVDD > 6 V 5 10 ms

tCLK Minimum SPI clock period 100 nstCLKH Clock high time See Figure 1 40 nstCLKL Clock low time See Figure 1 40 nstSU_SDI SDI input data setup time 20 nstHD_SDI SDI input data hold time 30 ns

tD_SDOSDO output data delay time, CLKhigh to SDO valid CL = 20 pF 20 ns

tHD_SDO SDO output data hold time See Figure 1 40 nstSU_SCS SCS setup time See Figure 1 50 nstHD_SCS SCS hold time 50 ns

tHI_SCSSCS minimum high time before SCSactive low 40 ns

tACCSCS access time, SCS low to SDOout of high impedance 10 ns

tDISSCS disable time, SCS high to SDOhigh impedance 10 ns


SCS

SDO

SDI

SCLK

_

Z ZMSB out (is valid) LSB

MSB in(must be valid)

LSB

tHI_SCS

tSU_SCS

tCLK

tHD_SCS

tCLKH tCLKL

tSU_SDI tHD_SDI

tACC tD_SDO tHD_SDOtDIS

9




(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X risingedge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.

6.8 Gate Timing and Protection Switching CharacteristicsPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMING, OUTPUT PINStpd,If-O Positive input falling to GH_x falling CL = 1 nF, 50% to 50% 45 nstpd,Ir-O Positive input rising to GL_x falling CL = 1 nF, 50% to 50% 45 nstd_min Minimum dead time after hand shaking (1) 50 nstdtp Dead time With RDTC set to different values 50 500 nstGDr Rise time, gate drive output CL = 1 nF, 10% to 90% 25 nstGDF Fall time, gate drive output CL = 1 nF, 90% to 10% 25 ns

tON_MIN Minimum on pulseNot including handshake communication.Hi-Z to on state, output of gate driver 50 ns

tpd_matchPropagation delay matching between highside and low side 5 ns

tdt_match Deadtime matching 5 nsTIMING, PROTECTION AND CONTROL

tpd,R_GATE-OPStart-up time, from EN_GATE active highto device ready for normal operation

PVDD is up before start up, all chargepump caps and regulator capacitors as inthe Recommended Operating Conditions

5 10 ms

tpd,R_GATE-Quick

If EN_GATE goes from high to low andback to high state within quick reset time,it will only reset all faults and gate driverwithout powering down charge pump,current amp, and related internal voltageregulators.

Maximum low pulse time 10 µs

tpd,E-L Delay, error event to all gates low 200 nstpd,E-FAULT Delay, error event to FAULT low 200 ns

Figure 1. SPI Slave Mode Timing Definition


10.0

10.2

10.4

10.6

10.8

11.0

11.2

11.4

11.6

11.8

12.0

-40 0 25 85 125

GV

DD

(V

)

Temperature (C) C001

8.0

8.2

8.4

8.6

8.8

9.0

9.2

9.4

9.6

9.8

10.0

-40 0 25 85 125

I PV

DD

1 (µ

A)


10.0

10.2

10.4

10.6

10.8

11.0

11.2

11.4

11.6

11.8

12.0

-40 0 25 85 125

GV

DD

(V

)


MSB

MSB

LSB

LSB

1 1615X432

SCLK

SDI

SDO

Receive

latch Points

SCS

10




Figure 2. SPI Slave Mode Timing Diagram

6.9 Typical Characteristics

PVDD = 8 V EN_GATE = LOW

Figure 3. IPVDD1 vs Temperature

PVDD = 8 V EN_GATE = HIGH

Figure 4. GVDD vs Temperature

PVDD = 60 V EN_GATE = HIGH

Figure 5. GVDD vs Temperature


11




7 Detailed Description

7.1 OverviewThe DRV8303 is a 6-V to 60-V, gate driver IC for three-phase motor drive applications. This device reducesexternal component count by integrating three half-bridge drivers and two current shunt amplifiers. The DRV8303provides overcurrent, over-temperature, and undervoltage protection. Fault conditions are indicated through thenFAULT and nOCTW pins in addition to the SPI registers.

Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the externalMOSFETs. Internal hand shaking is used to prevent through current.

VDS sensing of the external MOSFETs allows for the DRV8303 to detect overcurrent conditions and respondappropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.


INH_A

GND (PWR_PAD)

nFAULT

Current Sense Amplifier 1

Current Sense Amplifier 2

GH_A

SH_A

GL_A

RIS

EN

SE

RIS

EN

SE

SL_A

GH_B

SH_B

GL_B

SL_B

GH_C

SH_C

GL_C

SL_C

SN1

SP1

SN2

SP2

BST_B

BST_A

BST_C

PVDD

PVDD

PVDD

PGND

CP1

CP2

PVDD

GVDD

GVDD

GVDD

GVDD

GVDD

Trickle Charge

Trickle Charge

Trickle Charge

Trickle Charge

Trickle Charge

GVDD

GVDD

GVDD

HS VDSSense

LS VDSSense

PVDD

HS

LS

HS

LS

HS

LS

PVDD

HS VDSSense

LS VDSSense

PVDD

HS VDSSense

LS VDSSense

PVDD

INL_A

INH_B

INL_B

INH_C

INL_C

DTC

nOCTW

EN_GATE

nSCS

SDI

SDO

SCLK

VDD_SPI

SPI Communication, Registers, and Fault Handling

Gate Driver Control and

Timing Logic

AVDD LDO

DVDD LDO

AVDDDVDDDVDD

AVDD

GND

AGND

AGND

Offset½ REF

REF

REF

Offset½ REF

REF

REF

SO1

SO2

DC_CAL

GND PGNDAGND

DVDD

AVDD

AGND

DRV8303

Charge Pump

Regulator

GND GND

12




7.2 Functional Block Diagram


13




7.3 Feature DescriptionThe following sections describe the DRV8303 features.

7.3.1 Three-Phase Gate DriverThe half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycleoperation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for thelow-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drivevarious other loads.

The peak gate drive current and internal dead times are adjustable to accommodate a variety of externalMOSFETs and applications. The peak gate drive current is set through a register setting and the dead time isadjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground will provide the minimum deadtime (50 ns). There is an internal hand shake between the high side and low side MOSFETs during switchingtransitions to prevent current shoot through.

The three-phase gate driver can provide up to 30 mA of average gate drive current. This will support switchingfrequencies up to 200 kHz when the MOSFET Qg = 25 nC.

Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures thevoltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage iscompared against the programmed trip point to determine if an overcurrent event has occurred. The high-sidesense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins.Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provideaccurate VDS sensing.

The DRV8303 allows for both 6-PWM and 3-PWM control through a register setting.

Table 1. 6-PWM ModeINL_X INH_X GL_X GH_X

0 0 L L0 1 L H1 0 H L1 1 L L

Table 2. 3-PWM ModeINL_X INH_X GL_X GH_X

X 0 H LX 1 L H

(1) VCC is the logic supply to the MCU

Table 3. Gate Driver External ComponentsNAME PIN 1 PIN 2 RECOMMENDEDRnOCTW nOCTW VCC (1) ≥10 kΩRnFAULT nFAULT VCC (1) ≥10 kΩ

RDTC DTC GND (PowerPAD) 0 to 150 kΩ (50 ns to 500 ns)CGVDD GVDD GND (PowerPAD) 2.2-µF (20%) ceramic, ≥ 16 V

CCP CP1 CP2 0.022-µF (20%) ceramic, rated for PVDDCDVDD DVDD AGND 1-µF (20%) ceramic, ≥ 6.3 VCAVDD AVDD AGND 1-µF (20%) ceramic, ≥ 10 VCPVDD PVDD GND (PowerPAD) ≥4.7-µF (20%) ceramic, rated for PVDDCBST_X BST_X SH_X 0.1-µF (20%) ceramic, ≥ 16 V


SN

SP

SO

_

+

DC_CAL

DC_CAL

DC_CAL

S1

S2

S4

S3

S1

S2

S4

S3

5kW

5kW

400kW

200kW

100kW

50kW

400kW

200kW

100kW

50kW

100W

_

+

REF

Vref/2

AVDD

AVDD

50kW

50kW

( )- ´ -REFO X XV

V = G SN SP2

14




7.3.2 Current Shunt AmplifiersThe DRV8303 includes two high performance current shunt amplifiers to accurate low-side, inline currentmeasurement.

The current shunt amplifiers have 4 programmable GAIN settings through the SPI registers. These are 10, 20,40, and 80 V/V.

They provide output offset up to 3 V to support bidirectional current sensing. The offset is set to half the voltageon the reference pin (REF).

To minimize DC offset and drift over temperature a calibration method is provided through either the DC_CAL pinor SPI register. When DC calibration is enabled, the device will short the input of the current shunt amplifier anddisconnect the load. DC calibration can be done at any time, even during MOSFET switching, because the loadis disconnected. For the best results, perform the DC calibration during the switching OFF period, when no loadis present, to reduce the potential noise impact to the amplifier.

Use Equation 1 to calculate the output of the current shunt amplifier.

where• VREF is the reference voltage (REF pin)• G is the gain of the amplifier (10, 20, 40, or 80 V/V)• SNX and SPx are the inputs of channel x. SPx should connect to the ground side of the sense resistor for the

nest common mode rejection. (1)

Figure 6 shows the simplified block diagram for the current shunt amplifier.

Figure 6. Current Shunt Amplifier Simplified Block Diagram


15




7.3.3 Protection FeaturesThe DRV8303 provides a broad range of protection features and fault condition reporting. The DRV8303 hasundervoltage and over-temperature protection for the IC. It also has overcurrent and undervoltage protection forthe MOSFET power stage. In fault shut down conditions all gate driver outputs will be held low to ensure theexternal MOSFETs are in a high impedance state.

7.3.3.1 Power Stage ProtectionThe DRV8303 provides over-current and undervoltage protection for the MOSFET power stage. During fault shutdown conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.

7.3.3.2 Overcurrent Protection (OCP) and ReportingTo protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in theDRV8303. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage thresholdcan be determined to trigger the overcurrent protection features when exceeded. The voltage threshold isprogrammed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it isnot intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels forthe VDS trip point.

VDS = IDS × RDS(ON) (2)

The VDS sense circuit measures the voltage from the drain to the source of the external MOSFET while theMOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is betweenthe SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for theselines will help provide accurate VDS sensing .

There are four different overcurrent modes (OC_MODE) that can be set through the SPI registers. The OC statusbits operate in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch inthe DRV8303 registers until the fault is reset.1. Current Limit Mode: In current limit mode the device uses current limiting instead of device shutdown during

an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. ThenOCTW pin will be held low for a maximum 64-µs period (internal timer) or until the next PWM cycle. Ifanother overcurrent event is triggered from another MOSFET, during a previous overcurrent event, thereporting will continue for another 64-µs period (internal timer will restart) or until both PWM signals cycle.The associated status bit will be asserted for the MOSFET in which the overcurrent was detected. There aretwo current control settings in current limit mode. These are set by one bit in the SPI registers. The defaultmode is cycle by cycle (CBC).– Cycle-By-Cycle Mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on

will shut off until the next PWM cycle.– Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is

disabled for a 64-µs period (set by internal timer). If overcurrent is detected in another MOSFET, the timerwill be reset for another 64-µs period and both MOSFETs will be disabled for the duration. During thisperiod, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.

2. OC Latch Shut Down Mode: When an overcurrent event occurs, both the high-side and low-side MOSFETswill be disabled in the corresponding half-bridge. The nFAULT pin, nFAULT status bit, and OC status bit forthe MOSFET in which the overcurrent was detected will latch until the fault is reset through theGATE_RESET bit or a quick EN_GATE reset pulse.

3. Report Only Mode: No protective action will be taken in this mode when an overcurrent event occurs. Theovercurrent event will be reported through the nOCTW pin (64-µs pulse) and SPI status register. Theexternal MCU should take action based on its own control algorithm.

4. OC Disable Mode: The device will ignore and not report all overcurrent detections.

7.3.3.3 Undervoltage Protection (UVLO)To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, theDRV8303 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDDor GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs ina high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPIregisters will revert to their default settings.


16




A specific PVDD undervoltage transient brownout from 13 to 15 µs can cause the DRV8303 to becomeunresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD greaterthan the PVDD_UV level and then PVDD dropping below the PVDD_UV level for a specific period of 13 to 15 µs.Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage protection.Additional bulk capacitance can be added to PVDD to reduce undervoltage transients.

7.3.3.4 Overvoltage Protection (GVDD_OV)The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OVthreshold to prevent potential issues related to the GVDD pin or the charge pump (for example, short of externalGVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on theEN_GATE pin.

7.3.3.5 Overtemperature ProtectionA two-level over-temperature detection circuit is implemented:• Level 1: overtemperature warning (OTW)

OTW is reported through nOCTW pin (over-current-temperature warning) for default setting. OCTW pin canbe set to report OTW or OCW only through SPI command. See SPI Register section.

• Level 2: overtemperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)Fault will be reported to nFAULT pin. This is a latched shut down, so gate driver will not be recoveredautomatically even OT condition is not present anymore. An EN_GATE reset through pin or SPI(RESET_GATE) is required to recover gate driver to normal operation after temperature goes below a presetvalue, tOTSD_CLR.

SPI operation is still available and register settings will be remaining in the device during OTSD operation as longas PVDD is still within defined operation range.

7.3.3.6 Fault and Protection HandlingThe nFAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature,overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT will go high when gate driver isready for PWM signal (internal EN_GATE goes high) during start up.

The nOCTW pin indicates overcurrent event and over temperature event that not necessary related to shutdown.

Table 4 summarizes all protection features and their reporting structure:

Table 4. Fault and Warning Reporting and Handling

EVENT ACTION LATCH REPORTING ONnFAULT PINREPORTING ON

nOCTW PINREPORTING IN SPISTATUS REGISTER

PVDDundervoltage

External FETs HiZ;Weak pulldown of all gate

driver outputN Y N Y

DVDDundervoltage


driver output; When recovering,reset all status registers

N Y N N

GVDDundervoltage


driver outputN Y N Y

GVDDovervoltage

External FETs HiZ;Weak pulldown of all gate driver

outputShut down the charge pump

Won’t recover and reset throughSPI reset command or

quick EN_GATE toggling

Y Y N Y

OTW None N N Y (in defaultsetting) Y


17




Table 4. Fault and Warning Reporting and Handling (continued)

EVENT ACTION LATCH REPORTING ONnFAULT PINREPORTING ON

nOCTW PINREPORTING IN SPISTATUS REGISTER

OTSD_GATE

Gate driver latched shut down.Weak pulldown of all gate driver

outputto force external FETs HiZ

Shut down the charge pump

Y Y Y Y

External FEToverload – current

limit mode

External FETs current Limiting(only OC detected FET) N N Y

Y, indicates which phasehas OC

External FEToverload – Latch

mode

Weak pulldown of gate driveroutput and PWM logic “0” of

LS and HS in the same phase.External FETs HiZ

Y Y Y Y

External FEToverload –

reporting onlymode

Reporting only N N Y Y, indicates which phasehas OC

7.3.4 Start-Up and Shutdown Sequence ControlDuring power up, all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifierscan be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8303 isready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode aslong as PVDD is within functional region.

There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same powerlevel as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply shouldbe powered up first before any signal appears at SDO pin and powered down after completing allcommunications at SDO pin.

7.4 Device Functional Modes

7.4.1 EN_GATEEN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks intoa low power consumption mode to save energy. SPI communication is not supported during this state. Devicewill put the MOSFET output stage to high impedance mode as long as PVDD is still present.

When EN_GATE pin goes to high, it will go through a power-up sequence, and enable gate driver, currentamplifiers, charge pump, internal regulator, and so forth, and reset all latched faults related to gate driver block. Itwill also reset status registers in SPI table. All latched faults can be reset when EN_GATE is toggled after anerror event unless the fault is still present.

When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can putexternal FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of theblocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10 µs).This will prevent device to shut down other function blocks such as charge pump and internal regulators andbring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset mode.

The other way to reset all the faults is to use SPI command (RESET_GATE), which will only reset gate driverblock and all the SPI status registers without shutting down other function blocks.

One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset does notwork with GVDD_OV fault. A complete EN_GATE with low level holding longer than 10µS is required to resetGVDD_OV fault. TI highly recommends inspecting the system and board when GVDD_OV occurs.

7.4.2 DTCDead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to controlthe dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground will provide minimumdead time (50 ns). Resistor range is 0 kΩ to 150 kΩ. Dead time is linearly set over this resistor range.


18




Device Functional Modes (continued)Current shoot through prevention protection will be enabled in the device all time independent of dead timesetting and input mode setting.

7.4.3 VDD_SPIVDD_SPI is the power supply to power SDO pin. It must be connected to the same power supply (3.3V or 5V)that MCU uses for its SPI operation.

During power up or down transient, VDD_SPI pin could be zero voltage shortly. During this period, no SDOsignal should be present at SDO pin from any other devices in the system because it causes a parasitic diode inthe DRV8303 conducting from SDO to VDD_SPI pin as a short. This should be considered and prevented fromsystem power sequence design.

7.4.4 DC_CALWhen DC_CAL is enabled, device will short inputs of shunt amplifier and disconnect from the load, so externalmicrocontroller can do a DC offset calibration. DC offset calibration can be also done with SPI command. If usingSPI exclusively for DC calibration, the DC_CAL pin can connected to GND.


19




7.5 Programming

7.5.1 SPI Communication

7.5.1.1 SPIThe DRV8303 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and theremaining bits will shift out as 0.

A valid frame must meet following conditions:• Clock must be low when nSCS goes low.• Should have 16 full clock cycles.• Clock must be low when nSCS goes high.

When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a highimpedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response wordloads into the shift register based on the previous SPI input word.

The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock theresponse word is serially shifted out on the SDO pin with the MSB shifted out first.

While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI inputword is decoded to determine the register address and access type (read or write). The MSB will be shifted infirst. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit wordsto be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. Ifit is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1.After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferredinto a latch where the input word is decoded.

For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in thenext cycle. (N+1)

For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in thenext cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple writecommands.

7.5.1.2 SPI FormatThe SDI input data word is 16 bits long and consists of:• 1 read/write bit W [15]• 4 address bits A [14:11]• 11 data bits D [10:0]

The SDO output data word is 16 bits long and consists of:• 1 fault frame bit F [15]• 4 address bits A [14:11]• 11 data bits D [10:0]

The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).

Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.

Table 5. SPI Input Data Control Word FormatR/W ADDRESS DATA

Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Command W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0


20




Table 6. SPI Output Data Response Word FormatR/W DATA

Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0Command F0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

7.6 Register Maps

7.6.1 Read / Write BitThe MSB bit of the SDI input word (W0) is a read/write bit. When W0 = 0, the input word is a write command.When W0 = 1, input word is a read command.

7.6.2 Address Bits

Table 7. Register AddressREGISTER

TYPE ADDRESS [A3..A0] REGISTER NAME DESCRIPTION READ AND WRITE ACCESS

StatusRegister

0 0 0 0 Status Register 1 Status register for device faults R0 0 0 1 Status Register 2 Status register for device faults and ID R

ControlRegister

0 0 1 0 Control Register 1 R/W0 0 1 1 Control Register 2 R/W

7.6.3 SPI Data Bits

7.6.3.1 Status Registers

Table 8. Status Register 1 (Address: 0x00) (all default values are zero)

ADDRESS REGISTERNAME D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0x00 StatusRegister 1 FAULT GVDD_UV PVDD_UV OTSD OTW FETHA_OC FETLA_OC FETHB_OC FETLB_OC FETHC_OC FETLC_OC

Table 9. Status Register 2 (Address: 0x01) (all default values are zero)ADDRESS REGISTER

NAMED10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0x01 StatusRegister 2 GVDD_OVDevice ID

[3]Device ID

[2]Device ID

[1]Device ID

[0]

(1) Default value

7.6.3.2 Control Registers

Table 10. Control Register 1 for Gate Driver Control (Address: 0x02) (1)

ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0x02

GATE_CURRENT

Gate drive peak current 1.7 A 0(1) 0(1)

Gate drive peak current 0.7 A 0 1

Gate drive peak current 0.25 A 1 0

Reserved 1 1

GATE_RESETNormal mode 0(1)

Reset gate driver latched faults (reverts to 0) 1

PWM_MODE6 PWM inputs (see Table 1) 0(1)

3 PWM inputs (see Table 2) 1

OCP_MODE

Current limit 0(1) 0(1)

OC latch shut down 0 1

Report only 1 0

OC disabled 1 1

OC_ADJ_SET See OC_ADJ_SET table X X X X X


21




(1) Default value

Table 11. Control Register 2 for Current Shunt Amplifiers and Misc Control (Address: 0x03) (1)

ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0x03

OCTW_MODE

Report both OT and OC at nOCTW pin 0(1) 0(1)

Report OT only 0 1

Report OC only 1 0

Report OC only (reserved) 1 1

GAIN

Gain of shunt amplifier: 10 V/V 0(1) 0(1)

Gain of shunt amplifier: 20 V/V 0 1



DC_CAL_CH1Shunt amplifier 1 connects to load through input pins 0(1)

Shunt amplifier 1 shorts input pins and disconnects from loadfor external calibration 1

DC_CAL_CH2Shunt amplifier 2 connects to load through input pins 0(1)

Shunt amplifier 2 shorts input pins and disconnects from loadfor external calibration 1

OC_TOFFCycle by cycle 0(1)

Off-time control 1

Reserved

(1) Do not use settings 28, 29, 30, 31 for VDS sensing if the IC is expected to operate in the 6-V to 8-V range.

7.6.3.3 Overcurrent Adjustment

Table 12. OC_ADJ_SET TableControl Bit (D6–D10) (0xH) 0 1 2 3 4 5 6 7

Vds (V) 0.060 0.068 0.076 0.086 0.097 0.109 0.123 0.138Control Bit (D6–D10) (0xH) 8 9 10 11 12 13 14 15

Vds (V) 0.155 0.175 0.197 0.222 0.250 0.282 0.317 0.358Control Bit (D6–D10) (0xH) 16 17 18 19 20 21 22 23

Vds (V) 0.403 0.454 0.511 0.576 0.648 0.730 0.822 0.926Code Number (0xH) 24 25 26 27 28 29 30 31

Vds (V) 1.043 1.175 1.324 1.491 1.679 (1) 1.892 (1) 2.131 (1) 2.400 (1)


22




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe DRV8303 is a gate driver designed to drive a 3-phase BLDC motor in combination with external powerMOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shuntamplifier, and overcurrent protection.

8.1.1 Gate Driver Power-Up Sequencing ErrataThe DRV8301 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pinwhen EN_GATE is brought logic high (device enabled) after PVDD power is applied (PVDD1 > PVDD_UV). Thissequence should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when theDRV8301 is enabled through EN_GATE.


1nOCTW

2nFAULT

3DTC

4nSCS

5SDI

6SDO

7SCLK

8DC_CAL

9GVDD

10CP1

11CP2

12EN_GATE

13INH_A

14INL_A

15INH_B

16INL_B

17INH_C

18INL_C

19DVDD

20REF

21SO1

22SO2

23AVDD

24AGND

48GND

47GND

46GND

45VDD_SPI

44BST_A

43GH_A

42SH_A

41GL_A

40SL_A

39BST_B

38GH_B

37SH_B

36GL_B

35SL_B

34BST_C

33GH_C

32SH_C

31GL_C

30SL_C

29SN1

28SP1

27SN2

26SP2

25PVDD

49P

PA

D

10

10

PVDD

GH_C

SH_C

GL_C

SL_C

GH_B

SH_B

GL_B

SL_B

GH_A

SH_A

GL_A

SL_A10

m

1000

pF

SN1

SP1

SN2

SP2

SN1

SP1

GH_A

SH_A

GL_A

SL_A

2.2

µF

34.8

k

4.99

k

0.1

µF

AS

EN

SE

VCC

10

10

PVDD

10 m

1000

pFSN2

SP2

GH_B

SH_B

GL_B

SL_B

2.2

µF

34.8

k

4.99

k

0.1

µF

BS

EN

SE

VCC

10

10

PVDD

GH_B

SH_B

GL_B

SL_B

2.2

µF

34.8

k

4.99

k

0.1

µF

CS

EN

SE

VCC

0.1 µF

0.1 µF

0.1 µF

VCC

GND PGNDAGND

Diff. Pair Diff. Pair

PVDD

220

µF

220

µF

0.1

µF

0.01

µF

3.3

34

.8 k

4.99

k

0.1

µF

PVDDSENSE

VCC

PVDD

0.1

µF

4.7

µF

1 µF

1 µF

GND PGNDAGND

56

56

2200

pF

2200

pF

0.022 µF2.

2 µ

F

1

PVDDSENSE

ASENSE

BSENSE

CSENSE

MCU

DRV8303

ADC

PWM

GPIO

SPI

GPIO

10 k

10 k

VCC

POWER

VCC

+ +

23




8.2 Typical Application

Figure 7. Typical Application Schematic


24




Typical Application (continued)8.2.1 Design RequirementsTable 13 lists the design parameters for this example.

Table 13. Design ParametersDESIGN PARAMETER REFERENCE VALUE

Supply voltage PVDD 24 VMotor winding resistance MR 0.5 ΩMotor winding inductance ML 0.28 mHMotor poles MP 16 polesMotor rated RPM MRPM 4000 RPMTarget full-scale current IMAX 14 ASense resistor RSENSE 0.01 ΩMOSFET Qg Qg 29 nCMOSFET RDS(on) RDS(on) 4.7 mΩVDS trip level OC_ADJ_SET 0.123 VSwitching frequency ƒSW 45 kHzSeries gate resistance RGATE 10 ΩAmplifier reference VREF 3.3 VAmplifier gain Gain 10 V/V

8.2.2 Detailed Design Procedure

8.2.2.1 Gate Drive Average Current LoadThe gate drive supply (GVDD) of the DRV8303 can deliver up to 30 mA (RMS) of current to the external powerMOSFETs. Use Equation 3 to determine the approximate RMS load on the gate drive supply:

Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency (3)

Example:7.83 mA = 29 nC × 6 × 45 kHz (4)

This is a rough approximation only.

8.2.2.2 Overcurrent Protection SetupThe DRV8303 provides overcurrent protection for the external power MOSFETs through the use of VDS monitorsfor both the high side and low side MOSFETs. These are intended for protecting the MOSFET in overcurrentconditions and not for precise current regulation.

The overcurrent protection works by monitoring the VDS voltage of the external MOSFET and comparing itagainst the OC_ADJ_SET register value. If the VDS exceeds the OC_ADJ_SET value the DRV8303 takes actionaccording to the OC_MODE register.

Overcurrent Trip = OC_ADJ_SET / MOSFET RDS(on) (5)

Example:26.17 A = 0.123 V / 4.7 mΩ (6)

MOSFET RDS(on) changes with temperature and this will affect the overcurrent trip level.

8.2.2.3 Sense Amplifier SetupThe DRV8303 provides two bidirectional low-side current shunt amplifiers. These can be used to sense a sum ofthe three half-bridges, two of the half-bridges individually, or in conjunction with an additional shunt amplifier tosense all three half-bridges individually.1. Determine the peak current that the motor will demand (IMAX). This will be dependent on the motor

parameters and your specific application. I(MAX) in this example is 14 A.2. Determine the available voltage range for the current shunt amplifier. This will be ± half of the amplifier


25




reference voltage (VREF). In this case the available range is ±1.65 V.3. Determine the sense resistor value and amplifier gain settings. There are common tradeoffs for both the

sense resistor value and amplifier gain. The larger the sense resistor value, the better the resolution of thehalf-bridge current. This comes at the cost of additional power dissipated from the sense resistor. A largergain value will allow you to decrease the sense resistor, but at the cost of increased noise in the outputsignal. This example uses a 0.01-Ω sense resistor and the minimum gain setting of the DRV8303 (10 V/V).These values allow the current shunt amplifiers to measure ±16.5 A (some additional margin on the 14-Arequirement).

8.2.3 Application Curves

Figure 8. Motor Spinning 2000 RPM Figure 9. Motor Spinning 4000 RPM

Figure 10. Gate Drive 20% Duty Cycle Figure 11. Gate Drive 80% Duty Cycle


Local

Bulk Capacitor

Parasitic Wire

Inductance

+–

Motor

Driver

Power Supply Motor Drive System

VM

GND

+

IC Bypass

Capacitor

26




9 Power Supply Recommendations

9.1 Bulk CapacitanceHaving appropriate local bulk capacitance is an important factor in motor drive system design. It is generallybeneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:• The highest current required by the motor system• The capacitance of the power supply and its ability to source or sink current• The amount of parasitic inductance between the power supply and motor system• The acceptable voltage ripple• The type of motor used (brushed DC, brushless DC, stepper)• The motor braking method

The inductance between the power supply and motor drive system will limit the rate current can change from thepower supply. If the local bulk capacitance is too small, the system will respond to excessive current demands ordumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltageremains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine theappropriate sized bulk capacitor.

Figure 12. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for caseswhen the motor transfers energy to the supply.


27




10 Layout

10.1 Layout GuidelinesUse these layout recommendations when designing a PCB for the DRV8303.• The DRV8303 makes an electrical connection to GND through the PowerPAD. Always check to ensure that

the PowerPAD has been properly soldered (see PowerPAD™ Thermally Enhanced Package).• PVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to

device GND (PowerPAD).• GVDD bypass capacitor should be placed close its corresponding pin with a low impedance path to device

GND (PowerPAD).• AVDD and DVDD bypass capacitors should be placed close to their corresponding pins with a low impedance

path to the AGND pin. It is preferable to make this connection on the same layer.• AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.• Add stitching vias to reduce the impedance of the GND path from the top to bottom side.• Try to clear the space around and underneath the DRV8303 to allow for better heat spreading from the

PowerPAD.

http://www.ti.com/product/drv8303?qgpn=drv8303http://www.ti.comhttp://www.ti.com/product/drv8303?qgpn=drv8303http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS846C&partnum=DRV8303http://www.ti.com/lit/pdf/SLMA002

28




10.2 Layout Example

Figure 13. Layout Recommendation


29




11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related DocumentationFor related documentation see the following:• DRV8303EVM User Guide• PowerPAD™ Thermally Enhanced Package• Sensored 3-Phase BLDC Motor Control Using MSP430

11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

http://www.ti.com/product/drv8303?qgpn=drv8303http://www.ti.comhttp://www.ti.com/product/drv8303?qgpn=drv8303http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLOS846C&partnum=DRV8303http://www.ti.com/lit/pdf/SLVU983http://www.ti.com/lit/pdf/SLMA002http://www.ti.com/lit/pdf/SLAA503http://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://e2e.ti.comhttp://support.ti.com/http://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

DRV8303DCA ACTIVE HTSSOP DCA 48 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8303

DRV8303DCAR ACTIVE HTSSOP DCA 48 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8303

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DRV8303DCAR HTSSOP DCA 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV8303DCAR HTSSOP DCA 48 2000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

Pack Materials-Page 2

http://www.ti.com/lit/slma002

http://www.ti.com/lit/slma002http://www.ti.com/lit/slma004

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

http://www.ti.com/legal/termsofsale.htmlhttp://www.ti.com

1 Features2 Applications3 DescriptionTable of Contents4 Revision History5 Pin Configuration and Functions6 Specifications6.1 Absolute Maximum Ratings6.2 ESD Ratings6.3 Recommended Operating Conditions6.4 Thermal Information6.5 Electrical Characteristics6.6 Current Shunt Amplifier Characteristics6.7 SPI Characteristics (Slave Mode Only)6.8 Gate Timing and Protection Switching Characteristics6.9 Typical Characteristics

7 Detailed Description7.1 Overview7.2 Functional Block Diagram7.3 Feature Description7.3.1 Three-Phase Gate Driver7.3.2 Current Shunt Amplifiers7.3.3 Protection Features7.3.3.1 Power Stage Protection7.3.3.2 Overcurrent Protection (OCP) and Reporting7.3.3.3 Undervoltage Protection (UVLO)7.3.3.4 Overvoltage Protection (GVDD_OV)7.3.3.5 Overtemperature Protection7.3.3.6 Fault and Protection Handling

7.3.4 Start-Up and Shutdown Sequence Control

7.4 Device Functional Modes7.4.1 EN_GATE7.4.2 DTC7.4.3 VDD_SPI7.4.4 DC_CAL

7.5 Programming7.5.1 SPI Communication7.5.1.1 SPI7.5.1.2 SPI Format

7.6 Register Maps7.6.1 Read / Write Bit7.6.2 Address Bits7.6.3 SPI Data Bits7.6.3.1 Status Registers7.6.3.2 Control Registers7.6.3.3 Overcurrent Adjustment

8 Application and Implementation8.1 Application Information8.1.1 Gate Driver Power-Up Sequencing Errata

8.2 Typical Application8.2.1 Design Requirements8.2.2 Detailed Design Procedure8.2.2.1 Gate Drive Average Current Load8.2.2.2 Overcurrent Protection Setup8.2.2.3 Sense Amplifier Setup

8.2.3 Application Curves

9 Power Supply Recommendations9.1 Bulk Capacitance

10 Layout10.1 Layout Guidelines10.2 Layout Example

11 Device and Documentation Support11.1 Documentation Support11.1.1 Related Documentation

11.2 Receiving Notification of Documentation Updates11.3 Community Resources11.4 Trademarks11.5 Electrostatic Discharge Caution11.6 Glossary

12 Mechanical, Packaging, and Orderable Information

DRV8303 Three-Phase Gate Driver With Dual-Current Shunt ... · PWM DRV8303 6 to 60 V MCU N-Channel...

Documents

Transcript of DRV8303 Three-Phase Gate Driver With Dual-Current Shunt ... · PWM DRV8303 6 to 60 V MCU N-Channel...