1970, No. 7/8/9 277

Digital integrated circuits with MOS transistors

L. M. van der Steen

The simple structure and low dissipation of MOStransistors allow them to be formed in large numbersper unit surface area on a crystal chip. Moreover.since a MOST has a very high input impedance andallows current to flow in both direcrions, some MOScircuits require fewer components than the correspond-ing bipolar circuits. These features make the MOStransistor eminently suitable for use in integrated cir-cuits. In this article we shall describe some examplesof digital integrated circuits of this type, made entirelyfrom P-channel enhancement MOSTs.

Little need be said here about the MOS transistor;the N-channel type has been dealt with in detail else-where in this issue Ill. and the P-channel type (seefig. I) differs from this only in polarity. The IrI-V",family of characteristics and the graph of Irl sa 1- V gs

ha ve the same shape as the graphs in fig. 2 of Ill.

except that currents and voltages are now negative.For application in digital circuits the P-channel MOSTmay be regarded as a switch that passes current when Q

Vg, is sufficiently negative Cl Vgs\ > I VIlli. the thresholdvoltage Vl11 being typically -3 to -4 volts) and doesnot pass current when Vgs is between 0 volts and V111.

The manufacture of integrated MOS circuits

Fig. I. P-channel MOS transistor on a substrate of N-type silicon.The source S and the drain Dare P'-type regions diffused in thesilicon. The gate G is of aluminium (shown black) and is isolatedfrom the substrate by a layer of silicon dioxide (white). Substrateand source are earthed: a negative voltage is applied to the drainD. If a sufficiently negative voltage is applied to the gate (Jowerthan the threshold voltage VII], which is also negative), a thininverted P-type layer is formed beneath the gate, enabling cur-rent tu flow between Sand D. Below the source, drain and thechannel there is a depletion layer, which acts as an insulator sinceit contains hardly any free charge carriers.

The voltages applied to a MOST are always arrangedso that the drain and inversion layer are reverse-biasedwith respect to the substrate and therefore isolatedfrom it by a depletion layer (see fig. I). The source may £.be connected to the substrate : if it is not, the voltageon the source is always such that this electrode also issurrounded by a depletion layer. The natural isolationprovided by this depletion layer presents considerableadvantages in the manufacture of integrated circuits g_made up from MOS devices, since there is now no needto make an isolated island of the appropriate materialby means of an epitaxially grown silicon layer and anisolation diffusion for each transistor, as there is withintegrated circuits using bipolar transistors l21. Thenumber of photoetching processes needed for manu-facture is thus reduced from six for bipolar-transistorcircuits to four for MOS circuits.

The situations after the various photoetching pro-cesses [31 are shown schematically in fig. 2. The manu-

Drs. L. M. van der Steen is with the Philips Electronic Componentsand Materials Division (Elcoma ), at Nijmegen.

b

Fig. 2. Some stages in the manufacture of a MOS transistor.Windows for the source and drain are etched in an oxide layer(0) on the substrate (a). After diffusion of these electrodes, awindow for the oxide layer below the gate is etched in the oxidefilm formed during the diffusion process (b). After the oxidelayer has been formed, the windows are etched for the contactswith the source and drain (c). Finally an aluminium layer is de-posited, from which the electrodes are formed by etching awaysurplus aluminium (d).

------------------------m J. A. van Nielen, Operation and d.c, behaviour of MOS tran-

sistors ; this issue, page 209.l2] See A. Schmitz, Solid circuits, Philips tech. Rev. 27, 192-199,

1966.l3] For more details see the article by J. A. Appels, H. Kalter and

E. Kooi in this issue, page 225.

278 PHILlPS TECHNICAL REVIEW VOLUME 31

facture of a P-channel :t\10S circuit starts with a single-crystal wafer of homogeneously doped N-type silicon(of diameter say 50 mm and thickness 250 [Lm), onwhich a silicon-dioxide film is formed in a hot oxygen-rich atmosphere. A photoetching process is used tomake windows in this oxide film at the places wherethe source and drain are to be located (fig. 2a). Thewafer is then heated in a boron-containing atmosphere,so that the boron diffuses through the windows intothe N-type silicon and causes regions of P-type siliconto form. During the diffusion process a new layer ofsilicon dioxide forms on the wafer, and windows aremade in this layer in a second etching process (fig. 2b).By heating in an oxygen-rich atmosphere a thin layerof silicon dioxide (0.1 [Lm) is then formed in thesewindows to give isolation between the substrate and thegate electrodes. In a third etching process windows aremade in this oxide layer above the source and drain(fig. 2e). A layer of aluminium is then deposited, fromwhich the various electrodes and connections betweenthe components of the circuit are formed by removingthe surplus aluminium in a fourth and last etchingprocess.

Since in this technology there is no isolation diffu-sion, which takes up a good deal of space, a very large

. number of components can be formed on a siliconchip. And since the dissipation of MOS transistors isvery low, such a high packing density is a practicalproposition for many circuits. In a dynamic shiftregister, for example, which is discussed later on in thisarticle, the local packing densities are as high as 6 X 101components per cm", and the average packing densityfor the complete monolithic circuit is 2 X 104 cm-"!.. Amonocrystalline silicon chip measuring a few rnm-can now accommodate complete MOS circuits of 300to 1500 cornponents: in the near future monolithic

rcircuits with several thous~nd components will bepossible. At the present, the average packing densitythat can be achieved in integrated circuit~ made withbipolar transistors is generally much smaller: about afew thousand per cm-.

MOS logic circuits

Simple logic circuits such as NOR gates or NANDgates are generally used as the "building blocks" fordigital circuits, since all digital circuits. from simplebistable circuits to storage elements, shift registers. etc .•can be made up from such basic. elements [41. A gatecircuit is very easily made withMOS transistors;jig. 3ashows such a circuit, which lias four MOS transistorsTr; to Tr4. Briefly, the circuit operates as follows. Thedrain and gate ofTr4 are both connected tothe negativesupply voltage, so that Tr4 always operates in the satu-ration region. However, current can only flow through

A B C Q0 0 0 10 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 I 1 0

a b

Fig. 3. a) The NOR gate, made as an integrated MOS circuit.The supply voltage Veltl is negative. The voltages at the inputs A,Band C can be either zero or negative. Thè voltage at the out-put Q is at the zero level when one or more of the inputs arenegative, since there is then current in the circuit. When negativelogic is used (the negative voltage is then related to the state Iand the zero level to state 0), the relation between the output leveland the input levels is given by Q = A + B + C, which is aNOR function. hl The truth table of the circuit with negativelogic.

Tr4 provided one or more of the transistors Tri to Tr3are passing current, i.e. provided the voltage at one ormore of the inputs A, Band C is sufficiently negative.The circuit is designed in such a way that in this situa-tion the voltage at the output Q is at the "zero level".i.e. between 0 volts and Vtli' If the voltage at each ofthe three inputs is at the zero level, no current flows andthe output voltage is negative. The transistors Tri. Tr-iand Tr3 in this circuit thus behave as switches. and soare called switching transistors; whereas Tr4 acts as aresistor and is therefore called a load transistor.

The voltage levels can be related in two ways to thestates 0 and I used in the mathematical treatment oflogical operations by Boolean algebra. In positive logicstate I denotes the high level and state 0 the low. andvice versa in negative logic. It is the practice to usenegative logic for logic circuits built up from P-channelMOS transistors; A = I here therefore means thatthe voltage at point A is negative. and A = 0 meansthat this voltage is at the zero level. In the circuit givenin fig. 3a we then have: Q = I if A = O. B = 0 andC = 0; Q = 0 if one or more of the inputs A. BandC are I. Thus. Q is not I if A or B or C is I; thisNOT-OR relation is represented by the NOR functionQ = A + B + C. so that the circuit of fig. 3a, usingnegative logic. is a NOR gate. Fig. 3b gives the truthtable for this case. In the transition from negative topositive logic AND and OR gates change their name,a NOR gate .then becoming a NAND gate. This canbe seen from the table in fig. 3b by interchanging onesand zeros; Q is ,then zero (i.e. not I) only if A and B

(41 See for example page 48 in: E. J. van Barneveld, Digital cir-cuit blocks, Philips tech. Rev. 28, 44-56, 1967, and page 20in: C. Slofstra, The use of digital circuit blocks in industrialequipment, Philips tech. Rev. 29, 19-33, 1968.

1970, No. 7/8/9 DIGITAL INTEGRATED'CIRCUITS WITH MOSTS 279

and C are I, so that Q is then indeed equal to A.B.C.The switching transistors, which are in parallel in

fig. 3a, can also be arranged in series; the result is thena gate circuit which, with negative logic, acts as aNAND gate. If the output voltage in a current-con-ducting circuit is to remain within the zero level, thetotal resistance of the switching transistors must notexceed a particular value. This requirement presents nodifficulties if the switching transistors are in parallel;if they are in series, however, an increasing number ofinputs requires the use of larger and larger switchingtransistors, and the circuit then takes up a lot of spaceon the crystal chip. The circuit with parallel transistorsis therefore preferred.

Inverter circuit

To describe the behaviour of the gate circuit duringthe transition between the levels, we can take thesimplest situation, for which B = 0 and C = O. A canbe 0 or I, and Q is then I or 0 as the case may be ;TrI and Tr4 then constitute an inverter circuit. We shallnow analyse this circuit, referring to jig. 4, and fromthis analysis we shall derive the requirements that haveto be met in the design of the transistors.

Provided that there is no saturation the current in aMOS transistor is related to the applied voltage Velsand the gate voltage Vgs by:

Id =f1(Vgs- Vth-tVds)VdS .... (I)

Here the threshold voltage Vth is the voltage betweengate and source at which inversion starts, i.e. at whichcurrent begins to flow. If Wdsl ~ IVgs- Vthl, satura-tion occurs and the current is given by:

In these equations f1 = f1, Cox 11"//, where f1, is themobility of the holes in the channel, Cox the oxidecapacitance per unit surface area (i.e. of the capacitorformed by gate, oxide and substrate), 11" is the widthand / the length of the channel. (See equations (6) and(9) of the article mentioned in [11.)

For transistor TrI in fig. 4 we have VgS = Vi andVds = Vo, so that:

Fig. 4. MOS inverter circuit de-rived from the NOR gate offig. 3a with B = C = O. Vi andVo are the input and outputvoltages. When VI is at the nega-tive level (VI = I), Vo is at thezero level (Vo = 0), and viceversa.

Ia: = f11(VI- Vthl- tVo)Vo (3)

if IVi - Vthll > IVol (no saturation), and

(4)Ia: sat = tPI(Vi - Vthl)2

if I Vi - Vthil < IVol (saturation).

Since the gate of Tr4 is connected to the drain, sothat IVdsl > IVgs - Vlh41 at all times, this transistorwill always operate in the saturation region. In factTr4 acts here only as a resistor; a transistor is used atthis position because a diffused resistor of high enough-value would take up too much space on the crystalwafer. For Tr4 we have VgS = Vds =:= Vdd - Vo (seefig. 4), so that:

(5)

Fig. 5 shows the Id- Vo characteristics of Tri; thesehave Vi as parameter and at Vi - Vlhi = Vo they allmeet the horizontal part of the curve where the currentis saturated. The figure also shows the curved loadline which is obtained because Tr4 is used as a loadresistance and is derived from equation (5). Since atall times

(6)

the points where the load line intersects the Id- Vo

characteristics of Tri are the operating points of the

(2)

-('lctd-l1h4)----Va

Fig. 5. 1'1-V" characteristics of the transistor Tri from the invertercircuit of fig. 4, showing the curved load line which results whenTr4 is used as a load resistor. In the characteristics of Tri theparameter is VI: when VI is more negative the current is higher.The dashed line VI - Vtltl = V" connects the points where thecurrent through Tri goes into saturation.

circuit at different values of Vi; these operating pointsset out in a Vo-Vi diagram form the Vo-Vi characteris-tic of the inverter circuit (jig. 6).

In the characteristic given in fig. 6 three regionscan be distinguished. In region I, Vi is at th7 zerolevel, i.e. 0 < IVd < IVlhll. TrI is now not conduct-ing, so that l at. = Id4 = 0, and from equation (5) itfollows that Vo = Vdd - cVlh4. This is therefore the"I level" of the output voltage. In fig. 6 this situation

280 PHILlPS TECHNICAL REVIEW VOLUME 31

corresponds to the horizontal part of the characteristic;in fig. 5 the operating point lies on the Vo-axis.

In region 11 Vi falls below the threshold voltage, sothat TrI starts to conduct. At the same time, however,IVI - VtllII < lVol, and therefore in fig. 5 the opera-ting point lies to the right of the line Vi - VillI =..vo,so that TrI operates in saturation. In fig. 6 a lineartransition now arises between the two voltage levels;the region is bounded here by the lines Vi = VillIand VI ~ VillI = Voo

In region Hr Vi is even more negative, and hereIVj- VtllII> IVol. The current through the circuithas further increased, and TrI is now no longer insaturation. In this situation Vi = I and hence Vo = O.To ensure that this is so, the voltage divider formed byTrI and Tr4 must be so arranged that V0 is between 0and Vtlli when the circuit is passing current (as a ruleVo is put at approximately 0.1 Villi). Region III liesto the-right of the line .vo = VI - VillI in fig. 6 andto the left of it in fig. 5.

We shall now take a closer look at the situation inthe transition region I I, in which both transistors oper-ate in saturation. From equations (4). (5) and (6) itthen follows that:

tfh(Vi - Vtll1)2 = -}fJ.J(Vdel- Vo - Vlh.J)2 (7)

and this gives:

Vo = -(fil//34)1/2(Vi-Vlhl)+ (Vdcl-Vlh.J). (8)

In this region the Vo-Vi characteristic is therefore astraight line with a slope of ex = -(thltJ.j)1/2. Fig. 7shows a set of these characteristics for various valuesof ex and for the same values of Veld. Vlh1 and Vlh.J.In designing a circuit the choice of ex is partly deter-mined by the requirement noted above that in region IIIthe output voltage should be at the zero level. Thismeans that the slope must exceed a particular limitingvalue; in practice it is usual to take tJl/tJ4 ~ 20.

Since the transistors are parts of a monolithic circuit.and are thus formed during the same operation. theyhave the same thickness of oxide layer below the gatesand the same mobility for the holes in the channels. Infh and fJ4 the factors IJ- and Cox are therefore identical,so that

fJI wi/ftfJ4 = w4114 .

The ratio /31/fJ4 is therefore determined entirely by thelVII aspect ratios of the transistors. If, for example, theswitching transistor' has the dimensions IV = I = ra[.I.m(so that IVIll: = 1), and if fJl!/34 should have avalue of 20 to give the right slope, then 11'4114 for theload transistor should have a value of 1120. Thus wecould have w = 10 [.I.marid I' 200 [.I.m.

l

--~Fig.6. Vo- V! characteristic ofthe inverter circuit in fig.4, derivedfrom fig. 5 by plotting the points where the load line intersectsthe Ie- Vo characteristics of TrI. In region I, Vi = 0 and Vo = I;in region Ifl, Vi = I and Vo = O. Region H is the transitionbetween these situations. The curves Vi = VIlIl and Vi - VIII!

= Vu form the boundaries between the regions. In I and lithecurve is virtually a straight line.

1

,-/

//

//

/

/V;-V,hl=~//

- Vlf11

--\{

Fig. 7. Some VO-V! characteristics for different values of {3l/{34.In the transition region" the slope of the curves is proportionalto ({3l/fJ4)l/2. The output voltage in region III is within the zerolevel only for the two steepest curves in this region.

The characteristics of figs. 6 and 7 hold for the NORcircuit of fig. 3a when only one switching transistor isconducting. If several switching transistors are acti-vated simultaneously, Vo adjusts itself to a still lowervalue; the NOR circuit will operate correctly in anysituation if each of the switching transistors has thecorrect value of fJ to suit the load transistor.

If the load transistor were to be replaced bya diffused resistor,a widely -used integrated-circuit element, the surface area of thisresistor would be much larger than that of the load transistor.The resistance between source and drain of a MOS switchingtransistor of minimum dimensions (IV = 1= 10 fl.m) is severaltens of kn. This means that a load resistance of several hundred

1970, No. 7/8/9 DIGITAL INTEGRATED CIRCUITS WITH MOSTS 281

kn should be used to give the correct voltage division. A diffusedresistor ofthis value would be about 10mm longand 10 [Lmwide,whereas the corresponding load transistor with the same widthis only 0.2 mm long. Although the load. transistor has the ad-vantage of being small it has the disadvantage that the full supplyvoltage can never be obtained at the output of the circuit, sincethe threshold voltage of the load transistor is always lost. An-other disadvantage is that the response of the circuit with theload transistor is slower than when a diffused resistor is used.However, the most important feature is the extra space gainedon the chip.

The maximum switching frequency

The maximum permissible switching frequency of aNOR circuit is determined by the speed at which theoutput voltage switches over, and hence by the rate atwhich the capacitor connected to this output is chargedup. Of course, we must consider the worst case here,i.e. the transition from 0 to I, at which the switchingtransistors stop conducting and the output capacitor istherefore only charged up by the load transistor.

In a logic circuit the load on the output of a NORwill usually be several inputs of other NOR circuits.Here we shall take the simplest case where the only loadon the NOR is a single input of another NOR (e.g.input A in fig. 3a), so that the load is determined mainlyby the capacitance Cl of this input. Then the chargingcurrent Id4 sul is equal to tfJ4(Vdd - Vo - Vlh4)2,and is therefore also equal to CldVo/dt. Fromthe differential equation obtained by equating thesetwo expressions it can be shown that the RC timeconstant is proportional to CI/fJ4, and hence toCf.2ft2/p,.

Since the value of IJ( is already fixed, we must makeft small to be able to reach a high switching frequency.The channels in the switching transistors must there-fore be as short as possible and p, must be as large aspossible.

A much more unfavourable situation is found whenthe output of a NOR gate is not connected to anotherNOR circuit but to a point outside the integrated cir-cuit. The load capacitance is then usually determinedby the printed wiring of the board on which the inte-grated circuit is mounted. This wiring capacitance mayeasily be 1000 times larger than the input capacitanceof a NOR (a few tens ofpF against a few tens of fF;I fF = 10-15 F), and consequently the switching fre-quency for the logic circuit as a whole would be 1000times lower. Measures therefore have to be taken tokeep the RC product as small as possible. This is doneby using larger load transistors for the final NOR cir-cuit connected to this high capacitance, which make thecurrent 100 times greater than in the earlier circuits.The resistance of the load transistor in this circuit isthen only 1/100 of the original value, so that the RCproduct at the outputis now not 1000 times larger but

only ID times. The switching transistors in the laststage must of course be made larger in the same way,and this in turn gives a 100 times greater capacitiveload for the penultimate stage. To maintain a reason-able RC time constant the current through this stagemust therefore be increased as well, say by' a factor of10, so that larger transistors are also necessary here.The output stages of a 'circuit thus take up a relativelylarge amount of space on the chip; in fact it may hap-pen that no transistors at all of minimum dimensionscan be used in a small circuit.

MOS shift registers

1t can be seen from the above that MOS transistorsare most suitable for use in integrated circuits with asmall number of outputs. This is the case, for example,in stores with a fixed information content (read-only.stores), in "scratch-pad" stores and in shift registers.A shift register consists of a sequence of bistable cir-cuits, or cells whose information content, i.e. the stateof the individual cells, moves up one place when a shiftpulse or a combination of pulses is applied. Thus,information supplied to the input of the first cell ap-pears, after a number of shift pulses, at the output ofthe last cell of the register. Shift registers are widelyused as storage elements in the arithmetic unit of acomputer.

A distinction is made between static and dynamicshift registers. In static shift registers the informationcontent of the register is stored for an unlimited timeafter a shift pulse. In dynamic shift registers the infor-mation content is soon lost and therefore has to berepeatedly replenished. The shift pulses must con-sequently be repeated at a particular minimum fre-.quency, and this means that the information in adynamic shift register can never be kept in the sameplace. Another disadvantage of dynamic shift registersis that they require a more complex combination ofshift pulses than a static type: On the other hand, adynamic shift register is a great deal faster than a staticone, and its dissipation is also much lower. Moreover,in integrated-circuit form a dynamic shift register canhave a greater, packing density than a static shiftregister.

The static shift register

Fig. 8a gives the diagrain of a static shift-register cellbuilt with MOS transistors .. The cell consists of abistable circuit (or flip-flop) formed by two invertersTrl-Tr2 and Tra-Tr« coupled to form a.loop by meansof Tr6 and Tr7. The capacitors Cl and Cz, which playan essential part in the operatien of the cell, are formedby the capacitances between the gates of Tri and Traand the substrate, and by some stray capacitances. The

282 PHILlPS TECHNICAL REVIEW ' VOLUME 31

output voltage Vo represents the information content this zero voltage (i.e. Cl is not charged). TrI then passesof the cell. States 0 and I correspond, as in the inverter . no current, so that point A is negative, and this nega-circuit, to the zero level (Vo between 0 volts and V1hl) " tive voltage appears via TI', at the gate of Tr3 (i.e. C:~and the negative level (Vo = Vdd - Vth4). The infor- is' negatively charged); Tr3 passes current, so that Vomation in the preceding cell of the register is presented is held at the zero level. The two inverters are thusas a voltage VI at the input of the cell. The gate signals cross-coupled via Tr6 and Tr-i so that the output(/Ji, (/J2 and (/J3, consisting of shift-pulse trains (fig. 8b) voltage remains unaltered.are also fed to the circuit; the pulses (/J2 and (/J3 differ At the instant when the shift pulse epI arrives theonly in the steepness of their leading edges. Whenever' sequence of events is as follows. ep2 and ep3 go to thea combination of shift pulses arrives, the information zero level, so that Tr6 and TI', no longer conduct andcontent of the previous cell is taken over; in other the cross-coupling is broken. The output voltage, how-words, the voltage Vo assumes the level of Vi. ever, is maintained because the capacitor C2 is nega-

tively charged and Tr3 therefore continues to pass cur-rent. Since epI has become negative. Tr5 starts to con-duct. Assuming that the content of the preceding cellis I, then Cl will become negatively charged via Tr5,so that TrI also starts to cond uct. If (/JI returns to thezero level, Tr5 becomes non-conductive again, butthe negative voltage on Cl remains and TrI continuesto conduct. At the same time ep2 and (/J3 go negativeagain, so that Tr6 and TI', agairi start to conduct. Sincethe leading edges of these pulses are not equally steep.Tri starts to conduct somewhat earlier, so that C 2

discharges first through this transistor and TrI; as aresult, Tr3 stops conducting and Vo becomes negative.Meanwhile Tr6 also starts to conduct and the cross-coupling is restored, but now with a negative outputvoltage. with Cl negatively charged and C2 discharged.The information can now be stored again for an un-limited time.

The principle of this cell is thus fairly simple. Duringthe shifting process the cross-coupling is broken; theold information is held at the output by the capacitorC2, which keeps the inverter Tr3-Tr.J in its former state.The new information is meanwhile applied to Ct,causing Tri-Tr-. to assume the new state. Next, C2 israised to the new voltage (via Tr,), so that Tr3-Tr4 alsoassume the new state, and the cross-coupling is thenrestored through Tr6.

During the transfer of information a capacitivestorage is used twice. The capacitor Cl need only retainthe charge during the leading edge of (/J3, that is to sayuntil the cross-coupling is restored, while C2 must holdthe charge during the time that (/J2 and (/J3 are at thezero level. Both capacitors can only discharge throughthe leakage current of the P-N junctions of Tr6 and Tr-i.At room temperature the time constant of this dis-charge can have a value of a few tens of milliseconds ;if we compare this with the conventional pulse dura-tion of I to 20 fLs,we see that the storage action of thecapacitors is amply sufficient.

The maximum permissible frequency of the shiftpulses depends on the speed at which the circuitchanges state. This speed is determined by the time

Q

T

0~1 0 0

0

Q <1>2 1 =-oJ Il__

<1>3 ~ =-oJ \.... re-f

Fig. 8. a) Diagram of a cell of a static shift register. Tq-Tr2 andTr3-Tr4 form two 'inverter circuits, which are coupled to form aclosed loop by means óf Tr« and Tr7. The level of Vo (zero ornegative) is regarded as the "state" of the cell; VI indicates thestate of the preceding cell. b) The control (gate) signals r[Jl, r!J2

and r[J3 form a train of shift pulses. The information at the inputis transferred to the output byeach group of three pulses.

Fig. 90 gives a photograph of a 64-bit static shiftregister built up from cells of the type shown in fig. 80.An idea of the way in 'which the various componentsare joined together to form a circuit can be obtainedfrom fig. 9b, which illustrates a single cell from theregister; this is the cell that can be seen at the upperleft of the photograph.The cell works as follows. In the situation where (/JI

is at zero level (see fig. 80) and (/J2 and (/J3 are negative,Tr5 passes no current while Tr6 and Th are both con-ducting. Assuming that the output voltage Vo is at thezero level, then the gate of TrI, through Tr6, is also at

1970, No. 7/8/9 DIGITAL JNTEGRATED CIRCUITS WITH MOSTS 283

~-~~~~~~-{~~I I 'bl

_j:L I L __ J, ,·1 ~d: : --0, ,

L _

bI ,

'2', II ,,

Fig. 9. a) A static shift register (64 bits) using the cell shown in fig. Sa. The circuitcontains 458 components and measures 1.15 by 2.3 mm. The blue-grey strips are thescr ibed lines along which the crystal wafer can be broken to separate the circuits fromeach other. In the blue regions the upper layer consists of oxide, in the white regionsit consists of aluminium.b) Sketch of a single cell from the shift register. The areas covered with oxide areshaded; the shading is light where there is only substrate material under the oxide,and dark where there is a diffused region below the oxide. The areas where aluminiumhas been deposited by evaporation are left white, whatever is beneath them. The solidlines in the aluminium indicate boundaries between diffused regions and substratematerial; the dashed lines indicate regions with a thin oxide film (these are mostlythe isolation layers under the gate electrodes). These boundaries can also be seen onthe photograph, since there is a difference in height here. The contact windows areshown cross-hatched; these are the locations where the aluminium layer makes contactwith an underlying diffused region of source or drain. The various transistors inthe diagram are indicated by their number, placed in the channel.

A number of these cells are placed side by side, and the various signals are appliedto the strips of aluminium, which are clearly visible in the photograph. The sources ofTr i and Tra are earthed by connecting the central diffused layer with the earthedsubstra te at a point which lies outside this diagram.

needed to charge Cl or C2· In the transition from state 1 to state 0,described above, Cl must be charged via transistor Tr4 of the previouscircuit. During the transition from I to 0, C2 must be charged via Trzand Tri. Since Tr2 and Tr4 are load transistors, they have a fairly highresistance; however, when they are combined with switching transistorsof minimal dimensions (Cl and C2 are then about 50 f'F), the RC timeconstant for charging the capacitors can still be as small as 50 ns. Inthe situation illustrated, i.e. the transfer of information between twosuccessive cells in the shift register, this gives a maximum shift-pulserepetition frequency of I MHz. The speed of the register as a wholeis of course adversely affected by the output stage in the same way asdescribed for the NOR gate; in practice the maximum frequency wouldbe about 250 kHz.

284 PHILlPS TECHNICAL REVIEW

The dynamic shift register

Fig. lOa shows the diagram of a dynamic shiftregister cell built with MOS transistors. The level of .the output voltage Vo again indicates the state of thecell, and V;the state of the preceding cell. Cl and C2

are the capacitances of the gates of TrI and Tr4, Cl' isthe capacitance Cl of the next cell. There are four shiftsignals (/Jl, (/J2, (/Ja arid (/J4 (fig. lOb), consisting ofnega-tive pulse trains; after each group of four shift pulsesthe input voltage is taken over by the output. rn fig. lOait can be seen that both (/Jl and (/Ja are fed to two pointsof the circuit. Fig. 11a gives a photograph of a part of adynamic shift register in which this cell is used; fig. Il bagain shows a diagram of one of the cells from thisregister.

To explain the operation of the cell we start from thesituation where Vi is negative; TrI is then conducting.At the moment when the first shift pulses arrive. (/Jl

and (/J2 gÇ>negative, so that Trz and Tra also start toconduct. From the source supplying the voltage (/JI

the capacitor C2 will now be charged to a negativevoltage via Tra and the series arrangement of TrI andTr». The voltage CPI then returns to zero, but (/J2 re-mains negative. As a result, Tra stops conducting butTrI and Tri continue to pass current, and since the gateof TrI is now at the zero level, Cz discharges throughthese transistors. When cp'!. also returns to zero, C'2 isthus nearly discharged. Now when the shift pulses of(/Ja and (/J4 arrive, Tr5 and Tr6 start to conduct but Tr4remains non-conducting because C2 is discharged.Ca is now charged (through Tr6 only). but when (/J3

returns to zero it can no longer discharge. Thus. when(/J4 also goes back to zero, a negative voltage remainsat the output.

If the input voltage is at the zero level. Cs cannotdischarge because TrI does not go into conduction.Consequently C2 remains negative, which then enablesCa to discharge, and the output voltage goes to zero.We see' that in both cases the voltage that was at theinput is transferred toward the output after four shiftpulses. Since four phases can be distinguished in thisprocess, a circuit of this type is known as a four-phaseshift register.

The dynamic shift register of fig. lOa is based on thestorage action of the capacitors Cl and C2. Thesecapacitors, however, discharge as a result of the leakagecurrents in the P-N junctions of the correspondingtransistors, and since the dynamic circuit has no cross-coupling as in the static type, the information would begradually lost. To prevent this, the loss of charge isregularly compensated by the signals (/JI and CPa, andthis means that the whole shift-pulse pattern must berepeated at a particular minimum frequency. The re-gister therefore continues to transfer the information.

Q

VOLUME 31

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Fig. 10. a) Diagram of a cell from a dynamic four-phase shiftregister. The output voltage Vn indicates the state of the cell,and Vi the state of the preceding cell. bl The gate signals (!>l,(/>2, (/>3 and (/>., consist of negative pulse trains: the informationat the input is transferred to the output byeach group of fourof these shift pulses.

The minimum frequency at which the shift pulses haveto be suppl ied depends on the magnitude of the capaci-tances and leakage currents. Since leakage currents ofP-N junctions are involved the repetition frequency istemperature dependent ; at room temperature a fre-quency of 40 or 50 Hz may be high enough. but forevery JO degrees increase in temperature the minimumfrequency required increases by a factor of 2.

For the static shift registers MOS transistors of dif-ferent dimensions are needed (switching and load tran-sistors) in order to obtain the desired voltage divisionin the inverter circuits. This is not necessary for thedynamic registers, and switching transistors of mini-mum dimensions can therefore be used. The capaci-tances Cl and C'!. in fig. lOa have about the samevalue as those in the static shift register in fig. 8a, butduring the transfer process they are charged up throughtransistors whose resistance is a tenth of that of theload transistors in the static register. Because of thisthe maximum permissible shift frequency for thedynamic shift register is an order of magnitude higherthan for the static type; it is about JO MHz. Anotherconsequence of only using switching transistors is thatthe component density on the chip is higher in dynamicregisters.

1970, No. 7/8/9 DIGITAL INTEGRATED CIRCUITS WITH MOSTS 285

o 0- :...1...1...: I.:.l.: ....I..: .....l1-~'W.QJOW P1lQ.II Ö~ I1 t""!"'"'I" 1 t"'I ) l.""'P-r".0 • •..,. - 1.1 :T'" ..,...

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Fig. 11.1/) Part of a dynamic shift register built up with cells of the type shown in fig. 101/.h) Sketch of one cellof the shift register. The various areas are indicated in the same wayas in fig. 9h.

The cells are located in a rowan the crystal wafer and the various voltages are appliedto the aluminium strips. The photograph shows four such rows of cells one above the other,the strips for the voltages CP, and CP3 being connected to adjacent rows; the transistor Tr«in the sketch therefore belongs to a cell in a following row.

The dynamic register also dissipates less heat. In thestatic shift register there is always current flowingthrough one of the two inverter circuits, and the dissi-pation per cell is 2 mW. In the dynamic shift register nocurrent can flow direct to earth; energy is only dissi-pated when the capacitors are charged. The dissipationis therefore substantially lower than in the static case,and moreover it is proportional to the frequency of theshift pulses. The dissipation per cell is 50 iJ.W/MHz;even at a pulse frequency of 5 MHz the dissipationper cell is therefore no more than 250 ij.W, wh ich is agreat deal better than the 2 mW per cell of the staticregister.

As we noted earlier, there is a penalty to be paid forthese advantages: the information cannot be kept In

the same place and a more complex combination ofshift pulses is required.

Summary. The source and drain in MOS transistors are isolatedbya depletion layer from the substrate, so that no isolation dif-fusions are required. MOS transistors can therefore be packedvery densely on a crystal wafer. Since MOSTs also dissipate littleheat, they are very suitable for use in integrated circuits. After abrief description of the technology, some examples of such cir-cuits are given. The first is a logic circuit: the NOR gate, in whichthe MOS transistors are used as switches and also as resistors:the MOST is smaller than a diffused resistor of the same resis-tance. The other examples, a static and a dynamic shift register,make use of the specific advantages of the MOST: its very highinput impedance and the fact that the current through a MOSTcan flow in both directions. A cell cf the static shift register con-sists of a bistable circuit; the cell of the dynamic shift register isbased on the storage action of a capacitor. In the dynamic shiftregister there is no cross-coupling to prevent the informationfrom being lost, and the voltage on the capacitor therefore hasto be continuously replenished by the shift pulses (4 pulses percycle). This means that the information in the dynamic registermust be kept moving through at a specific minimum frequency.Compared with the static type the dynamic register has the twoadvantages ofa maximum pulse frequency that is 10 times higher(10 MHz against I MHz), which is possible because only MOSTsof minimum dirnensions are used, and a lower dissipation(50 [.LW/MHz per cell as against 2 mW per cell).