Digital Integrated Circuits A Design Perspectivej.guntzel/ine5442/memory-1.pdf · 2010-12-02 · ©...
Transcript of Digital Integrated Circuits A Design Perspectivej.guntzel/ine5442/memory-1.pdf · 2010-12-02 · ©...
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Digital Integrated
Circuits
A Design Perspective
Semiconductor Memories (Part 1)
Reference: Digital Integrated Circuits,
2nd edition, Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic
Disclaimer: slides adapted for
INE5442/EEL7312 by José L. Güntzel
and Luiz dos Santos from the book´s
companion slides made available by the
authors.
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Lecture Summary
Memory Classification
Memory Architectures
The Memory Core (ROM Memories)
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Memory Timing: Definitions
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Semiconductor Memory Classification
Read-Write Memory Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E 2 PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N 2 2
Word N 2 1
Storage cell
M bits
N words
S 0
S 1
S 2
S N 2
S N – 1
Input-Output ( M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
Decoder
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Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N 2 2
Word N 2 1
Storage cell
M bits M bits
N words
S 0
S 1
S 2
S N 2
A 0
A 1
A K – 1
K = log 2 N
S N – 1
Word 0
Word 1
Word 2
Word N 2 2
Word N 2 1
Storage cell
S 0
Input-Output ( M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals K = log 2 N
Decoder reduces the number of select signals
Input-Output ( M bits)
Decoder
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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to rail-to-rail amplitude
Selects appropriate word –
–
–
+
4096 rows x 2048 cells
212 rows x 28 8-bit words
4096 rows x 256 8-bit words
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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to rail-to-rail amplitude
Selects appropriate word –
–
–
+
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Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
–
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Block Diagram of 4 Mbit SRAM
Subglobal row decoder Global row decoder Subglobal row decoder
Block 30 Block 31
128 K Array Block 0
Block 1
Clock generator
CS, WE buffer
I/O buffer
Y -address buffer
X -address buffer
x1/x4 controller
Z -address buffer
X -address buffer
Predecoder and block selector Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
Local row decoder [Hirose90]
32 128-bit
blocks (selected by a
single row address)
Local row decoder
Sub-global
row decoder
Global row
decoder
4Mbit = 32 blocks x 128Kbit = 32 blocks x 1024 rows x 128 columns Z = 5, Y = 7, X = 10
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Contents-Addressable Memory
Address Decoder
I/O Buffers
Commands
2 9 Validity Bits Priority Encoder
Address Decoder
I/O Buffers
Commands
2 9 Validity Bits Priority Encoder
Ad
dre
ss D
eco
de
r
Data (64 bits)
I/O
Bu
ffe
rs
Comparand
CAM Array2
9 words 3 64 bits
Mask
Control Logic R/W Address (9 bits)
Co
mm
an
ds
29 V
alid
ity B
its
Prio
rity
En
co
de
r
x
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Memory Timing: Approaches
DRAM Timing Multiplexed Addressing
SRAM Timing Self-timed
DRAM external timing signals:
RAS= Row Address Strobe
CAS=Column Address Strobe
SRAM: no external timing signals!
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Read-Only Memory Cells
WL
BL
WL
BL
1 WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
MOS ROM1: BL must be resistively clamped to ground
MOS ROM2: BL must be resistively clamped to Vdd
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MOS OR ROM
WL [0]
V DD
BL [0]
WL [1]
WL [2]
WL [3]
V bias
BL [1]
Pull-down loads
BL [2] BL [3]
V DD
To reduce area
overhead,
supply voltage
lines are shared
between
adjacent rows
Data read
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Data read
MOS NOR ROM
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
V DD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
Each column is a pseudo-NMOS (WLs are the inputs)!
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MOS NOR ROM Layout
Programmming using the
Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5l x 7l)
GND
GND
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
0 1 0 0
1 0 0 1
0 1 0 1
0 0 0 0
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MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11l x 7l)
Programming using
the Contact Layer Only
WL[0]
WL[1]
WL[2]
WL[3]
GND
GND
BL[0] BL[1] BL[2] BL[3]
1 0 1 1
0 1 1 0
1 0 1 0
1 1 1 1
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MOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
V DD
Pull-up devices
BL [3] BL [2] BL [1] BL [0]
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MOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROM
drastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8l x 7l)
Programmming using
the Metal-1 Layer Only WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
0 1 0 0
1 0 0 1
0 1 1 1
0 0 0 0
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NAND ROM Layout
Cell (5l x 6l)
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
Programmming using
Implants Only
No contacts at all!
BL[0] BL[1] BL[2] BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
0 1 0 0
1 0 0 1
0 1 0 1
0 0 0 0
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Equivalent Transient Model for MOS NOR ROM
Word line parasitics Wire capacitance and gate capacitance
Wire resistance (polysilicon)
Bit line parasitics Resistance not dominant (metal)
Drain and Gate-Drain capacitance
Model for NOR ROM V DD
C bit
r word
c word
WL
BL
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Equivalent Transient Model for MOS NAND ROM
Word line parasitics Similar to NOR ROM
Bit line parasitics Resistance of cascaded transistors dominates
Drain/Source and complete gate capacitance
Model for NAND ROM V DD
C L
r word
c word
c bit
r bit
WL
BL
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Precharged MOS NOR ROM
PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
V DD
BL [1]
Precharge devices
BL [2] BL [3]
GND
pre f
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ROM memories: user perspective
Application specific ROMs
Designer can use any mask layer to program the device
Commodity ROM chips
Mask programmable (one layer only) – Late processing phase: either contact or metal
Variant: only a fraction of die is mask programmable (compatible with SoC approach)
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Conclusions
Large variety of memory types
according to:
Function
Volatility
Access pattern
I/O (ports)
Application
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Conclusions
Memory structure varies with size
Unidimensional array (of words)
Bidimensional array of words
–Rows and colums
Tridimensional arrays of words
–Rows, columns, and blocks
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Conclusions
ROM cores vary in
Structure (OR, NOR, NAND)
Programmable layers –Active area,
–Contact
– Threshold lowering implant
Pull-up mechanism –PMOS transistor load
–PMOS precharging transistors
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Digital Integrated
Circuits
A Design Perspective
Semiconductor Memories (Part 1)
Reference: Digital Integrated Circuits,
2nd edition, Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic
Disclaimer: slides adapted for
INE5442/EEL7312 by José L. Güntzel
and Luiz dos Santos from the book´s
companion slides made available by the
authors.